RT9173PL5 [RICHTEK]
Peak 3A Bus Termination Regulator; 峰值3A总线终端稳压器
| 型号： | RT9173PL5 |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Peak 3A Bus Termination Regulator |
| 文件： | 总13页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT9173/A
Peak 3A Bus Termination Regulator
General Description
Features
z Support Both DDR 1 (1.25VTT) and DDR 2
The RT9173/A regulator is designed to convert voltage
supplies ranging from 1.6V to 6V into a desired output
voltage which adjusted by two external voltage divider
resistors. The regulator is capable of sourcing or sinking
up to 3Aof peak current while regulating an output voltage
to within 2% (DDR 1) and 3% (DDR 2) or less.
(0.9VTT) Requirements
z SOP-8, TO-252-5 and TO-263-5 Packages
z Capable of Sourcing and Sinking 3A Peak Current
z Current-limiting Protection
z Thermal Protection
z Integrated Power MOSFETs
The RT9173/A, used in conjunction with series termination
resistors, provides an excellent voltage source for active
termination schemes of high speed transmission lines as
those seen in high speed memory buses and distributed
backplane designs. The voltage output of the regulator can
be used as a termination voltage for DDR SDRAM.
z Generates Termination Voltages for SSTL-2
z High Accuracy Output Voltage at Full-Load
z Adjustable VOUT by External Resistors
z Minimum External Components
z Shutdown for Standby or Suspend Mode
Operation with High-impedance Output
z RoHS Compliant and 100% Lead (Pb)-Free
Current limits in both sourcing and sinking mode, plus on-
chip thermal shutdown make the circuit tolerant of the
output fault conditions.
Applications
z DDR Memory Termination
z Active Termination Buses
z Supply Splitter
Ordering Information
RT9173/A
Package Type
M5 : TO-263-5
L5 : TO-252-5
S : SOP-8
Pin Configurations
(TOP VIEW)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
5
4
3
2
1
VOUT
REFEN
VCNTL (TAB)
GND
3A Sink & Source
1.5A Sink & Source
VIN
Note :
TO-263-5 (RT9173A)
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
5
4
3
2
1
VOUT
REFEN
VCNTL (TAB)
GND
`Suitable for use in SnPb or Pb-free soldering processes.
`100%matte tin (Sn) plating.
VIN
TO-252-5 (RT9173A)
8
7
6
5
VIN
GND
VCNTL
VCNTL
VCNTL
VCNTL
2
3
4
REFEN
VOUT
SOP-8 (RT9173)
DS9173/A-18 March 2007
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1
RT9173/A
Typical Application Circuit
V
= 3.3V
= 2.5V
CNTL
V
IN
R
TT
R
VIN
VCNTL
VOUT
1
C
C
CNTL
IN
RT9173/A
REFEN
2N7002
C
C
OUT
SS
EN
GND
R
2
R
DUMMY
R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω
COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition
RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present
CSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF
Test Circuit
2.5V
VIN
3.3V
VCNTL
VOUT
RT9173/A
V
OUT
C
1.25V
REFEN
V
GND
OUT
I
L
Figure 1. Output Voltage Tolerance, ΔVLOAD
3.3V
2.5V
A
VIN
RT9173/A
REFEN VOUT
VCNTL
1.25V
V
OUT
C
1.25V
0.2V
0V
GND
OUT
R
L
V
R
and C
OUT
L
Time deleay
Figure 2. Current in Shutdown Mode, ISHDN
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DS9173/A-18 March 2007
RT9173/A
3.3V
2.5V
VIN
VCNTL
RT9173/A
V
OUT
C
1.25V
REFEN
VOUT
A
V
GND
OUT
I
L
Figure 3. Current Limit for High Side, ILIMIT
Power Supply
with Current Limit
2.5V
3.3V
A
VIN
VCNTL
I
L
RT9173/A
REFEN VOUT
V
OUT
C
1.25V
V
GND
OUT
Figure 4. Current Limit for Low Side, ILIMIT
3.3V
2.5V
VIN
VCNTL
VOUT
RT9173/A
V
OUT
C
1.25V
REFEN
V
REFEN
GND
0.2V
OUT
R
L
V
1.25V
V
OUT
0V
V
V
would be low if V
< 0.2V
> 0.8V
OUT
OUT
REFEN
would be high if V
REFEN
R
and C
OUT
L
Time deleay
Figure 5. REFEN Pin Shutdown Threshold, VTRIGGER
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RT9173/A
Functional Pin Description
Pin Name
VIN
Pin Function
Power Input Voltage
Ground
GND
VCNTL
REFEN
VOUT
Gate Drive Voltage
Reference Voltage Input and Chip Enable
Output Voltage
Function Block Diagram
VCNTL
VIN
Current
Limiting Sensor
REFEN
VOUT
GND
CNTL
Thermal
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RT9173/A
Absolute Maximum Ratings
z Input Voltage------------------------------------------------------------------------------------------------------------ 7V
z PowerDissipation ----------------------------------------------------------------------------------------------------- Internally Limited
z ESD Rating ------------------------------------------------------------------------------------------------------------- 2kV
z Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
z Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------------- 260°C
z Power Dissipation, PD @ TA = 25°C
TO-263-5 ----------------------------------------------------------------------------------------------------------------- 1.923W
TO-252-5 ----------------------------------------------------------------------------------------------------------------- 1.471W
SOP-8 -------------------------------------------------------------------------------------------------------------------- 0.625W
z Package Thermal Resistance (Note 3)
TO-263-5, θJC ---------------------------------------------------------------------------------------------------------- 7.7°C/W
TO-252-5, θJC ---------------------------------------------------------------------------------------------------------- 8°C/W
SOP-8, θJC -------------------------------------------------------------------------------------------------------------- 23.2°C /W
TO-263-5,θJA ------------------------------------------------------------------------------------------------------------ 52°C/W
TO-252-5, θJA ----------------------------------------------------------------------------------------------------------- 68°C/W
SOP-8, θJA -------------------------------------------------------------------------------------------------------------- 160°C/W
Electrical Characteristics
(VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10μF (Ceramic), TA = 25°C, unless otherwise specified.)
Parameter
Symbol
Test Conditions
Min
-20
--
Typ
Max Units
Output Offset Voltage
V
OS
IOUT = 0A, Figure 1 (Note 1)
0
20
mV
I : 0A → 1.5A, Figure 1
0.8/1.2 2/3
0.8/1.2 2/3
L
Load Regulation (DDR 1/2)
ΔV
LOAD
%
I : 0A → -1.5A
--
L
V
V
1.6 2.5/1.8
--
6
Input Voltage Range (DDR 1/2)
(Note 2)
Keep V
≥ V on operation power
IN
CNTL IN
V
on and power off sequences
No Load
--
--
--
3.3
6.5
50
CNTL
CNTL
SHDN
Operating Current of VCNTL
Current In Shutdown Mode
Short Circuit Protection
Current limit
I
I
10
90
mA
V
< 0.2V, R = 180Ω, Figure 2
μA
REFEN
L
I
Figure 3,4
3.0
--
--
A
LIMIT
Over Temperature Protection
Thermal Shutdown Temperature T
Thermal Shutdown Hysteresis
Shutdown Function
3.3V ≤ V
≤ 5V
125
--
150
50
--
--
°C
°C
SD
CNTL
Guaranteed by design
V
Output = High, Figure 5
Output = Low, Figure 5
0.8
--
--
--
--
TRIGGER
Shutdown Threshold Trigger
V
V
0.2
TRIGGER
Note 1. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN
.
Note 2. For safely operate your system, the 3.3V rail MUST be tied to VCNTL rather than 5V rail, especially for the new part of
RT9173ACL5.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board (single Layers,
1S) of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the on the center of VCTRL pins (Lead
6 & 7) for SOP-8 packages, the center of heat sink (tab) for TO-252-5 and TO-263-5 packages.
DS9173/A-18 March 2007
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RT9173/A
Typical Operating Characteristics
Sourcing Current (Peak) vs. Temperature
Sinking Current (Peak) vs. Temperature
8.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
7.0
6.0
5.0
4.0
3.0
2.0
VCNTL = 3.3V
VCNTL = 3.3V
VIN = 2.5V
VIN = 2.5V
VOUT = 1.25V
1.0
0.0
VOUT = 1.25V
-40
-20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100 120
Temperature
(°C)
Temperature
(°C)
Turn-On Threshold vs. Temperature
Turn-On Threshold vs. Temperature
700
650
600
550
500
450
400
700
650
600
550
500
450
400
VCNTL = 3.3V
VCNTL = 5.0V
VIN = 2.5V
VIN = 2.5V
-40
-20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80 100 120
Temperature (°C)
Temperature
(°C)
1.25VTT @ 1.5A Transient Response
1.25VTT @ 3A Transient Response
100
50
0
100
50
0
VIN = 2.5V
VREFEN
VCNTL = 3.3V
Swing Frequency = 1KHz
VIN = 2.5V
VREFEN
VCNTL = 3.3V
Swing Frequency = 1KHz
=
=
-50
-50
≈
≈
≈
≈
2
1
4
2
0
0
-1
-2
-2
-4
Time (250us/Div)
Time (250us/Div)
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DS9173/A-18 March 2007
RT9173/A
0.9VTT @ 1.5A Transient Response
0.9VTT @ 3A Transient Response
100
50
0
100
50
0
VIN = 1.8V
VCNTL = 3.3V
VIN = 1.8V
VREFEN = 0.9V
VCNTL = 3.3V
Swing Frequency = 1KHz
VREFEN = 0.9V
Swing Frequency = 1KHz
-50
-50
≈
≈
≈
≈
2
1
4
2
0
0
-1
-2
-2
-4
Time (250us/Div)
Time (250us/Div)
RDS(ON) vs. Temperature
RDS(ON) vs. Temperature
0.32
0.31
0.30
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.31
0.30
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
VIN = 0.9V
VIN = 0.9V
VIN = 0.85V
VIN = 0.85V
VIN = 0.8V
VIN = 0.8V
VCNTL = 5.0V
VCNTL = 3.3V
VREFEN = 1.0V
VREFEN = 1.0V
25 35 45 55 65 75 85 95 105 115 125
25 35 45 55 65 75 85 95 105 115 125
Temperature
(°C)
Temperature
(°C)
Output Short-Circuit Protection
Output Short-Circuit Protection
12
10
8
12
10
8
Sink
VIN = 2.5V
CNTL = 3.3V
Source
VIN = 2.5V
CNTL = 3.3V
V
V
VREFEN = 1.25V
VREFEN = 1.25V
6
4
6
4
2
2
0
0
-2
-4
-2
-4
Force the output shorted to VDDQ
Time (5ms/Div)
Force the output shorted to ground
Time (5ms/Div)
DS9173/A-18 March 2007
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RT9173/A
Application Information
Internal Parasitic Diode
Thermal Consideration
Avoid forward-bias internal parasitic diode, VOUT to V
,
RT9173/A regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed absolute maximum
operation junction temperature 125°C. The power
dissipation definition in device is :
L
CNT
and VOUT to VIN, the VOUT should not be forced some
voltage respect to ground on this pin while the VCNTL or
VIN is disappeared.
Consideration while Designs the Resistance of
Voltage Divider
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
Make sure the sinking current capability of pull-downNMOS
if the lower resistance was chosen so that the voltage on
VREFEN is below 0.2V.
In addition, the capacitor and voltage divider form the low-
pass filter. There are two reasons doing this design; one is
for output voltage soft-start while another is for noise
immunity.
PD(MAX) = ( TJ(MAX) -TA ) /θJA
Where TJ(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance. The
junction to ambient thermal resistance θJA highly depends
on IC package, PCB layout, and the rate of surroundings
airflow. θJA for SOP-8 package is 160°C/W and TO-263-5
package is 52°C/W on standard JEDEC 51-3 (single layer,
1S) thermal test board. The maximum power dissipation
at TA = 25°C can be calculated by following
How to reduce power dissipation on Notebook PC or
the dual channel DDR SDRAM application?
In notebook application, using RichTek's Patent
"Distributed Bus Terminator Topology" with choosing
RichTek's product is encouraged.
Distributed Bus Terminating Topology
Terminator Resistor
formula :
R0
PD(MAX) = (125°C - 25°C) / (160 °C/W)= 0.625W (SOP-8
package)
BUS(0)
R1
BUS(1)
R2
R3
R4
R5
R6
R7
R8
R9
VOUT
RT9173/A
BUS(2)
PD(MAX) = (125°C- 25°C) / (52 °C/W)= 1.923W (TO- 263-
5 package )
BUS(3)
BUS(4)
Since the multiple VCTRL pins of the SOP-8 package are
internally fused and connected to lead frame, it is efficient
to dissipate the heat by adding cooper area on VCTRL
footprint. Figure 7 shows the package sectional drawing
of SOP-8. Every package has several thermal dissipation
paths, as show in Figure 8, the thermal resistance
equivalent circuit of SOP-8. The path 2 is the main path of
thermal flow due to these materials thermal conductivity.
We define the center of multiple VCTRL pins are the case
point of the path 2.
REFEN
BUS(5)
BUS(6)
BUS(7)
VOUT
RT9173/A
BUS(8)
BUS(9)
RN
BUS(N)
RN+1
BUS(N+1)
Figure 6
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DS9173/A-18 March 2007
RT9173/A
θJA vs. Copper Area
Molding Compound
Lead Frame
100
90
80
70
60
50
40
30
Case Point
Die
Die Pad
Ambient
Molding Compound
Gold Wire
SOP-8
2S2P thermal test board
Lead Frame
Die Pad
0
10 20 30 40 50 60 70 80 90 100
Copper Area (mm2)
Figure 9. Thermal Resistance θJA vs. CopperArea of
Figure 7. The Package SectionDrawing of RT9173/A
SOP-8 Package
SOP-8 Packages
Thermal Resistance vs. Cooper Area
70
The thermal resistance θJA of IC package is determined by
the package design and the PCB design. However, the
package design has been decided. If possible, it's useful
to increase thermal performance by the PCB design. The
thermal resistance can be decreased efficiently by adding
copper under the main path of thermal flow on the package.
60
1S thermal test board
50
40
2S2P thermal test board
30
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. For RT9173/A package, the Figure 9 and
the Figure 10 show the thermal resistance θJA vs. copper
area of SOP-8 and TO-263-5 packages on single layer
(1S) and 4-layer (2S2P) thermal test board at TA = 25°C,
PCB copper thickness = 2oz.
20
10
TO-263-5
0
0
50
100 150 200 250 300 350 400
Cooper Area (mm2)
Figure 10. Thermal Resistance θJA vs. CopperArea of
TO-263-5 Packages
R
R
R
PCB
GOLD-LINE
LEAD FRAME
For example, as shown in Figure 9, RT9173/ASOP-8 with
10mm x 10mm cooper area on 4-layers (2S2P) thermal
test board at TA = 25°C, we can obtain the lower thermal
resistance about 45°C/W. The power maximum dissipation
can be calculated as :
path 1
Internally Fused
R
R
R
R
R
PCB
DIE
R
DIE-ATTACH
DIE-PAD
LEAD FRAME
Junction
Ambient
path 2
MOLDING-COMPOUND
PD(MAX) = (125°C - 25°C) / (45 °C/W) = 2.22W (SOP-8)
path 3
As shown in Figure 10, RT9173/A TO-263-5 with
15mm x 15mm cooper area on 4-layers (2S2P) thermal
test board at TA = 25°C, we can obtain the lower thermal
resistance about 29°C/W. The power maximum dissipation
Figure 8. Thermal Resistance Equivalent Circuit of
RT9173/ASOP-8 Package
DS9173/A-18 March 2007
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9
RT9173/A
can be calculated as :
PD(MAX) = (125°C - 25°C) / (29°C/W) = 3.45W (TO-263-5)
Figure 11 and Figure 12 of power dissipation vs. copper
area allow the designer to see the effect of rising ambient
temperature on the maximum power allowed.
Power Dissipation vs. Copper Area
100
2S2P thermal test
90
80
70
60
50
40
30
20
10
0
board
TA = 65°C
TA = 55°C
TA = 25°C
SOP-8
2.5 3
0
0.5
1
1.5
2
Power Dissipation (W)
Figure 11. PowerDissipation vs. CopperArea of SOP-8
Package
Cooper Area vs. Power Dissipation
400
2S2P thermal test
board
350
300
250
200
150
100
50
0
TA = 65°C
TA = 25°C
TO-263-5
3.5 4.5
TA = 55°C
0
0.5
1
1.5
2
2.5
3
4
Power Dissipation (W)
Figure 12. PowerDissipation vs. CopperArea of
TO-263-5 Package
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DS9173/A-18 March 2007
RT9173/A
Outline Dimension
C
D
U
B
V
E
L1
L2
b
e
b2
A
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
10.668
1.676
9.652
4.826
1.397
Min
Max
0.420
0.066
0.380
0.190
0.055
D
B
9.652
1.143
8.128
4.064
1.143
0.380
0.045
0.320
0.160
0.045
E
A
C
U
V
6.223 Ref.
7.620 Ref.
0.245 Ref.
0.300 Ref.
L1
L2
b
14.605
2.286
0.660
0.305
1.524
15.875
2.794
0.914
0.584
1.829
0.575
0.090
0.026
0.012
0.060
0.625
0.110
0.036
0.023
0.072
b2
e
5-Lead TO-263 Plastic Surface Mount Package
DS9173/A-18 March 2007
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RT9173/A
E
C2
R
b3
L3
T
V
S
D
H
L
b
P
L2
A
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
2.388
0.889
5.461
0.889
6.223
6.731
10.414
1.780
Min
Max
0.086
0.015
0.195
0.018
0.210
0.250
0.354
0.020
0.094
0.035
0.215
0.035
0.245
0.265
0.410
0.070
A
b
2.184
0.381
4.953
0.457
5.334
6.350
9.000
0.508
b3
C2
D
E
H
L
0.020 Ref.
L2
L3
P
0.508 Ref.
0.035
0.080
0.889
2.032
1.270 Ref.
5.200 Ref.
0.050 Ref.
0.205 Ref.
V
R
0.200
2.500
0.500
1.500
3.400
0.850
0.008
0.098
0.020
0.059
0.134
0.033
S
T
5-Lead TO-252 Surface Mount Package
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DS9173/A-18 March 2007
RT9173/A
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.050
5.791
0.400
5.004
3.988
1.753
0.508
1.346
0.254
0.254
6.200
1.270
0.189
0.150
0.053
0.013
0.047
0.007
0.002
0.228
0.016
0.197
0.157
0.069
0.020
0.053
0.010
0.010
0.244
0.050
J
M
8-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS9173/A-18 March 2007
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