RT9248A [RICHTEK]
Multi-Phase PWM Controller for CPU Core Power Supply; 多相PWM控制器，用于CPU核心供电
| 型号： | RT9248A |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Multi-Phase PWM Controller for CPU Core Power Supply |
| 文件： | 总14页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT9248A
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
The RT9248Ais a cost-effective multi-phase buckDC/DC
controller integrated with all control functions forGHz CPU
VRM. The RT9248A controls 2 or 3 buck switching stages
operating in interleaved phase set automatically. The multi-
phase architecture provides high output current while
maintaining low power dissipation on power devices and
low stress on input and output capacitors. The high
equivalent operating frequency also reduces the component
dimension and the output voltage ripple in load transient.
z Multi-Phase Power Conversion with Automatic
Phase Selection
z VRM9 & VRD10 DAC Output with Active Droop
Compensation for Fast Load Transient
z Smooth VCORE Transition at VID Jump
z Multi-Level VID125 Input for VRM9 & VRD10
Selection
z Power Stage Thermal Balance by RDS(ON) Current
Sense
z Hiccup Mode Over-Current Protection
z Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and
Soft-Start
RT9248Acontrols both voltage and current loops to achieve
good regulation, response & power stage thermal balance.
Precise current loop using RDS(ON) as sense component
builds precise load line for strict VRM DC & transient
specification and also ensures thermal balance of different
power stages. The settings of current sense, droop tuning,
VCORE initial offset and over current protection are
independent to compensation circuit of voltage loop. The
feature greatly facilitates the flexibility of CPU power supply
design and tuning.
z High Ripple Frequency Times Channel Number
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z Intel® Processors Voltage Regulator: VRM9 and VRD10
z Low Output Voltage, High CurrentDC-DC Converters
z Voltage Regulator Modules
TheDAC output of RT9248Asupports VRM9 & VRD10 by
VID125 multi-level input, precise initial value & smooth
VCORE transient at VID jump. The IC monitors the VCORE
voltage for PGOODand over-voltage protection. Soft-start,
over-current protection and programmable under-voltage
lockout are also provided to assure the safety of micro-
processor and power system.
Pin Configurations
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VID4
VID3
VID2
VID1
VID0
VCC
2
3
4
5
6
7
8
9
10
11
12
13
14
PWM1
PWM2
PWM3
NC
ISP1
ISP2
Ordering Information
VID125
SGND
FB
COMP
PGOOD
DVD
SS
RT
VOSS
RT9248A
ISP3
ISN
GND
ADJ
VDIF
VSEN
IMAX
Package Type
C : TSSOP-28
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Note :
TSSOP-28
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS9248A-06 March 2006
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1
Preliminary
RT9248A
Typical Application Circuit
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2
DS9248A-06 March 2006
Preliminary
RT9248A
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VOSS (Pin 14)
VID0 (Pin 5) & VID125 (Pin 6)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the offset value.
DAC voltage identification inputs. Tie VID125 to GND for
VRM9 or to VCC for VRD10. These pins are internally
pulled to 3.3V if left open.
IMAX (Pin 15)
Over-Current protection set.
SGND (Pin 7)
VSEN (Pin 16)
Connect this pin to the return pin of VCORE
.
Power good and over-voltage monitor input. Connect this
FB (Pin 8)
to the sense pin of VCORE
.
Inverting input of the internal error amplifier.
VDIF (Pin 17)
COMP (Pin 9)
This pin is being tied to VSEN pin internally.
Output of the error amplifier and input of the PWM
comparator.
ADJ (Pin 18)
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
PGOOD (Pin 10)
Power good open-drain output.
GND (Pin 19)
DVD (Pin 11)
IC ground.
Programmable power UVLO detection or converter enable
input.
ISN (Pin 20)
RDS(ON) current sense input from anyone of channel sense
components'GNDnode.
SS (Pin 12)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
ISP1 (Pin 23), ISP2 (Pin 22), ISP3 (Pin 21)
RDS(ON) current sense inputs for individual converter
channels. Tie this pin to the component's sense node.
RT (Pin 13)
Switching frequency setting. Connect this pin toGNDwith
a resistor to set the frequency.
NC (Pin 24)
No internal connection.
Frequency vs. RRT
450
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25)
400
350
300
250
200
150
100
50
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 2 channels, connect PWM3 high.
VCC (Pin 28)
IC power supply. Connect this pin to a 5V supply.
0
0
10
20
30
40
50
60
70
RRT (k Ω)
DS9248A-06 March 2006
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3
Preliminary
RT9248A
Function Block Diagram
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4
DS9248A-06 March 2006
Preliminary
RT9248A
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID3
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID2
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VID125 = H
No CPU
0.850V
0.875V
0.900V
0.925V
0.950V
0.975V
1.000V
1.025V
1.050V
1.075V
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
VID125 = L
No CPU
1.625V
1.650V
1.675V
1.700V
1.725V
1.750V
1.775V
1.800V
1.825V
1.850V
1.100V
1.125V
1.150V
1.175V
1.200V
1.225V
1.250V
1.275V
1.300V
1.325V
1.350V
1.375V
1.400V
1.425V
1.450V
1.475V
1.500V
1.525V
1.550V
1.575V
1.600V
Note:(1) 0: Connected to GND
(2) 1: Open
(3) For VID125, H: VCC, L: GND
DS9248A-06 March 2006
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5
Preliminary
RT9248A
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND-0.3V to VCC+0.3V
z Package Thermal Resistance
TSSOP-28, θJA -------------------------------------------------------------------------------------------------- 45°C/W
z Junction Temperature ------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10%
z Ambient Temperature Range--------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range--------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
VCC Supply Current
Symbol
Test Conditions
PWM 1,2,3 Open
VCC Rising
Min
Typ
Max Units
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
ICC
--
12
--
mA
VCCRTH
VCCHYS
VDVDTP
VDVDHYS
4.0
0.2
0.9
--
4.2
0.5
1.0
70
4.5
--
V
V
Trip (Low to High)
Hysteresis
Enable
1.1
--
V
VDVD Threshold
mV
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
fOSC
170
50
--
200
--
230
400
--
kHz
kHz
V
RRT = 12kΩ
RRT = 12kΩ
fOSC_ADJ
ΔVOSC
VRV
1.9
1.0
66
Ramp Valley
--
--
V
Maximum On-Time of Each Channel
RT Pin Voltage
62
0.94
75
%
VRT
1.0
1.06
V
RRT = 12kΩ
Reference and DAC
--
--
--
+1
+10
+1
%
mV
%
VRD10, VDAC ≥ 1V
VRD10, VDAC < 1V
VRM9
−1
−10
−1
DACOUT Voltage Accuracy
DACOUT Voltage Accuracy
ΔVDAC_10
ΔVDAC
_
9
To be continued
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DS9248A-06 March 2006
Preliminary
RT9248A
Parameter
DAC (VID0-VID4) Input Low
DAC (VID0-VID4) Input High
VID125 Input for VRM9
VID125 Input for VRD10
DAC (VID0-VID125) Bias Current
VOSS Pin Voltage
Symbol
Test Conditions
Min
--
Typ
Max Units
--
--
0.4
--
V
V
V
ILDAC
0.8
--
V
V
V
IHDAC
--
0.4
--
V
VID125_9
VID125_10
BIAS_DAC
0.8
35
--
V
50
1.0
65
μA
V
I
0.95
1.15
RVOSS = 100kΩ
V
VOSS
Error Amplifier
DC Gain
--
--
--
85
10
3
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
Current Sense GM Amplifier
ISP 1,2,3 Full Scale Source Current
ISP 1,2,3 Current for OCP
Protection
60
90
--
--
--
--
μA
μA
I
I
ISPFSS
ISPOCP
IMAX Voltage
R
IMAX = 10k
0.94
--
1.0
13
1.06
--
V
μA
%
V
IMAX
SS Current
VSS = 1V
I
SS
Over-Voltage Trip (VSEN/DACOUT)
Power Good
--
140
--
ΔOVT
Lower Threshold (VSEN/DACOUT)
Output Low Voltage
VSEN Rising
PG = 4mA
--
--
92
--
--
%
V
V
V
PG−
I
0.2
PGL
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
DS9248A-06 March 2006
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7
Preliminary
RT9248A
Application Information
RT9248Ais a multi-phaseDC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9248Aand its companion MOSFET driver provides high
quality CPU power and all protection functions to meet
the requirement of modern VRM.
Fault Detection
The chip detects VCORE for over voltage and power good
detection. The “hiccup mode” operation of over-current
protection is adopted to reduce the short circuit current.
The inrush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and output
voltage.
Voltage Control
RT9248A senses the CPU VCORE by an precise
instrumental amplifier to minimize the voltage drop on PCB
trace at heavy load. VSEN & SGND are the differential
inputs. VDIF is the output node of the differential voltage &
the input for PGOOD & OVP sense. The internal high
accuracy VID DAC allows selection of either VRM9 or
VRD10 compliance via VID125 pin setting. Control loop
consists of error amplifier, multi-phase pulse width
modulator, driver and power components. Like conventional
voltage mode PWM controller, the output voltage is locked
at the VREF of error amplifier and the error signal is used as
the control signal VC of pulse width modulator. The PWM
signals of different channels are generated by comparison
of EAoutput and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
Phase Setting and Converter Start Up
RT9248Ainterfaces with companion MOSFET drivers (like
RT9600, RT9602 or RT9603 series) for correct converter
initialization. The tri-state PWM output (high, low and high
impedance) pins sense the interface voltage at IC POR
period (both VCC andDVDtrip). The channel is enabled if
the pin voltage is 1.2V less than VCC. Please tie the PWM
output to VCC and the current sense pins to GND or left
floating if the channel is unused. For 2-Channel application,
connect PWM3 high.
Current Sensing Setting
RT9248Asenses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and droop tuning. The differential sensing
GM amplifier converts the voltage on the sense component
(can be a sense resistor or the RDS(ON) of the low side
MOSFET) to current signal into internal circuit (see
Figure 1). Be careful to choose GND sense input, ISN, of
theGM amplifier for effective channel current balance.
Current Balance
RT9248Asenses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and droop tuning. The differential sensing
GM amplifier converts the voltage on the sense component
(can be a sense resistor or the RDS(ON) of the low side
MOSFET) to current signal into internal balance circuit.
The current balance circuit sums and averages the current
signals then produces the balancing signals injected to
pulse width modulator. If the current of some power channel
is greater than average, the balancing signal reduces the
output pulse width to keep the balance.
IX1
C urrent
Balance
I
2I
I
X
X
X
IBP
R
<
SP1
ISP1
Sam ple
&
H old
-
D roop Tune
<
<
G M
+
R
IL
S
IBN
O ver-C urrent
D etection
IX2
C urrent
B alance
I
2I
I
X
X
X
IBP
R
R
<
SP2
SN
ISP2
ISN
Sam ple
&
H old
-
G M
D roop Tune
<
<
+
R
IL
Load Droop
S
IBN
O ver-C urrent
D etection
The sensed power channel current signals regulate the
reference ofDAC to form a output voltage droop proportional
to the load current. The droop or so-called “active voltage
positioning” can reduce the output voltage ripple at load
transient and the LC filter size.
G N D R eturn
IX3
C urrent
B alance
I
2I
I
X
X
X
IBP
R
<
SP3
ISP3
Sam ple
&
H old
-
G M
D roop Tune
<
<
+
R
IL
S
IBN
O ver-C urrent
D etection
Figure 1. Current Sense Circuit
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8
DS9248A-06 March 2006
Preliminary
RT9248A
IL ×RS
RSP
IX =
The sensing circuit gets
by local feedback.
Protection and SS Function
RSP = 3 x RSN (at 3 phase operation) to cancel the voltage
drop caused by GM amplifier input bias current. IX is
sampled and held just before low side MOSFET turns off
(See Figure 2). Therefore,
For OVP, the RT9248A detects the VCORE by VDIF pin
voltage of the differential amplifier output. Eliminate the
delay due to compensation network (compared to sensing
FB voltage) for fast and accurate detection. The trip point
of OVP is 140% of normal output level. The PWM outputs
are pulled low to turn on the low side MOSFET and turn off
the high side MOSFET of the synchronous rectifier at OVP.
The OVP latch can only be reset by VCC or DVD restart
power on reset sequence. The PGOOD detection trip point
of VCORE is 92% lower than the normal level. The PGOOD
open drain output pulls low when VCORE is lower than the
trip point. For VID jumping issue, only power fail conditions
(VCC & DVD are lower than trip point or OVP) reset the
output low.
I
L (S/H) × R
V
O
T
OFF
I
X (S/H)
=
S , IL (S/H) = IL (AVG)
−
×
,
R
SP
L
2
V
IN − V
O
⎡
⎤
T
OFF
=
× 5uS for fosc = 200kHz
⎢
⎥
V
IN
⎣
⎦
⎡
⎤
⎥
⎥
⎥
V
IN − V
O
⎡
⎤
V
O
−
× 5uS
⎢
⎢
⎣
⎥
⎦
R
S
V
IN
⎢
I
X (S/H) = IL(AVG)
−
×
2L
R
SP
⎢
⎢
⎣
⎥
⎦
Falling Slope = Vo/L
Inductor Current
IL
Soft-start circuit generates a ramp voltage by charging
external capacitor with 13μA current after IC POR acts.
The PWM pulse width and VCORE are clamped by the rising
ramp to reduce the inrush current and protect the power
devices.
IL(AVG)
IL(S/H)
PWM Signal & High Side MOSFET Gate Signal
Over-current protection trip point is set by the resistor RIMAX
connected to IMAX pin. OCP is triggered if one channel
0.6V
⎛
⎞
S/H current signal IX >
Controller forces
×1.4.
⎜
⎟
R
IMAX
⎝
⎠
Low Side MOSFET Gate Signal
PWM output latched at high impedance to turn off both
high and low side MOSFETs in the power stage and initial
the hiccup mode protection. The SS pin voltage is pulled
low with a 13μAcurrent after it is less than 90% VCC. The
converter restarts after SS pin voltage < 0.2V. Three times
of OCP disable the converter and only release the latch by
POR acts (see Figure 4).
Figure 2. Inductor Current and PWM Signal
DAC Offset Voltage & Droop Tuning
The DAC offset voltage is set by compensation network
1V
Rf1
⎛
⎞
×
⎜
⎟
& VOSS pin external resistors by
.
RVOSS
4
⎝
⎠
The S/H current signals from power channels are injected
to ADJ pin to create droop voltage.
VADJ = RADJ×
2IX
CCOoUuNntT==22 CCOoUuNntT==33
Count =1
∑
S.S
The DAC output voltage decreases by VADJ to form the
VCORE load droop (see Figure 3).
VCORE
0V
V
DAC
+
Overload
Applied
2I
V
X1
X2
X3
ADJ
-
COMP
+
-
2I
2I
∑
EA
ILOAD
0A
Current
Source
>
IVOSS
1
4
1V
IVOSS =
RVOSS
T3,T4
T0,T1
T2
+
-
FB
R
ADJ
V
OSS
TIME
R
R
ADJ
VOSS
F1
Figure 4.
V
CORE
Figure 3. DAC Offset Voltage & Droop Tune Circuit
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9
Preliminary
RT9248A
3-Phase Converter and Components Function Grouping
12V
VCC
BST
DRVH
SW
RT9603
IN
DRVL
PGND
SGND
VSEN
VDIF
PWM1
ISP1
12V
VID
PGOOD
VCC
BST
DRVH
RT9248A
VCORE
Compensation
& Offset
SW
COMP
FB
RT9603
PWM2
IN
DRVL
PGND
ADJ
Droop Setting
ISP2
ISN
12V
DVD
12V
Driver Power
UVLO
VOSS
SS
ISP3
VCC
BST
DAC Offset
Voltage Setting
DRVH
PWM3
SW
IMAX
GND
RT9603
IN
DRVL
PGND
OCP Setting
Current Sense
Components
Design Procedure Suggestion
Voltage Loop Setting
VRM Load Line Setting
a. Droop amplitude (ADJ pin resistor).
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. No load offset (additional resistor in compensation
network).
b. Error amplifier compensation & sawtooth wave amp-
litude (compensation network).
c. DAC offset voltage setting (VOSS pin & compen-
sation network resistor).
c. Kelvin sense for VCORE
.
Current Loop Setting
Power Sequence & SS
a. GM amplifier S/H current (current sense component
RDS(ON), ISPx & ISN pin external resistor value,
keep ISPx current < 60μA at full load condition for
better load line linearity).
DVD pin external resistor and SS pin capacitor.
PCB Layout
a. Kelvin sense for current sense GM amplifier input.
b. Refer to layout guide for other item.
b. Over-current protection trip point (IMAX pin resistor,
keep ISPx current < 90μA at OCP condition for
precision issue).
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DS9248A-06 March 2006
Preliminary
RT9248A
Design Example
Given:
Asymptotic Bode Plot of PWM Loop Gain
100
80
60
40
20
0
Apply for three phase converter
VIN = 12V
Uncompensated EA Gain
VCORE = 1.5V
ILOAD (max) = 60A
VDROOP = 120mV at full load
OCP trip point set at 30A for each channel (S/H)
RDS(ON) = 6mΩ of low side MOSFET at 27°C
L = 2μH
Compensated EA Gain
PWM Loop Gain
-20
-40
-60
Modulator Gain
10
100
1K
10K
100K 1M 10M
COUT = 9,000μF with 2mΩ ESR.
Frequency (Hz)
1. Compensation Setting
Figure 6.
a. ModulatorGain, Pole and Zero:
2. Droop & DAC Offset Setting
From the following formula:
For each channel the load current is 60A / 3 = 20A
and the ripple current, ΔIL, is given as:
V
IN
12V
Modulator Gain =
=
= 4.2 (12.46dB)
3
2
V
RAMP
1.9V×
1.5V
2uH
1.5V
12V
⎛
⎞
⎟
5us x
x 1−
= 3.28A
ΔIL
⎜
where VRAMP : ramp amplitude of sawtooth wave
1
⎝
L
⎠
LC Filter Pole =
= 1.2kHz and
The load current, I , at S/H is
.
= 18.36A
20A −
2π x LC
2
Using the following formula to select the appropriate
1
ESR Zero =
= 8.8kHz
IX (MAX) for the S/H of GM amplifier:
2π xESR x COUT
R
DS(ON) × 18.36A
I
X (MAX)
=
b. EA Compensation Network:
R
SP
Select R1 = 2.4kΩ, R2 = 24kΩ, C1 = 6.6nF,
C2 = 33pF and use the type 2 compensation
scheme shown in Figure 5.
The suggested IX is in the order of 40 to 50μA, select
RSP = 2.4kΩ then IX (MAX) will be 45.9μA.
VDROOP = 120mV = 45.9μA × 2 × 3 (phase no.) ×
RADJ, therefore RADJ will be 435Ω.
C1
C3
R2
C2
R3
The R
of MOSFET varies with temperature
DS(ON)
R1
rise. When the low side MOSFET working at 70°C
and 5000ppm/°C temperature coefficient of RDS(ON)
the RDS(ON) at 70°C is given as:
VDIF
>
COMP
,
FB
R3,C3 are used in type
-
+
6mΩ × {1+ (70°C − 27°C) × 5000ppm/°C} = 7.3mΩ.
RADJ at 70°C is given as:
RADJ_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 358Ω
3 compensation scheme
(left NC in type 2)
DACOUT
Figure 5.
3. Over-Current Protection Setting
From the following formulas:
1
OCP trip point set at 30A for each channel,
1
R
DS(ON) ×30A
0.6V
F
Z
=
, F =
P
I
X
=
=1.4 ×
, RIMAX = 11.2kΩ
IMAX
C
1
1
×C
+ C
2
2
2π x R
2
x C
1
⎛
⎞
⎟
RSP
R
2π x R x
2
⎜
⎝
R
R
2
C
⎠
Middle Band Gain =
Take the temperature rise into account, the RIMAX at
70°C will be:
1
By calculation, the FZ = 1kHz, F = 200kHz and
P
RIMAX_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 9.2kΩ
Middle Band Gain is 10 (i.e 20dB).
The asymptotic bode plot of EA compensation and
PWM loop gain is shown as Figure 6.
4. Soft-Start Capacitor Selection
CSS = 0.1μF is the suitable value for most application.
DS9248A-06 March 2006
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11
Preliminary
RT9248A
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to ISP1,2,3 and ISN should be located not more than 0.5 inch from the IC and away from the
noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin
connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
L1
SW1
VOUT
VIN
RIN
COUT
RL
CIN
V
L2
SW2
Figure 7. Power Stage Ripple Current Path
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12
DS9248A-06 March 2006
Preliminary
RT9248A
Next to IC
+12V
CBP
+12V or +5V
PWM
+5VIN
VCC
CBP
IMAX
CBOOT
VCC
IN
BST
VOSS
Next to IC
COMP
DRVH
LO1
COUT
VCORE
CC
RC
SW
RT9248A
CIN
RT9603
DRVL
Kelvin
Sense
Locate next
to FB Pin
RSP
FB
PGND
ISPx
ISN
RFB
RSN
Locate near MOSFETs
VSEN
ADJ
GND
For Thermal Couple
Figure 8. Layout Consideration
DS9248A-06 March 2006
www.richtek.com
13
Preliminary
RT9248A
Outline Dimension
D
L
E
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
0.850
0.050
0.800
0.178
9.601
1.200
0.152
1.050
0.305
9.804
0.033
0.002
0.031
0.007
0.378
0.047
0.006
0.041
0.012
0.386
D
e
0.650
0.026
E
6.300
4.293
0.450
6.500
4.496
0.762
0.248
0.169
0.018
0.256
0.177
0.030
E1
L
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
www.richtek.com
14
DS9248A-06 March 2006
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