RT9262AGS [RICHTEK]
High Efficiency, Low Supply Current, Step-up DC/DC Converter; 高效率，低电源电流，升压型DC / DC转换器
| 型号： | RT9262AGS |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | High Efficiency, Low Supply Current, Step-up DC/DC Converter |
| 文件： | 总10页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT9262/A
High Efficiency, Low Supply Current, Step-up DC/DC Converter
General Description
Features
ꢀ 1.0V Low Start-up Input Voltage
ꢀ High Supply Capability to Deliver 3.3V 100mA with
1V Input Voltage
The RT9262/A is a compact, high efficient, step-up
DC/DC converter with an adaptive current mode PWM
control loop, providing a stable and high efficient operation
over a wide range of load currents. It operates in both
continuous and discontinuous current modes in stable
waveforms without external compensation.
ꢀ 17μA Quiescent (Switch-off) Supply Current
ꢀ 90% Efficiency
ꢀ 550kHz Fixed Switching Rate
ꢀ Providing Flexibility for Using Internal and External
Power Switches
The low start-up input voltage below 1V makes
RT9262/A suitable for 1 to 4 battery cell applications
providing up to 400mA output current. The 550kHz high
switching rate minimized the size of external components.
Besides, the 17μA low quiescent current together with
high efficiency maintains long battery lifetime.
ꢀ Built-in 300mA LDO, also for the Zero-Output-
Current Shutdown Mode (RT9262)
ꢀ Boost DC-DC Integrating LDO for Up-Down
Regulation (RT9262)
ꢀ Built-in 0.86V Voltage Detector (RT9262A)
ꢀ 8-Pin SOP Package
The 1.8V to 5V output voltage is set with 2 external
resistors. Both internal 2A switch and driver for driving
external power devices (NMOS or NPN) are provided.
ꢀ RoHS Compliant and 100% Lead (Pb)-Free
A 300mA LDO is included in RT9262 to provide a
secondary low noise output as well as an output current
stop in the shutdown mode. Similarly, a 1.8V to 5V LDO
output voltage can be set with 2 external resistors. For
RT9262A, a low battery detector with 0.86V detection
voltage is included. RT9262/A are provided in SOP-8
packages.
Applications
ꢀ PDA
ꢀ Portable Instrument
ꢀ Wireless Equipment
ꢀ DSC
ꢀ LCD Back Bias Circuit
ꢀ RF-Tags
Pin Configurations
Ordering Information
RT9262/A
(TOP VIEW)
Package Type
S : SOP-8
GND
EXT
8
7
6
5
EN
LX
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
2
3
4
LFB
VDD
FB
LDO O
Include Low Battery Detector
Include LDO
RT9262CS
Note :
GND
EXT
LBO
LBI
8
EN
LX
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
2
3
4
7
6
5
VDD
FB
`Suitable for use in SnPb or Pb-free soldering processes.
`100%matte tin (Sn) plating.
RT9262ACS
SOP-8
DS9262/A-11 March 2007
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1
Preliminary
RT9262/A
Typical Application Circuit
C3
100uF
V
IN
C4
100pF
R1
1.6M
L1
4.7uF
VDD
EN
RT9262
EXT
LX
D1
3.3V
V
2.5V
LDO O
C5
1nF
V
OUT1
R4
1.3M
OUT2
LFB
GND
FB
C6
10uF
R2
980K
C2
1uF
C1
100uF
R3
680K
Figure 1. RT9262 TypicalApplication for Portable Instruments below 400mA
C3
100uF
V
IN
L1
VDD
R1
1.6M
C4
100pF
4.7uF
EN
RT9262
EXT
LX
D1
3.3V
V
Low Battery
LBO
OUT1
Warning Output
(Open Collector)
R4
R3
LFB
GND
FB
R2
980K
C2
1uF
C1
100uF
Figure 2. RT9262ATypicalApplication for Portable Instruments below 400mA
C3
100uF
V
IN
C4
100pF
Chip
Enable
R1
1.6M
L1
VDD
4.7uF
EN
RT9262
EXT
LX
D1
3.3V
LDO O
V
OUT
LFB
GND
FB
C5
R2
980K
C2
1uF
C1
100uF
10uF
Figure 3.Application Circuit with Zero-Output-Current Shutdown Mode Control
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2
DS9262/A-11 March 2007
Preliminary
RT9262/A
C3
100uF
V
IN
L1
4.7uF
C4
100pF
R1
1.6M
VDD
EN
LX
EXT
FB
3.3V
RT9262
V
Q1
N MOS
OUT1
D1
2.5V
V
LDO O
LFB
C5
1nF
R4
1.3M
OUT2
GND
C6
R2
980K
C2
1uF
C1
100uF
10uF
R3
680K
Figure 4. 0.4A ~ 2A Output Current Application
D1
L1
5V
V
10uF
IN
C4
100uF
VDD
Q1
N MOS
15V
EN
EXT
RT9262
V
OUT1
C3
0.1uF
2.5V
V
LDO O
LFB
LX
FB
R1
2.2M
C5
1nF
R4
1.3M
OUT2
GND
C6
C2
1uF
C1
100uF
R2
200K
10uF
Rm
0.05 ~ 0.1
R3
680K
Figure 5. High Voltage Application (Rm should be added when IL > 100mA)
DS9262/A-11 March 2007
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3
Preliminary
RT9262/A
Functional Pin Description
Pin No.
Pin Name
Pin Function
RT9262
RT9262A
1
1
GND
EXT
Ground
Output Pin for Driving External NMOS or NPN
2
2
When driving an NPN, a resistor should be added for limiting base current.
3
4
--
--
LFB
Feedback Pin of the Built-in LDO (Internal Vref = 0.86V)
Voltage Output Pin of the Built-in LDO
LDOO
Drain Output Pin of the NMOS of the Built-in Low Voltage Detector
This pin will be internally pulled low when the voltage at LBI pin drops to
below 0.86V.
--
3
LBO
Input Pin of the Built-in Low Voltage Detector
Trip point = 0.86V
--
5
4
5
LBI
FB
Feedback Input Pin
Internal reference voltage for the error amplifier is 1.25V.
6
7
8
6
7
8
VDD
LX
Input Positive Power Pin of RT9262/A
Pin for Switching
EN
Chip Enable Pin (Active High).
Function Block Diagram
RT9262
VDD
VDD
-
+
0.86V
Q2
P MOS
EXT
LX
LDO O
LFB
Q1
-
+
FB
N MOS
Loop Control Circuit
1.25V
VDD
R2
R1
Shut Down
Q3
N MOS
EN
GND
Over Temp.
Detector
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DS9262/A-11 March 2007
Preliminary
RT9262/A
VDD
LBI
RT9262A
LBO
-
+
Q2
N MOS
EXT
LX
0.86V
Q1
-
+
FB
N MOS
Loop Control Circuit
1.25V
VDD
R2
R1
Shut Down
Q3
N MOS
EN
GND
Over Temp.
Detector
Absolute Maximum Ratings
ꢀ Supply Voltage ----------------------------------------------------------------------------------------------------- −0.3V to 7V
ꢀ LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to 7V
ꢀ LDO Output Voltage ---------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V)
ꢀ Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V)
ꢀ LX Pin Switch Current -------------------------------------------------------------------------------------------- 2.5A
ꢀ EXT PinDriver Current -------------------------------------------------------------------------------------------- 30mA
ꢀ LBO Current -------------------------------------------------------------------------------------------------------- 30mA
ꢀ PowerDissipation, PD @ TA = 25°C
SOP-8 ---------------------------------------------------------------------------------------------------------------- 0.625W
ꢀ Package Thermal Resistance
SOP-8, θJA ---------------------------------------------------------------------------------------------------------- 160°C/W
ꢀ Operating Junction Temperature ------------------------------------------------------------------------------- 150°C
ꢀ Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to +150°C
DS9262/A-11 March 2007
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5
Preliminary
RT9262/A
Electrical Characteristics
(VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions
Start-UP Voltage
Min
--
Typ
0.98
--
Max Units
1.05
6.5 *
--
V
V
V
ST
I = 1mA
L
Operating VDD Range
0.8
--
V
I
Start-up to I
> 250μA
DD1
DD
47
No Load Current I (V )
V
V
= 1.5V, V = 3.3V
OUT
μA
μA
μA
V
IN
NO LOAD
IN
Switch-off Current I (VDD)
--
17
--
ISWITCH OFF
= 6V
IN
--
0.1
1
Shutdown Current I (V )
I
EN Pin = 0V, V = 4.5V
IN
IN
OFF
Feedback Reference Voltage
1.225
1.25 1.275
0.86 0.877
0.86 0.877
V
Close Loop, V = 3.3V
DD
REF
REF
Feedback Reference
Voltage for LDO
RT9262
0.843
V
V
Close Loop, V = 3.3V
DD
LBI Pin Trip Point
RT9262A
0.843
--
V
kHz
%
V
V
= 3.3V
= 3.3V
= 3.3V
= 3.3V
= 3.3V
= 3.3V
= 3.3V
DD
Switching Rate
550
92
--
--
F
S
DD
Maximum Duty
--
D
V
V
V
V
V
V
MAX
DD
DD
DD
DD
DD
LX ON Resistance
Current Limit Setting
EXT ON Resistance to VDD
EXT ON Resistance to GND
Line Regulation
--
0.25
2
--
Ω
--
--
A
I
LIM
--
40
--
Ω
--
30
--
Ω
--
10
--
mV/V
mV/mA
Ω
ΔV
ΔV
= 1.5 to 2.5V, I = 1mA
LINE
IN
L
Load Regulation
--
0.25
1
--
V
IN
= 2.5V, I = 1 to 100mA
LOAD
L
LDO PMOS ON Resistance RT9262
--
1.5
--
V
DD
= 3.3V
LDO Drop Out Voltage
LBO ON Resistance
EN Pin Trip Level
RT9262
--
70
mV
Ω
V
DROP
V
DD
V
DD
V
DD
= 3.3V, I = 100mA
L
RT9262A
--
40
--
= 3.3V
= 3.3V
0.2
--
0.8
50
1.4
--
V
Temperature Stability for FB, LFB, LBI
Thermal Shutdown
Guaranteed by Design
Guaranteed by Design
Guaranteed by Design
T
ppm/°C
°C
S
--
165
10
--
T
SD
Thermal Shutdown Hysterises
--
--
ΔT
°C
SD
* Note: The EN pin shall be tied to VDD pin and inhibit to act the ON/OFF state whenever the VDD pin voltage may
reach to 5.5V or above.
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6
DS9262/A-11 March 2007
Preliminary
Typical Operating Characteristics
RT9262/A
Efficiency
Efficiency
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
Refet to Application Circuit Figure 1 and Figure 2
Refet to Application Circuit Figure 1 and Figure 2
VIN = 4.0V
3.0V
VIN = 3.0V
2.5V
2.0V
2.0V
1.5V
1.5V
1.2V
1.2V
1.0V
VOUT = 5.0V; TA = 25°C
0.01 0.1
1.0V
VOUT = 3.3V; TA = 25°C
1
10
100
1000
0.01
0.1
1
10
100
1000
ILOAD (mA)
ILOAD (mA)
No Load Current
No Load Current
90
80
70
60
50
40
30
20
10
0
140
120
100
80
VOUT = 3.3V; TA = 25°C
VOUT = 5.0V; TA = 25°C
60
40
20
Refet to Application Circuit Figure 1 and Figure 2
1.2 1.5 2.5
Refet to Application Circuit Figure 1 and Figure 2
1.2 1.5 2.5
0
1
2
3
1
2
3
4
Input Voltage (V)
Input Voltage (V)
Start Up Voltage
Start Up Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
VOUT = 3.3V; TA = 25°C
VOUT = 5.0V; TA = 25°C
Refet to Application Circuit Figure 1 and Figure 2
20 40 60 80
Refet to Application Circuit Figure 1 and Figure 2
0
100
0
25
50
75
100
ILOAD (mA)
ILOAD (mA)
DS9262/A-11 March 2007
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7
Preliminary
RT9262/A
Applications Information
Output Voltage Setting
PRECAUTION 1: Improper probing to FB or LFB
pin will cause fluctuation at VOUT1 and VOUT2. It
may damage RT9262/A and system chips
because VOUT1 may drastically rise to an over-
rated level due to unexpected interference or
parasitics being added to FB pin.
Referring to application circuits Figure 1 to Figuer 5 the
output voltage of the switching regulator (VOUT1) can be
set with Equation (1).
The LDO output voltage (VOUT2 of RT9262) can be set
with Equation (2).
R1
PRECAUTION 2:Disconnecting R1 or short circuit
across R2 may also cause similar IC damage as
described in precaution 1.
(1)
VOUT1 = (1+
)×1.25V
R2
R4
R3
(2)
VOUT2 = (1+
)× 0.86V
PRECAUTION 3: When large R values were used
in feedback loops, any leakage in FB/LFB node
may also cause VOUT1 and VOUT2 voltage
fluctuation, and IC damage. To be especially
highlight here is when the air moisture frozen and
re-melt on the circuit board may cause several
mA leakage between IC or component pins. So,
when large R values are used in feedback loops,
post coating, or some other moisture-preventing
processes are recommended.
And trip point of the low battery detector is 0.86V at LBI
pin of RT9262A.
Feedback Loop Design
Referring to application circuits Figure 1 to Figure 5. The
selection of R1, R2, R3, and R4 based on the trade-off
between quiescent current consumption and interference
immunity is stated below:
ꢀ Follow Equation (1) and Equation (2).
ꢀ Higher R reduces the quiescent current (Path current
= 1.25V/R2, and 0.86V/R3), however resistors beyond
5MW are not recommended.
V
OUT1
R1
Prober Parasitics
_
FB Pin
ꢀ
Lower R gives better noise immunity, and is less
sensitive to interference, layout parasitics, FB/LFB node
leakage, and improper probing to FB/LFB pins.
R2
Q
+
Layout Guide
ꢀ A proper value of feed forward capacitor parallel with
R1 (or R4) on Figure 1 to Figure 5 can improve the
noise immunity of the feedback loops, especially in an
improper layout. An empirical suggestion is around
100pF ~ 1nF for feedback resistors of MW, and 10nF~
0.1μF for feedback resistors of tens to hundreds kΩ.
ꢀ AfullGNDplane without gap break.
ꢀ VOUT1 toGNDnoise bypass−Short and wide connection
for C2 to Pin1 and Pin6.
ꢀ VIN toGNDnoise bypass -Add a 100μF capacitor close
to L1 inductor, when VIN is not an idea voltage source.
For applications without standby or suspend modes, lower
values of R1 to R4 are preferred. For applications
concerning the current consumption in standby or
suspend modes, the higher values of R1 to R4 are
needed. Such "high impedance feedback loops" are
sensitive to any interference, which require careful layout
and avoid any interference, e.g. probing to FB/LFB pins.
ꢀ Minimized FB/LFB node copper area and keep far away
from noise sources.
ꢀ Minimized parasitic capacitance connecting to LX and
EXT nodes, which may cause additional switching loss.
ꢀ The following diagram is an example of 2-layer board
layout for application circuits Figure 1 to Figure 4.
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8
DS9262/A-11 March 2007
Preliminary
RT9262/A
First Layer
RT9262/A
Second Layer (FullGNDPlane)
DS9262/A-11 March 2007
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9
Preliminary
RT9262/A
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.050
5.791
0.400
5.004
3.988
1.753
0.508
1.346
0.254
0.254
6.200
1.270
0.189
0.150
0.053
0.013
0.047
0.007
0.002
0.228
0.016
0.197
0.157
0.069
0.020
0.053
0.010
0.010
0.244
0.050
J
M
8-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
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10
DS9262/A-11 March 2007
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