RT9618 [RICHTEK]
Synchronous-Rectified Buck MOSFET Drivers; 同步整流降压MOSFET驱动器
| 型号： | RT9618 |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Synchronous-Rectified Buck MOSFET Drivers |
| 文件： | 总12页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT9618/A
Synchronous-Rectified Buck MOSFET Drivers
General Description
Features
z Drives Two N-Channel MOSFETs
z Adaptive Shoot-Through Protection
z Embedded Boot Strapped Diode
z Support High Switching Frequency
z Fast Output Rise Time
The RT9618/A is a high frequency, dual MOSFET driver
specifically designed to drive two power N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. This driver combined with Richtek’ s series of
Multi-Phase Buck PWM controller form a complete core-
voltage regulator solution for advanced micro-processors.
z Small SOP-8 Package
z Tri-State Input for Bridge Shutdown
z Supply Under Voltage Protection
z Upper MOSFET Direct Shorted Protection
z RoHS Compliant and 100% Lead (Pb)-Free
The RT9618/A drives both the lower/upper gate in a
synchronous-rectifier bridge with 12V. This drive-voltage
flexibility provides the advantage of optimizing applications
involving trade-offs between switching losses and
conduction losses.
Applications
RT9618Ahas longer UGATE/LGATE deadtime which can
drive the MOSFETs with large gate RC value, avoiding the
shoot-through phenomenon. RT9618 is targeted to drive
low gate RC MOSFETs and performs better efficiency.
z Core Voltage Supplies forDesktop, Motherboard CPU
z High Frequency Low ProfileDC-DC Converters
z High Current Low VoltageDC-DC Converters
The output drivers in the RT9618/A can efficiently switch
power MOSFETs at frequency up to 500kHz. Switching
frequency above 500kHz has to take into account the
thermal dissipation of SOP-8 package. RT9618/A is
capable to drive a 3nF load with a 30ns rise time. RT9618/
A implements bootstrapping on the upper gate with an
external capacitor and an embedded diode. This reduces
implementation complexity and allows the use of higher
performance, cost effectiveN-Channel MOSFETs.Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
Ordering Information
RT9618/A
Package Type
S : SOP-8
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Long Dead Time
Short Dead Time
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Pin Configurations
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
(TOP VIEW)
BOOT
PWM
OD
8
7
6
5
UGATE
PHASE
PGND
2
3
4
VCC
LGATE
SOP-8
DS9618/A-04 March 2007
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1
RT9618/A
Typical Application Circuit
L1
2.2uH
ATX_12V
V
IN
C12
1000uF
C8
10uF
C9
10uF
C10
1000uF
C11
1000uF
C13
10uF
C14
10uF
C2
1uF
R2
1
D1
1
R1
10
R3
2.2
BOOT
8
4
ATX_12V
VCC
Q1
Q2
UGATE
C1
1uF
L2
1uH
RT9618/A
V
CORE
C7
7
5
PHASE
LGATE
3
2
OD
PWM
+5V
R5
2.2
R4
0
C4
2200uF
C5
2200uF
C6
10uF
PWM
10uF
C3
3.3nF
PGND
6
Functional Pin Description
Pin No. Pin Name
Pin Function
1
2
BOOT
PWM
Floating bootstrap supply pin for upper gate drive.
Input PWM signal for controlling the driver.
Output Disable. When low, both UGATE and LGATE are driven low and the normal
operation is disabled.
3
OD
4
5
6
VCC
+12V Supply Voltage.
LGATE
PGND
Lower Gate Drive Output. Connected to gate of low-side power N-Channel MOSFET.
Common Ground.
Connected this pin to the source of the high-side MOSFET and the drain of the low-side
MOSFET.
7
8
PHASE
UGATE
Upper Gate Drive Output. Connected to gate of high-side power N-Channel MOSFET.
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DS9618/A-04 March 2007
RT9618/A
Function Block Diagram
VCC
POR
Internal
5V
R
BOOT
Input
Disable
PWM
Shoot-Through
Protection
UGATE
R
Turn Off Detect
PHASE
OD
VCC
Shoot-Through
Protection
LGATE
PGND
Timing Diagram
PWM
t
pdlLGATE
90%
LGATE
UGATE
t
pdlUGATE
2V
2V
90%
2V
t
2V
t
pdhUGATE
pdhLGATE
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RT9618/A
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC ------------------------------------------------------------------------------------- −0.3V to 15V
z BOOT to PHASE ----------------------------------------------------------------------------------------- −0.3V to 15V
z BOOT toGND
DC------------------------------------------------------------------------------------------------------------ −0.3V to VCC + 15V
< 200ns ----------------------------------------------------------------------------------------------------- −0.3V to 42V
z PHASE to GND
DC------------------------------------------------------------------------------------------------------------ −5V to 15V
< 200ns ----------------------------------------------------------------------------------------------------- −10V to 30V
z LGATE
DC------------------------------------------------------------------------------------------------------------ GND − 0.3V to VCC + 0.3V
< 200ns ----------------------------------------------------------------------------------------------------- −2V to VCC + 0.3V
z UGATE ------------------------------------------------------------------------------------------------------ VPHASE − 0.3V to VBOOT + 0.3V
< 200ns ----------------------------------------------------------------------------------------------------- VPHASE − 2V to VBOOT + 0.3V
z PWM Input Voltage -------------------------------------------------------------------------------------- GND − 0.3V to 7V
z OD------------------------------------------------------------------------------------------------------------ GND − 0.3V to 7V
z PowerDissipation, PD @ TA = 25°C
z SOP-8 ------------------------------------------------------------------------------------------------------- 0.625W
z Package Thermal Resistance (Note 4)
SOP-8, θJA ------------------------------------------------------------------------------------------------- 160°C/W
z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------- −40°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------- 12V 10%
z Junction Temperature Range--------------------------------------------------------------------------- 0°C to 125°C
z Ambient Temperature Range--------------------------------------------------------------------------- 0°C to 70°C
Electrical Characteristics
(Recommended Operating Conditions, TA = 25°C unless otherwise specified)
Parameter
Supply Voltage
Symbol
Test Conditions
Min
7.3
--
Typ
--
Max Units
V
CC
Power Supply Voltage
Supply Current
13.5
2.5
V
V
CC
V
CC
Power Supply Current
1
mA
I
V
= 12V, PWM = 0V
VCC
BOOT
Power-On Reset
5.5
--
6.4
2.2
7.3
--
POR Threshold
Hysteresis
V
V
V
V
CC
Rising
VCCrth
V
VCChys
To be continued
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DS9618/A-04 March 2007
RT9618/A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
PWM Input
Maximum Input Current
PWM Floating Voltage
PWM Rising Threshold
PWM Falling Threshold
Output Disable Input
OD Rising Threshold
OD Hysteresis
PWM = 0V or 5V
--
--
300
2.4
3.6
1.3
--
--
μA
V
I
PWM
V
V
CC
= 12V
PWMfl
3.2
1.1
3.9
1.5
V
V
PWMrth
PWMfth
V
V
1.5
--
1.8
0.5
2.1
--
V
V
V
V
ODrth
ODhys
Timing
UGATE Rise Time
UGATE Fall Time
LGATE Rise Time
LGATE Fall Time
t
t
t
t
V
V
V
V
= 12V, 3nF load
= 12V, 3nF load
= 12V, 3nF load
= 12V, 3nF load
--
--
--
--
--
--
--
--
--
27
32
35
27
20
90
15
20
8
35
45
45
38
--
ns
ns
ns
ns
rUGATE
fUGATE
rLGATE
fLGATE
CC
CC
CC
CC
RT9618
t
pdhUGATE
V
− V
= 12V
BOOT
PHASE
RT9618A
--
See Timing Diagram
Propagation Delay
ns
t
t
t
--
pdlUGATE
pdhLGATE
pdlLGATE
RT9618/A
--
See Timing Diagram
--
Output
UGATE Drive Source
UGATE Drive Sink
LGATE Drive Source
LGATE Drive Sink
R
R
R
R
V
V
V
V
− V
− V
= 12V
= 12V
--
--
--
--
1.9
1.4
1.9
1.1
3
3
Ω
Ω
Ω
Ω
UGATEsr
UGATEsk
LGATEsr
LGATEsk
BOOT
PHASE
BOOT
PHASE
= 12V
= 12V
3
CC
CC
2.2
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
DS9618/A-04 March 2007
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RT9618/A
Typical Operating Characteristics
High side MOSFET : FR3707Z x 1, Low side MOSFET : LR8113 x 2
Drive Enable
Drive Disable
OD
(2V/Div)
OD
(2V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
No Load
No Load
Time (1μs/Div)
Time (1μs/Div)
PWM to Drive Waveform
PWM to Drive Waveform
PWM
(5V/Div)
PWM
(5V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
No Load
No Load
Time (25ns/Div)
Time (25ns/Div)
Dead Time
Dead Time
30A/CH
UGATE
30A/CH
UGATE
PHASE
PHASE
LGATE
(5V/Div)
(5V/Div)
LGATE
Time (20ns/Div)
Time (20ns/Div)
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DS9618/A-04 March 2007
RT9618/A
Dead Time
Dead Time
No Load
UGATE
No Load
UGATE
PHASE
LGATE
PHASE
LGATE
(5V/Div)
(5V/Div)
Time (20ns/Div)
Time (20ns/Div)
Short Pulse
Internal Diode I-V Curve
0.06
0.05
0.04
0.03
0.02
0.01
0.00
IOUT = 119A to 24A
UGATE
PHASE
LGATE
(5V/Div)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Voltage (V)
Time (20ns/Div)
DS9618/A-04 March 2007
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RT9618/A
Application Information
The RT9618/Ais designed to drive both high side and low
side N-Channel MOSFET through externally input PWM
control signal. It has power-on protection function which
held UGATE and LGATE low before VCC up across the
rising threshold voltage. After the initialization, the PWM
signal takes the control. The rising PWM signal first forces
the LGATE signal turns low then UGATE signal is allowed
to go high just after a non-overlapping time to avoid shoot-
through current. The falling of PWM signal first forces
UGATE to go low. When UGATE and PHASE signal reach
a predetermined low level, LGATE signal is allowed to turn
high.
Also to prevent the overlap of the gate drives during LGATE
turn low and UGATE turn high, the non-overlap circuit
monitors the LGATE voltage. When LGATE go below 1.2V,
UGATE is allowed to go high.
Driving Power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. When Vgs at 12V (or 5V), the gate draws
the current only few nano-amperes. Thus once the gate
has been driven up to "ON" level, the current could be
negligible.
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large currents
to drive the gate up and down 12V (or 5V) rapidly. It also
required to switch drain current on and off with the required
speed. The required gate drive currents are calculated as
follows.
The PWM signal is acted as "High" if above the rising
threshold and acted as "Low" if below the falling threshold.
Any signal level enters and remains within the shutdown
window is considered as "tri-state", the output drivers are
disabled and both MOSFET gates are pulled and held
low. If left the PWM signal floating, the pin will be kept
around 2.4V by the internal divider and provide the PWM
controller with a recognizable level. OD pin will also
shutdown the bridge of tied to GND.
D1
L
d1
s1
V
V
OUT
IN
Cgs1
Cgd1
Cgd2
Cgs2
d2
Igs1
Igd1
Ig1
The RT9618/A typically operates at frequency of 200kHz
to 500kHz. It shall be noted that to place a 1N4148 or
schottky diode between the VCC and BOOT pin as shown
in the typical application circuit for ligher efficiency.
Ig2 Igd2
Igs2
g1
g2
D2
s2
GND
V
g1
Non-overlap Control
V
+12V
PHASE
To prevent the overlap of the gate drives during the UGATE
turn low and the LGATE turn high, the non-overlap circuit
monitors the voltages at the PHASE node and high side
gate drive (UGATE-PHASE). When the PWM input signal
goes low, UGATE begins to turn low (after propagation
delay). Before LGATE can turn high, the non-overlap
protection circuit ensures that the monitored voltages have
gone below 1.2V. Once the monitored voltages fall below
1.2V, LGATE begins to turn high. For short pulse condtion,
if the PHASE pin had not gone high after LGATE turns
low, the LGATE has to wait for 200ns before turn high. By
waiting for the voltages of the PHASE pin and high side
gate drive to fall below 1.2V, the non-overlap protection
circuit ensures that UGATE is low before LGATE turns
high.
t
t
V
g2
12V
Figure 1. Equivalent Circuit andAssociated Waveforms
In Figure 1, the current Ig1 and Ig2 are required to move the
gate up to 12V. The operation consists of charging Cgd
and Cgs. Cgs1 and Cgs2 are the capacitances from gate to
source of the high side and the low side power MOSFETs,
respectively. In general data sheets, the Cgs is referred as
"Ciss" which is the input capacitance. Cgd1 and Cgd2 are the
capacitances from gate to drain of the high side and
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DS9618/A-04 March 2007
RT9618/A
the low side power MOSFETs, respectively and referred to
the data sheets as "Crss" the reverse transfer capacitance.
For example, tr1 and tr2 are the rising time of the high side
and the low side power MOSFETs respectively, the required
the total current required from the gate driving source is
(9)
Ig1 = Igs1 +Igd1 = (1.428 + 0.326) = 1.754 (A)
Ig2 = Igs2 +Igd2 = (0.88 + 0.4) = 1.28 (A)
(10)
current Igs1 and Igs2 are showed below :
,
By a similar calculation, we can also get the sink current
required from the turned off MOSFET.
Cgs1×12
dVg1
dt
Igs1 = Cgs1
=
(1)
(2)
tr1
Cgs1×12
dVg2
dt
Select the Bootstrap Capacitor
Igs2 = Cgs1
=
tr2
Figure 2 shows part of the bootstrap circuit of RT9618/A.
The VCB (the voltage difference between BOOTand PHASE
on RT9618/A) provides a voltage to the gate of the high
side power MOSFET. This supply needs to be ensured
that the MOSFET can be driven. For this, the capacitance
CB has to be selected properly. It is determined by following
constraints.
Before driving the gate of the high side MOSFET up to
12V (or 5V), the low side MOSFET has to be off; and the
high side MOSFET is turned off before the low side is
turned on. From Figure 1, the body diode "D2" had been
turned on before high side MOSFETs turned on.
dV
dt
12V
tr1
(3)
Igd1 = Cgd1
= Cgd1
V
IN
1N4148
V
CC
Before the low side MOSFET is turned on, the Cgd2 have
been charged to VIN. Thus, as Cgd2 reverses its polarity
and g2 is charged up to 12V, the required current is
BOOT
+
C
UGATE
PHASE
B
V
CB
-
dV
dt
Vi+12V
(4)
I
= C
= C
gd2
gd2
gd2
t
V
r2
CC
LGATE
PGND
It is helpful to calculate these currents in a typical case.
Assume a synchronous rectified buck converter, input
voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side MOSFET
is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and
tr = 14ns. The low side MOSFET is PHB95N03LT whose
Ciss = 2200pF, Crss = 500pF and tr= 30ns, from the equation
(1) and (2) we can obtain
Figure 2. Part of Bootstrap Circuit of RT9618/A
In practice, a low value capacitor CB will lead the over-
charging that could damage the IC. Therefore to minimize
the risk of overcharging and reducing the ripple on VCB,
the bootstrap capacitor should not be smaller than 0.1μF,
and the larger the better. In general design, using 1μF can
provide better performance.At least one low-ESR capacitor
should be used to provide good local de-coupling. Here, to
adopt either a ceramic or tantalum capacitor is suitable.
1660×10-12 ×12
(5)
(6)
Igs1
=
=
= 1.428 (A)
= 0.88 (A)
14×10-9
2200×10-12 ×12
30×10-9
Igs2
from equation. (3) and (4)
Power Dissipation
For not exceeding the maximum allowable power
dissipation to drive the IC beyond the maximum
recommended operating junction temperature of 125°C, it
is necessary to calculate power dissipation appro-priately.
380×10-12 ×12
(7)
(8)
I
=
=
= 0.326 (A)
gd1
gd2
14×10-9
500×10-12 ×(12+12)
I
= 0.4 (A)
30×10-9
DS9618/A-04 March 2007
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9
RT9618/A
This dissipation is a function of switching frequency and
total gate charge of the selected MOSFET. Figure 3 shows
the power dissipation test circuit. CL and CU are the UGATE
and LGATE load capacitors, respectively. The bootstrap
capacitor value is 0.01μF.
TJ = (160°C/W x 100mW) + 25°C = 41°C
where the ambient temperature is 25°C.
(11)
The method to improve the thermal transfer is to increase
the PCB copper area around the RT9618/A first. Then,
adding a ground pad under IC to transfer the heat to the
peripheral of the board.
C
BOOT
1uF
1N4148
10
+12V
+12V
Over-Voltage Protection Function at Power-On
BOOT
UGATE
2N7002
VCC
An unique feature of the RT9618/A driver is the addition of
over-voltage protection in the event of upper MOSFET direct
shorted before power-on. The RT9618/A detects the fault
condition during initial start-up, the internal power-on OVP
sense circuitry will rapidly drive the output lower MOSFET
on before the multi-phase PWM controller takes control.
1uF
C
3nF
U
RT9618/A
PHASE
2N7002
5V
PWM
OD
VIN
20
LGATE
PGND
C
L
3nF
Figure 5 shows the measured waveforms with the high
side MOSFET directly shorted to 12V.
Figure 3. Test Circuit
Figure 4 shows the power dissipation of the RT9618/Aas
a function of frequency and load capacitance. The value of
the CU and CL are the same and the frequency is varied
from 100kHz to 1MHz.
(2V/Div)
VCC
Power Dissipation vs. Frequency
(2V/Div)
PHASE
1000
CU=CL=3nF
900
800
700
600
500
400
300
200
100
0
(2V/Div)
LGATE
(2V/Div)
VCORE
CU=CL=2nF
CU=CL=1nF
Time (50ms/Div)
Figure 5. Waveforms at High Side MOSFET Shorted
Please note that the VCC trigger point to RT9618/A is at
3V, and the clamped level on PHASE pin is at about 2.4V.
Obviously since the PHASE pin voltage increases during
initial start-up, the VCORE increases correspondingly, but
it would quickly drop-off followed by LGATE and VCC
decreased.
0
200
400
600
800
1000
Frequency (kHz)
Figure 4. PowerDissipation vs. Frequency
The operating junction temperature can be calculated from
the power dissipation curves (Figure 4). Assume
VCC =12V, operating frequency is 200kHz and the
CU=CL=1nF which emulate the input capacitances of the
high side and low side power MOSFETs. From Figure 4,
the power dissipation is 100mW. For RT9618/A, the
package thermal resistance θJA is 160°C/W, the operating
junction temperature is calculated as :
Layout Consideration
Figure 6 shows the schematic circuit of a two-phase
synchronous buck converter to implement the RT9618/A.
The converter operates from 5V to 12V of VIN.
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DS9618/A-04 March 2007
RT9618/A
D1
L1
R1
10
12V
V
12V
IN
C4
1uF
1.2uH
C2
1uF
1
4
C1
1000uF
BOOT
VCC
CB
1uF
2
3
VIN
PWM
5V
8
Q1
L2
UGATE
PHASE
7
V
OD
CORE
PHB83N03LT
PHB95N03LT
2uH
Q2
C3
1500uF
5
6
PGND
LGATE
Figure 6. Two-Phase Synchronous Buck Converter Circuit
When layout the PCB, it should be very careful. The power-
circuit section is the most critical one. If not configured
properly, it will generate a large amount of EMI. The junction
of Q1, Q2, L2 should be very close.
Next, the trace from UGATE, and LGATE should also be
short to decrease the noise of the driver output signals.
PHASE signals from the junction of the power MOSFET,
carrying the large gate drive current pulses, should be as
heavy as the gate drive trace. The bypass capacitor C4
should be connected to PGND directly. Furthermore, the
bootstrap capacitors (CB) should always be placed as close
to the pins of the IC as possible.
DS9618/A-04 March 2007
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RT9618/A
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.050
5.791
0.400
5.004
3.988
1.753
0.508
1.346
0.254
0.254
6.200
1.270
0.189
0.150
0.053
0.013
0.047
0.007
0.002
0.228
0.016
0.197
0.157
0.069
0.020
0.053
0.010
0.010
0.244
0.050
J
M
8-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
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