R1273L103A-E2-Y [RICOH]
Switching Regulator,;型号: | R1273L103A-E2-Y |
厂家: | RICOH ELECTRONICS DEVICES DIVISION |
描述: | Switching Regulator, |
文件: | 总40页 (文件大小:1680K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
R1273L-Y Series
34V, 1ch_14A Synchronous Step-down DC/DC Converter for Industrial Applications
NO.EY-352-190307
OUTLINE
The R1273L is a step-down DC/DC converter which can generate an output voltage of 0.7 V to 5.3 V by driving
high- / low-side NMOSs. By the adoption of a unique current mode PWM architecture without an external
current sense resistor, the R1273L can make up a stable DC/DC converter with high-efficiency even if adding
a low DCR inductor externally. And, by the frequency characteristics optimization with using external phase
compensation capacitor, the R1273L can achieve a high-speed response to variations of input voltage and
load current. The user-settable oscillation frequency is adjustable over a range of 250 kHz to 1 MHz by external
resistors, and also can be synchronized to an external clock in a range of 250 kHz to 1 MHz. The R1273L
supports three operating modes: Forced PWM mode, PLL_PWM mode, and PWM/VFM Auto-switching mode.
These modes are selectable according to conditions of the MODE pin. Especially, the PWM/VFM Auto-
switching mode can improve efficiency under light load conditions.
The R1273L can minimize the output voltage drop caused by an input voltage drop at cranking, with reducing
the operating frequency (the lowest possible limit is a quarter of the frequency) so that the off-duty is reduced.
Protection functions include a current limit function, a hiccup-mode short-circuit protection (non-latch type), a
thermal shutdown function, an UVLO (Under Voltage Lock Out) function, an OVD (Over Voltage Detection)
function, a soft-start function, a low-inductor current shutdown function, and so on. Also, a power good function
provide the status of output with using a power good (PGOOD) pin.
For EMI reduction, SSCG (Spread-Spectrum Clock Generator) for diffused oscillation frequency at the PWM
operation is optionally available. The R1273L is available in QFN0505-32B package.
This is a high-reliability semiconductor device for industrial application (-Y) that has passed both the screening
at high temperature and the reliability test with extended hours.
FEATURES
● Operating Voltage (Maximum Rating) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 4.0 V to 34 V (36 V)
● Operating Temperature Range ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ −40°C to 105°C
● Start-up Voltage ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 4.5 V
● Output Voltage Range ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 0.7 V to 5.3 V
● Feedback Voltage Tolerance ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 0.64 V ±1%
● Consumption Current at No Load(at VFM mode)ꞏꞏꞏꞏꞏꞏꞏ Typ.15 µA
● Adjustable Oscillation Frequency(1)ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 250 kHz to 1 MHz
● Synchronizable Clock Frequency(1)ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 250 kHz to 1 MHz
● Minimum On-Time ꞏꞏꞏ ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Typ.100 ns
● Minimum Off-Time ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Typ.120 ns (at regulation mode)
At dropout, actual minimum off-time is reduced.
● Adjustable Soft-start Time(2) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Typ.500 µs
● Pre-bias Start-up
● Anti-phase Clock Output
● Thermal Shutdown Function ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Tj = 160ºC (Typ.)
● Under Voltage Lockout (UVLO) Functionꞏꞏꞏꞏꞏꞏꞏꞏꞏ ꞏꞏꞏꞏꞏꞏꞏꞏ VCC = 3.3V (Typ.)
(1) The adjustable oscillation frequency range becomes 250 kHz ≤ fOSC ≤ 600 kHz when 0.7 V ≤ VOUT < 1.35V.
(2) 500 µs(Typ.) as a lower limit with using an external capacitor. Otherwise, available the tracking function through the
application of an external voltage.
1
R1273L-Y
NO.EY-352-190307
● Over Voltage Detection (OVD) Function ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ FB pin voltage (VFB) + 10% (Typ.)
Detection/Release Hysteresis ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ FB pin voltage (VFB) x 3% (Typ.)
● Under Voltage Detection (UVD) Functionꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ FB pin voltage (VFB) - 10% (Typ.)
Detection/Release Hysteresis ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ FB pin voltage (VFB) x 3% (Typ.)
● Selectable Over-current Protectionꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Hiccup-mode / Latch mode
● Selectable Current Limit Thresholdꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ 50 mV / 70 mV / 100 mV
● High-side / Low-side Tr. ON-resistance ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Typ.11.8 mΩ / 12.3 mΩ
● Power Good Output ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ NMOS Open-drain Output
● Packageꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ QFN0505-32B
APPLICATIONS
● Power source for car accessories including car audio equipment, car navigation system, and ETC system.
SELECTION GUIDE
The function and setting for the ICs are selectable at the user’s request.
Product Name
Package
Quantity per Reel
Pb Free
Halogen Free
R1273LxxyA-E2-Y
QFN0505-32B
1,000
Yes
Yes
xx : Select the combination of processing and function.
xx
00
01
03
10
11
13
Over Current Protection
Non-latch type hiccup mode
Latch mode
SSCG
Disable
Disable
Enable
Disable
Disable
Enable
Output Voltage Range
3.15 V < VOUT ≤ 5.3 V
3.15 V < VOUT ≤ 5.3 V
3.15 V < VOUT ≤ 5.3 V
0.7 V ≤ VOUT ≤ 3.15 V
0.7 V ≤ VOUT ≤ 3.15 V
0.7 V ≤ VOUT ≤ 3.15 V
Latch mode
Non-latch type hiccup mode
Latch mode
Latch mode
If required a version with SSCG function, please contact our sales offices.
y : Select the current limit threshold voltage.
Set Voltage for Current
Limit Threshold (Typ.)
y
1
2
3
50 mV
70 mV
100 mV
2
R1273L-Y
NO.EY-352-190307
BLOCK DIAGRAMS
Thermal Shutdown
0.6V
-
+
OVP
OVP
UVLO
INT Regulator
Int_Reg
Hiccup
/Latch
SHDN
-
+
1.2V
VCC Regulator
Mode
Select
PFC
Filter
SSCG_EN
VCO
OVD
Mode
Freq_NG
Freq
Detection
SHDN
CLK
Set_Pulse
Mode
OFF_Pulse
Drive
Circuit
VIN
VOUT
Mode
Rev
OFF_Pulse
Soft_Start
VFM Control
Over Voltage Detection
Under Voltage Detection
OVD
UVD
Rev
Reverse
Detection
Int_Reg
2uA
Mode
OVD
Set_Pulse
S
R
Q
SHDN
-
+
-
+
ILIM
OVD
Limit Current
Hiccup
/Latch
Hiccup/Latch
SHDN
OVP
Soft Start
Circuit
Soft_Start
Freq_NG
Peak Limit
Circuit
Reference
VOUT
VCC
Slope
Soft_Start
CLK
SHDN
OVD
UVD
VIN VOUT
R1273LxxxA
3
R1273L-Y
NO.EY-352-190307
PIN DESCRIPTIONS
Pin No.
Pin Name
Description
1
PGOOD
MODE
AGND
PGND
LX
Power-good output pin
Mode-set input pin
Analog GND pins
Power GND pins
Switching pins
2
3, 25
4, 5, 6, 7, 8
9, 10, 11, 12
13, 18, 20, 22
NC
No connection
14, 15, 16, 17, 23
VIN
Power supply pins
Bootstrap pin
19
21
24
26
27
28
29
30
31
32
BST
VCC
VCC output pin
CSS/TRK
CE
Soft-start adjustment pin
Chip enable pin (Active ”H”)
SENSE
VOUT
RT
Sense pin for Inductor current
Output voltage feedback input pin
Oscillation adjustment pin
COMP
FB
Capacitor connecting pin for Phase compensation of error amplifier
Feedback input pin for Error amplifier
Clock output pin
CLKOUT
4
R1273L-Y
NO.EY-352-190307
INTERNAL EQUIVALENT CIRCUIT FOR EACH PIN
VIN
Int_Reg
CE
< VIN Pin >
< CE Pin >
VIN
CSS/TRK
1kΩ
< CSS/TRK Pin >
< VOUT Pin >
< SENSE Pin >
< RT Pin >
5
R1273L-Y
NO.EY-352-190307
< COMP Pin >
< FB Pin >
< CLKOUT Pin >
< PGOOD Pin >
< MODE Pin >
< LX Pin >
6
R1273L-Y
NO.EY-352-190307
< BST Pin >
< VCC Pin >
< AGND-PGND Pins >
7
R1273L-Y
NO.EY-352-190307
ABSOLUTE MAXIMUM RATINGS
Symbol
VIN
Item
Rating
-0.3 to 36
-0.3 to 36
-0.3 to 3
Unit
V
VIN pin voltage
VCE
CE pin voltage
V
VCSS/TRK
VOUT
VSENSE
VRT
CSS/TRK pin voltage
VOUTpin voltage
SENSEpin voltage
RT pin voltage
V
-0.3 to 6
V
-0.3 to 6
V
-0.3 to 3
V
VCOMP
VFB
COMP pin voltage(1)
-0.3 to 6
V
FB pin voltage
-0.3 to 3
V
VCC pin voltage
-0.3 to 6
V
VCC
Output current for VCC pin
Internally Limited
LX-0.3 to LX+6
-0.3 to 36
-0.3 to 6
mA
V
VBST
VLX
BST pin voltage
LX pin voltage(2)
V
VMODE
VPGOOD
VCLKOUT
MODE pin voltage
PGOOD pin voltage
CLKOUT pin voltage(1)
V
-0.3 to 6
V
-0.3 to 6
V
Power Dissipation(3)
(QFN0505-32B, JEDEC STD.51-7 Test Land Pattern)
PD
2300
mW
Tj
Junction Temperature
-
-
40 to 125
55 to 125
C
C
Tstg
Storage Temperature Range
ABSOLUTE MAXIMUM RATINGS
Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent
damages and may degrade the life time and safety for both device and system using the device in the field.
The functional operation at or over these absolute maximum ratings are not assured.
RECOMMENDED OPERATING CONDITIONS
Symbol
VIN
Item
Rating
4.0 to 34
−40 to 105
0.7 to 5.3
Unit
V
Input Voltage
Ta
Operating Temperature Range
Output Voltage Range
°C
V
VOUT
RECOMMENDED OPERATING CONDITIONS
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the recommended
operating conditions, even if when they are used over such ratings by momentary electronic noise or surge. And the
semiconductor devices may receive serious damage when they continue to operate over the recommended
operating conditions.
(1) The pin voltage must be prevented from exceeding VCC +0.3V.
(2) The pin voltage must be prevented from exceeding VIN +0.3V.
(3) Refer to POWER DISSIPATION for detailed information.
8
R1273L-Y
NO.EY-352-190307
ELECTRICAL CHARACTERISTICS
VIN = 12 V, CE = VIN, unless otherwise specified.
The specifications surrounded by
are guaranteed by design engineering at -40°C ≤ Ta ≤ 105°C.
R1273LxxxA Electrical Characteristics
(Ta = 25°C)
Symbol
VSTART
VCC
Item
Start-up Voltage
VCC Pin Voltage (VCC - AGND) VFB = 0.672 V
Conditions
Min.
Typ.
Max.
4.5
5.3
8
Unit
4.9
5.1
3
V
ISTANDBY
Standby Current
VIN = 34 V, CE = 0 V,
µA
VFB = 0.672 V,
R1273L0xx MODE = 5 V,
1.0
1.15
15
1.15
1.75
44
VIN Consumption
Current 1 at
VOUT = SENSE = LX = 5V
IVIN1
mA
VFB = 0.672 V,
MODE = 5 V,
VOUT = SENSE = 1.5 V,
LX = 5V
Switching Stop in
PWM mode
R1273L1xx
VFB = 0.672 V,
R1273L0xx MODE = 0 V,
VOUT = SENSE = LX = 5V
VIN Consumption
Current 2 at
IVIN2
µA
VFB = 0.672 V,
MODE = 0 V,
VOUT = SENSE = 1.5 V,
LX = 5V
Switching Stop in
VFM mode
R1273L1xx
38
99
VUVLO2
VUVLO1
VCC Rising
3.85
3.1
4.0
3.3
4.2
3.4
V
V
UVLO Threshold Voltage
FB Voltage Accuracy
VCC Falling
Ta=25°C
0.6336
0.6272
225
0.6464
0.6528
275
VFB
0.64
V
-40°C ≤ Ta ≤ 105°C
RT = 135 kΩ
RT = 32 kΩ
fOSC0
fOSC1
tOFF
tON
Oscillation Frequency 0
Oscillation Frequency 1
Minimum Off Time
250
1000
120
kHz
kHz
ns
900
1100
190
VIN = 5 V, VOUT = 5 V
Minimum On Time
100
120
ns
fOSCꢀ 0.5
250
fOSCꢀ1.5
1000
0.75
kHz
kHz
ms
ms
µA
fSYNC
Synchronizing Frequency
fOSC as the reference
tSS1
tSS2
ITSS
Soft-start Time 1
Soft-start Time 2
CSS/TRK = OPEN
CSS = 4.7nF
0.4
1.4
2.0
Charge Current for Soft-start pin CSS/TRK = 0 V
CSS/TRK pin Voltage at End of
Soft-start
1.8
2
2.2
VFB
VSSEND
VFB
2.0
VFB+0.06
5.0
V
+0.03
Discharge Resistance for
CSS/TRK pin
VIN = 4.5 V, CE = 0 V,
CSS/TRK = 3 V
RDIS_CSS
3.0
kΩ
9
R1273L-Y
NO.EY-352-190307
VIN = 12 V, CE = VIN, unless otherwise specified.
The specifications surrounded by
are guaranteed by design engineering at -40°C ≤ Ta ≤ 105°C.
R1273LxxxA Electrical Characteristics Continued
(Ta = 25°C)
Max. Unit
Symbol
Item
Conditions
Min.
40
Typ.
50
60
80
mV
mV
mV
mV
mV
mV
Current Limit Threshold Voltage
(SENSE – VOUT)
VILIMIT
60
70
90
100
-25
-35
-50
110
-15
-25
-40
-35
-45
-60
Reverse Current Sense
Threshold Voltage
VIREVLIMIT
MODE = H / CLK
(SENSE – VOUT)
LX Shot to GND Detector
Threshold Voltage (VIN – LX)
LX Short to VCC Detector
Threshold Voltage (LX – PGND)
CE ”H” Input Voltage
VLXSHORTL
VLXSHORTH
0.345
0.43
0.43
0.520
0.515
V
V
0.330
1.27
VCEH
V
V
VCEL
CE ”L” Input Voltage
1.14
2.45
1.00
0.1
ICEH
CE ”H” Input Current
CE = 34 V
CE = 0 V
VFB = 3 V
VFB = 0 V
0.20
-1.00
-0.1
µA
µA
µA
µA
V
ICEL
CE ”L” Input Current
0
IFBH
FB ”H” Input Current
IFBL
FB ”L” Input Current
-0.1
0.1
VMODEH
VMODEL
IMODEH
IMODEL
VCLKOUTH
VCLKOUTL
MODE ”H” Input Voltage
MODE ”L” Input Voltage
MODE ”H” Input Current
MODE ”L” Input Current
Clock Output High Voltage
Clock Output Low Voltage
Temperature at Thermal
Shutdown Detection
1.33
0.74
6.60
1.0
V
MODE = 6 V
1.00
-1.0
4.7
0
µA
µA
V
MODE = 0 V
0
CLKOUT = Hi-Z
CLKOUT = Hi-Z
VCC
0.1
V
TTSD
TTSR
Ta Rising
Ta Falling
150
125
160
140
0.26
0
°C
°C
V
Temperature at Thermal
Shutdown Release
VIN = 4.0 V,
VPGOODOFF PGOOD Pin ”OFF” Voltage
0.54
0.10
PGOOD = 1 mA
VIN = 34 V, CE = 0 V,
PGOOD = 6 V
VFB Rising
IPGOODOFF
PGOOD Pin ”OFF” Current
-0.10
nA
VFBOVD1
VFBOVD2
0.680 VFBꢀ1.10 0.740
V
V
FB Pin OVD Threshold Voltage
0.712
0.604
VFB Falling
0.664 VFBꢀ1.07
0.556 VFBꢀ0.90
VFBUVD1
VFBUVD2
gm (EA)
VFB Falling
V
V
FB Pin UVD Threshold Voltage
Trans Conductance Amplifier
VFB Rising
0.574 VFBꢀ0.93 0.628
0.35 1.55
COMP = 1.5 V,
1
mS
All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C).
10
R1273L-Y
NO.EY-352-190307
OPERATING DESCRIPTIONS
MODE Pin Function
The R1273L operating mode is switched among the forced PWM mode, PWM/VFM auto-switching mode and
PLL_PWM mode, by a voltage or a pulse applied to MODE pin. The forced PWM mode is selected when the
voltage of the MODE pin is more than 1.33 V, and the PWM works regardless of a load current. The PWM/VFM
auto-switching mode is selected when it is less than 0.74 V, and control is switched between a PWM mode
and a VFM mode depending on the load current.
See Forced PWM mode and VFM mode for details. And see Frequency Synchronization Function for the
operation on connecting an external clock.
Frequency Synchronization Function
The R1273L can synchronize to the external clock being inputted via the MODE pin, with using a PLL (Phase-
locked loop). The forced PWM mode is selected during synchronization. The external clock with a pulse-width
of 100 ns or more is required. The allowable range of oscillation frequency is 0.5 to 1.5 times of the set
frequency(1), and the operating guaranteed frequency is in the 250 kHz to 1 MHz range(2). The R1273L can
synchronize to the external clock even if the soft-start works. That is, the R1273L executes the soft-start and
the synchronization functions at a time if having started up while inputting an external clock to the MODE pin.
When the maxduty or the duty_over state is caused by reduction in differential between input and output
voltages, the device runs at asynchronous to the MODE pin, and it operates in the frequency reduced until
one-fourth of the external clock frequency. Likewise, the CLKOUT pin becomes asynchronous to the MODE
pin. If making synchronization to the MODE pin, take notice in use under a reduced input voltage.
Duty_over Function
When the input voltage is reduced at cranking, the operating frequency is reduced until one-fourth of the set
frequency with being linearly proportional to time in order to maintain the output voltage. Exploiting the ON
duty to exceed the maxduty value at normal operation can make the differential between input and output
voltages small.
PGOOD (Power Good) Output Function
The power good function with using a NMOS open drain output pin can detect the following states of the
R1273L. The NMOS turns on and the PGOOD pin becomes “Low” when detecting them. After the R1273L
returns to their original state, the NMOS turns off and the PGOOD pin outputs “High” (PGOOD Input Voltage:
VUP).
・CE = “L” (Shut down)
・UVLO (Shut down)
(1) See Oscillation Frequency Setting for details of the set frequency.
(2) The adjustable oscillation frequency range becomes 250 kHz ≤ fOSC ≤ 600 kHz when 0.7 V ≤ VOUT < 1.35V.
11
R1273L-Y
NO.EY-352-190307
・Thermal Shutdown
・Soft-start time
・at UVD Threshold Voltage Detection
・at OVD Threshold Voltage Detection
・at hiccup-type Protection (when hiccup mode is selected)
・at latch-type Protection (when latch mode is selected)
The PGOOD pin is designed to become 0.54 V or less in “Low” level as the flag when the current floating to
the PGOOD pin is 1 mA. The use of the PGOOD input voltage (VUP) of 5.5 V or less and the pull-up resistor
(RPG) of 10 kΩ to 100 kΩ are recommended. If not using the PGOOD pin, connect it to “Open” or “GND”.
PGOOD Output Pin Connecting Diagram
Rising / Falling Sequence of Power Good Circuit
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Under Voltage Detection (UVD)
The UVD function indirectly monitors the output voltage with using the FB pin. The PGOOD pin outputs “L”
when the UVD detector threshold is 90% (Typ.) of VFB and VFB is less than the UVD detector threshold for
more than 30 µs (Typ.). When VFB is over 93% (Typ.) of 0.64 V, the PGOOD pin outputs “H” after delay time
(Typ.120 µs.). And, the hiccup- / latch-type overcurrent protection works when detecting an overcurrent, an LX
power supply protection, or an over voltage protection during the UVD detection.
Over Voltage Detection (OVD)
The OVD function indirectly monitors the output voltage with using the FB pin. Switching stops even if the
internal circuit is active state, when detecting the over voltage of VFB. The PGOOD pin outputs “L” when the
OVD detector threshold is 110% (Typ.) of VFB and VFB is over the OVD detector threshold for more than 30 µs
(Typ.). When VFB is under 107% (Typ.) of VFB, which is the OVD released voltage, the PGOOD pin outputs “H”
after delay time (Typ.120 µs.). Then, switching is controlled by normal operation. The over voltage protection
works when an error is caused by a feedback resistor in peripheral circuits for the FB pin.
Over Voltage Protection (OVP)
The OVP function monitors the voltage of VOUT pin to reduce an over voltage, when an error is caused in
peripheral circuits for the FB pin. Switching stops even if the internal circuit is active state, when VOUT is over
the OVP detector threshold. When VOUT is under the OVP detector threshold, switching is controlled by normal
operation. If the UVD for FB pin occur during the OVP detect state, an error will occur and hiccup- / latch-type
protection will work. However, the operation under this function is not guaranteed because the OVP detector
threshold is set to the absolute maximum rating and more for the VOUT pin.
LX Power Supply (VIN Short) / GND (GND Short ) Protection
In addition to normal current limit, the R1273L provides the LX power supply / GND short protection to monitor
the voltage between the transistor’s drain and source. Since the current limit function is controlled with an
external inductor’s DCR or a sense resistance, the current limit function cannot work when a through-current
is flowed through the transistor and when an overcurrent is generated by shorting the LX pin to VDD/GND.
The detecting current is determined by LX shot to VDD/GND detector threshold voltage (Transistor_ON-
Resistance x Current, Typ.0.43 V).
Hiccup-type / Latch-type Overcurrent Protection
The hiccup-type / latch-type overcurrent protection can work under the operating conditions that is the UVD
can function during the current limit or OVP and the LX GND short protection. The latch-type protection can
release the circuit by setting the CE pin to “L” or by reducing VIN to be less than the UVLO detector threshold,
when the output is latched off. The hiccup type protection stops switching releases the circuit after the
protection delay time (Typ. 3.5 ms). Since this protection is auto-release, the CE pin switching of “L” / “H” is
unnecessary. And, damage due to the overheating might not be caused because the term to release is long.
When the output is shorted to GND, switching of “ON” / “OFF” is repeated until the shorting is released.
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Current Limit Function
The current limit function can be to limit the current by the peak current method to turn the high-side transistor
off that the potential differences is over the current limit threshold voltage. The threshold voltage is selectable
among 50 mV / 70 mV / 100 mV. And, the two following detection methods can be selected by external
components connected.
A. Detecting Method with RSENSE
The current limit value is detected with the voltage across the inductor that a sense resistance is connected in
series. By connecting a resistance with low level of variation, the current limit with high accuracy can achieve.
As a result, be caution that the power loss is caused from the current and RSENSE. The peak current in the
current limit inductor can be calculated by the following equation.
Peak current in Current limit inductor (A) = Current limit threshold voltage (mV) / RSENSE (mΩ)
Figure A Detection with Sense Resistance
B. Detecting Method with DCR of Inductor
The current limit value is detected with the DCR of the inductor. The reduction of the loss is minimized since
the inductor is in no need of a resistance. But, the SENSE pin requires to connect a resistor and a capacitor
to each end of the inductor. Because a constant slope is caused depending on the inductance and the
capacitance. Factors causing the poor accuracy of current limit value include the variation in production of the
inductor’s DCR and the temperature characteristics. RS and CS can be calculated by the following equation.
Peak current in Current limit inductor (A) = Current limit threshold voltage (mV) / Inductor’s DCR (mΩ)
CS = L / (DCR x RS)
Figure B Detecting with Inductor’s DCR
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Output Voltage Setting
The output voltage (VOUT) can be set by adjustable values of RTOP and RBOT. The value of VOUT can be
calculated by Equation 1 :
VOUT = VFB × (RTOP + RBOT) / RBOT ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 1
For example, when setting VOUT = 3.3 V and setting RBOT = 22 kΩ, RTOP can be calculated by substituting them
to Equation 1. As a result of the expanding Equation 2, RTOP can be set to 91.4 kΩ.
To make 91.4 kΩ with using the E24 type resistors, the connecting use of 91 kΩ and 0.39 kΩ resistors in series
is required. If the tolerance level of the set output voltage is wide, using a resistor of 91 kΩ to RTOP can reduce
the number of components.
R
TOP = (3.3 V / 0.64 V - 1) × 22 kΩ
= 91.4 kΩ ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 2
As to R1273L00x, R1273L01x and R1273L03x, RTOP and RBOT should be selected to meet the required output
voltage (VOUT) > 2.91 V with a variation in resistance taken into account.
Oscillation Frequency Setting
Connecting the oscillation frequency setting resistor (RRT) between the RT pin and GND can control the
oscillation frequency in the range of 250 kHz to 1 MHz(1). For example, using the resistor of 66 kΩ can set the
frequency of about 500 kHz.
The Electrical Characteristics guarantees the oscillation frequency under the conditions stated below for fOSC0
(at RRT = 135 kΩ) and fOSC1 (at RRT = 32 kΩ).
RRT [kΩ] = 41993 x fOSC [kHz] ^ (-1.039)
R1273L001A Oscillation Frequency Setting Resistor (RRT) vs. Oscillation Frequency (fOSC
)
(1) The adjustable oscillation frequency range becomes 250 kHz ≤ fOSC ≤ 600 kHz when 0.7 V ≤ VOUT < 1.35V.
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Soft-start Function
The soft-start time is a time between a rising edge (“H” level) of the CE pin and the timing when the output
voltage reaches the set output voltage. Connecting a capacitor (CSS) to the CSS / TRK pin can adjust the soft-
start time (tSS) – provided the internal soft-start time of 500 µs (Typ.) as a lower limit. The adjustable soft-start
time (tSS2) is 1.6 ms (Typ.) when connecting an external capacitor of 4.7 nF with the charging current of 2.0
μA (Typ.). If not required to adjust the soft-start time, set the CSS / TRK pin to “Open” to enable the internal
soft-start time (tSS1) of 500 µs (Typ.).
If connecting a large capacitor to an output signal, the overcurrent protection or the LX GND short protection
might run. To avoid these protections caused by starting abruptly when reducing the amount of power current,
soft-start time must be set as long as possible.
Each of soft-start time (tss1/ tss2) is guaranteed under the conditions described in the chapter of “Electrical
Characteristics”.
CSS [nF] = (tSS - tVO_S) / 0.64 × 2.0
tSS: Soft-start time (ms)
tVO_S: Time period from CE = “H” to VOUT’s rising
(Typ. 0.160 ms)
Soft-start Time Adjustable Capacitor (CSS) vs. Soft-start Time (tSS)
Soft-start Sequence
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Tracking Function
Applying an external tracking voltage to the CSS / TRK pin can control the soft-start sequence – provided that
the lowest internal soft-start time is limited to 500 µs (Typ.). Since VFB becomes nearly equal to VCSS/TRK at
tracking, the complex start timing and soft-start can be easily designed. The available voltage at tracking is
between 0 V and 0.64 V. If the tracking voltage is over 0.64 V, the internal reference voltage of 0.64 V is
enabled. Also, an arbitrary falling waveform can be generated by reducing VCSS/TRK to 0.64 V (Typ.) or less,
because the R1273L supports both of up- and down- tracking.
Tracking Sequence
Min. ON-time
The min. ON time (Max. 120 ns), which is determined in the R1273L internal circuit, is a minimum time to turn
high-side transistor on. The R1273L cannot generate a pulse width less than the min. ON time. Therefore,
settings of the output set voltage and the oscillator frequency are required so that the minimum step-down
ratio [VOUT/VIN x (1 / fOSC)] does not stay below 120ns. If staying below 120 ns, the pulse skipping will operate
to stabilize the output voltage. However, the ripple current and the output voltage ripple will be larger.
Min. OFF-time
By the adoption of bootstrap method, the high-side transistor, which is used as the R1273L internal circuit for
the min. OFF time, is used a NMOS. The voltage sufficient to drive the high-side transistor must be charged.
Therefore, the min. OFF time is determined from the required time to charge the voltage. By the adoption of
the frequency’s reduction method by one-quarter of a set value (Min.), if the input-output difference voltage
becomes small or load transients are caused, the OFF period can be caused once in four-cycle period of
normal cycle. As a result, the min. OFF time becomes 30 ns (Typ.) substantially, and the maximum duty cycle
can be improved.
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Reverse Current Limit Function
The reverse current limit function works when the output voltage is pulled up more than the set output voltage
by shorting. When the current is over the threshold current to detect the reverse current, the low-side transistor
is turned OFF to control the reverse current. As with the current limit value, the reverse current limit value is
determined by the voltage between the VOUT pin and the SENSE pin. The detector threshold is one half of
the current limit value.
SSCG (Spread Spectrum Clock Generator)
The SSCG function works for EMI reduction at the PWM mode. This function is enabled in the R1273L03xA.
This function make EMI waveforms decrease in amplitude to generate a ramp waveform within approximately
±3.6% (Typ.) of the oscillator frequency (fOSC). The modulation cycle is fOSC / 128. At the VFM mode, the SSCG
is disabled.
Bad Frequency (BADFREQ) Protection
If a current equivalent to 2 MHz (Typ.) or more or 125 kHz (Typ.) or less is applied to the RT pin when the
resistor of the RT pin is in open / short, the R1273L will stop switching to protect the IC and will cause the
internal state to transition to its state before the soft-start. The CLKOUT pin is fixed to “L” while the bad
frequency as above is detected. The R1273L will restart under the normal control from the state of soft-start
when recover after the abnormal condition.
BADFREQ Detection / Release Sequence
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Operation of the Step-down Converter
A basic step-down DC/DC converter circuit is illustrated in the following figures. This DC/DC converter charges
energy in the inductor when the high-side transistor turns on, and discharges the energy from the inductor
when the high-side transistor turns off and controls with less energy loss, so that a lower output voltage than
the input voltage is obtained.
IL
ILMAX
i1
H-side Tr.
L-side Tr.
ILMIN
tOPEN
V
IN
VOUT
L
i2
COUT
GND
tON
tOFF
t=1/ fOSC
Basic Circuit
Current Through Inductor
Step1. The high-side transistor turns on and current IL (= i1) flows, and energy is charged into COUT. At this
moment, IL increases from ILMIN (= 0) to reach ILMAX in proportion to the on-time period (ton) of the
high-side transistor turns on and current IL (= i1) flows, and energy is charged into COUT. At this
moment, IL increases from ILMIN (= 0) to reach ILMAX in proportion to the on-time period (tON) of the
high-side transistor.
Step2. When the high-side transistor turns off, the low-side transistor turns on in order to maintain IL at ILMAX
,
and current IL (= i2) flows.
Step3. When MODE = L (VFM/PWM Auto-switching mode),
IL (= i2) decreases gradually and reaches IL = ILMIN = 0 after a time period of tOPEN, and the low-side
transistor turns off. This case is called as discontinuous mode. The VFM mode is switched if go to
the discontinuous mode. If the output current is increased, a time period of tOFF runs out prior to reach
of IL = ILMIN = 0. The result is that the high-side transistor turns on and the low-side transistor turns off
in the next cycle. This case is called continuous mode.
When MODE = H (Forced PWM mode), MODE = External Clock (PLL_PWM mode),
Since the continuous mode works at all time, the low-side transistor turns on until going to the next
cycle. That is, the low-side transistor must keep “On” to meet IL = ILMIN < 0, when reaches IL = ILMIN
0 after a time period of tOPEN
=
.
In the PWM mode, the output voltage is maintained constant by controlling tON with the constant switching
frequency (fOSC).
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Forced PWM Mode and VFM Mode
The output voltage control methods are selectable between the PWM / VFM Auto-switching mode and the
forced PWM mode by using the MODE pin.
Forced PWM Mode
Forced PWM mode is selected when setting the MODE pin to “H”. This mode can reduce the output noise,
since the frequency is fixed during light load conditions. Thus, ILMIN becomes less than "0" when IOUT is less
than ∆IL/2. That is, the electric charge, which is charged to COUT, is discharged via transistor for the durations
– when IL reaches “0” from ILMIN during the tON periods and when IL reaches ILMIN from “0” during tOFF periods.
But, pulses are skipped to prevent the overvoltage when high-side transistor is set to ON under the condition
that the output voltage being more than the set output voltage.
VFM Mode
PWM / VFM Auto-switching mode is selected when setting the MODE pin to “L”. This mode can automatically
switch from PWM to VFM to achieve a high-efficiency during light load conditions. By the VFM mode
architecture, the high-side transistor is turned on for tON x 1.54 (typ.) at the PWM mode under the same
condition as the VFM mode when the VFB pin voltage drops below the internal reference voltage (Typ.0.64 V).
After the On-time, the high-side transistor is turned off and the low-side transistor is turned on. When the
inductor current of 0 A is detected, the low-side transistor is turned off and the switching operation is stopped
(Both of hi- and low-side transistors are OFF). The switching operation restarts when the VFB pin voltage
becomes less than 0.64 V.
The On-time at the PWM mode is determined by a resistance, input and output voltages, which are connected
to the RT pin. Refer to “Calculation of VFM Ripple” for detailed description on the On-time at the VFM mode.
ILMAX
IL
ILMAX
IL
ΔIL
IOUT
0
0
ILMIN
ILMIN
t
t
tON
tOFF
T=1/fOSC
tON
tOFF
Forced PWM Mode
VFM Mode
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Calculation of VFM Ripple
Calculation example of output ripple voltage (VOUT_VFM) is described. VOUT_VFM can be calculated by Equation
1. And, the maximum value of inductor current (IL_VFM) can be calculated by Equation 2.
VOUT_VFM = RCOUT_ESR × (IL_VFM) + COEF_TON_VFM × (IL_VFM / 2) / fOSC / COUT_EFF ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 1
IL_VFM = ((VIN -VOUT) / L) × COEF_TON_VFM × VOUT / VIN / fOSCꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 2
V
OUT_VFM : Output ripple
COUT_ESR : ESR of output capacitor
IL_VFM : Maximum current of inductor
OEF_TON_VFM : Scaling factor of On-time - Typ.1.54X (Design value)
R
C
(VIN-VOUT) / L : Slope of inductor current
COEF_TON_VFM × VOUT / VIN / fOSC : On-time
IL (A)
Inductor Current (Max.)
IL_VFM
Slope
Slope
⊿IL=(VIN-VOUT)/L
⊿IL= VOUT/L
Average Area of
IL (A) x Time (s)
Time(s)
T2
T1
H-side Tr.
L-side Tr.
Inductor Current Waveform at VFM Mode
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Output voltage can be calculated by the following simple equation.
VOUT = I × T/C
I : Current, C : Capacitance, T : Time
Since I is represented by 1/2 x IL_VFM as the average current, the time of current passing at the VFM mode can
be expressed by the following equation.
T = COEF_TON_VFM / fOSC
And, the output ripple voltage (VOUT_VFM) is superimposed a voltage for ESR × I, and Equation 1 is determined.
But, ESR is so small that it may be ignored if ceramic capacitors are connected in parallel.
The amount of charge to the output capacitor can be calculated by Equation 3.
(High-side Tr. On-time (T1) + Low-side Tr. On-time (T2)) × Average amount of current
ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 3
Then, T1 and T2 can be calculated by the following equations, and the time of current passing can be
determined.
T1 = COEF_TON_VFM / fOSC × VOUT / VINꞏꞏꞏꞏꞏ (On-time at VFM)
T2 = (VIN/VOUT-1) × T1 (0 = IL_VFM – VOUT/L × T2)
T = T1 + T2
= VIN /VOUT × T1
= COEF_TON_VFM / fOSC
And then, the amount of charge can be determine as Equation 4.
T x IL_VFM /2 = COEF_TON_VFM / fOSC × IL_VFM /2 ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 4
With using above-equations, the output ripple voltage (VOUT_VFM) can be calculated by Equation 5.
V = IT/C = COEF_TON_VFM / fOSC × IL_VFM / 2 / COUT_EFF ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 5
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APPLICATION INFORMATION
Typical Application Circuit
Cvcc
Cbst
Css
Cin1 Cin2
AGND
CE
VIN
VIN
VIN
N.C.
LX
SENSE
Rs
Cs
VOUT
Rt
RT
R1273LxxxA
Cc
L
COMP
FB
LX
VOUT
Rc
LX
Cc2
CLKOUT
LX
Cout
Rtop
Cspd
Rflag
R1273LxxxA Typical Application Circuit
Selection of External Components
External components and its value required for R1273L are described. Each value is reference value at initial.
Since inductor’s variations and output capacitor’s effective value may lead a drift of phase characteristics,
adjustment to a unity-gain and phase characteristics may be required by evaluation on the actual unit.
1. Determination of Requirements
Determine the frequency, the output capacitor, and the input voltage required. For reference values,
parameters listed in the following table will be used to explain each equation.
Parameter
Output Voltage (VOUT
Value
3.3 V
)
Output Current (IOUT
Input Voltage (VIN)
)
10 A
12 V
Input Voltage Range
Frequency (fOSC
ESR of Output Capacitor (RCOUT_ESR
8 V to 16 V
500 kHz
3 mΩ
)
)
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2. Selection of Unity-gain frequency (fUNITY
)
The unity-gain frequency (fUNITY) is determined by the frequency that the loop gain becomes “1” (zero dB). It is
recommended to select within the range of one-sixth to one-tenth of the oscillator frequency (fOSC). Since the
fUNITY determines the transient response, the higher the fUNITY, the faster response is achieved, but the phase
margin will be tight. Therefore, it is required that the fUNITY can secure the adequate stability. As for the reference,
the fUNITY is set to 70 kHz.
3. Selection of Inductor
After the input and the output voltages are determined, a ripple current (∆IL) for the inductor current is
determined by an inductance (L) and an oscillator frequency (fOSC). The ripple current (∆IL) can be calculated
by Equation 1.
∆IL= (VOUT / L / fOSC) x (1-VOUT / VIN_MAX) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 1
VIN_MAX : Maximum input voltage
The core loss in the inductor and the ripple current of the output voltage become small when the ripple current
(∆IL) is small. But, a large inductance is required as shown by Equation 1. The inductance can be calculated
by Equation 2 when a reference value of ∆IL assumes 30% of IOUT is appropriate value.
L = (VOUT / ∆IL / fOSC) x (1-VOUT / VIN_MAX)ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 2
= (VOUT / (IOUT x 0.3) / fOSC) x (1-VOUT / VIN_MAX
)
The inductance can be calculated by substituting each parameter to Equation 2.
L = (3.3 V / 3 A / 500 kHz) x (1-3.3 V / 16 V)
= 1.75 µH
When selecting the inductor of 2.2µH as an approximate value of the above calculated value, ∆IL can be shown
as below.
∆IL = (3.3 V / 2.2 µH / 500 kHz) x (1-3.3 V / 16 V)
= 2.38 A
4. Setting of Output Capacitance
The output capacitance (COUT) must be set to meet the following conditions.
■ Calculation based on phase margin
To secure the adequate stability, it is recommended that the pole frequency (fP_OUT) is set to become equal or
below one-fourteenth of the unity-gain frequency. The pole frequency (fP_OUT) can be calculated by Equation 3.
fP_OUT = 1/(2 x π x COUT_EFF x ((ROUT_MIN x 2 x π x fOSC x L) / (ROUT_MIN + 2 x π x fOSC x L) + RCOUT_ESR))
ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 3
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COUT_EFF : Output capacitance (rms)
R
R
OUT_MIN : Output resistance at maximum output current
OUT_MIN = VOUT/ IOUT
= 3.3 V / 10 A
= 0.33 Ω
Equation 4 can be expressed by substituting fP_OUT = fUNITY / 14 to Equation 3.
COUT_EFF = 14 / (2 ×π× fUNITY × ((ROUT_MIN × 2 ×π× fOSC × L) / (ROUT_MIN + 2 ×π× fOSC × L) + RCOUT_ESR))
ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 4
Then, the output capacitance (rms) can be calculated by substituting each parameter to Equation 4.
C
OUT_EFF =14 / (2 ×π×70kHz×((0.33Ω × 2 ×π× 500 kHz × 2.2 µH) / (0.33Ω+ 2 ×π× 500kHz × 2.2µH)+3mΩ))
= 100.1 µF
It is recommended that the output capacitance is set to become equal or over the value (rms) calculated by
Equation 4.
The output capacitance (rms), which is derated depending on the DC voltage applied, can be calculated by
Equation 5. Refer to “Capacitor Manufacture’s Datasheet” for details about derating.
C
OUT_EFF = COUT_SET × (VCO_AB - VOUT) / VCO_AB ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 5
COUT_SET : Output capacitor’s spec
VCO_AB : Capacitor’s voltage rating
With using Equation 5, the effective value (rms) is calculated to become 100.1 µF or more. The output
voltage (COUT) can be shown as below when VCO_AB is 10 V.
C
C
C
OUT_SET > COUT_EFF / ((VCO_AB - VOUT) / VCO_AB
OUT_SET > 100.1µF / ((10 - 3.3) / 10)
OUT > 149.4 µF
)
As the calculated result, COUT selects a capacitor of 150 µF (rms is 100.5 µF).
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■ Calculation based on ripple at VFM mode
With using the calculated value of COUT, the amount of ripple at the VFM mode can be shown as Equations 6
and Equation 7.
IL_VFM = ((VIN_MAX-VOUT) / L) × COEF_TON_VFM × VOUT / VIN_MAX / fOSC ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 6
VOUT_VFM = RCOUT_ESR × (IL_VFM) + COEF_TON_VFM × (IL_VFM / 2) / fOSC / COUT_EFF ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 7
IL_VFM : Maximum current of inductor
C
OEF_TON_VFM : On-time scaling (multiples of PWM_ON time)
VOUT_VFM : Maximum output ripple
C
OEF_TON_VFM can be calculated by 1.54 times (Typ.) as the design value. The ripple value can be calculated by
substituting each parameter to Equations 6 and Equation 7.
IL_VFM = ((16 V - 3.3 V ) / 2.2 µH) × 1.54 × 3.3 V / 16 V / 500 kHz
= 3.67 A
VOUT_VFM = 3 mΩ ×3.67 A + 1.54 × (3.67 A / 2) / 500 kHz / 100.5 µF
= 67.2 mV
VOUT_VFM must be set to become the target ripple value or less. If VOUT_VFM is over the target value, the output
capacitance must be calculated by Equation 8.
C
OUT_EFF = 1.54 × (IL_VFM / 2) / fOSC / (VOUT_VFM - RCOUT_ESR × (IL_VFM)) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 8
5. Designation of Phase Compensation
Since the current amplifier for the voltage feedback is output via the COMP pin, the phase compensation is
achieved with using external components. The phase compensation is able to secure stable operation with
using an external ceramic capacitor and the phase compensation circuit.
VOUT
CSPD
RTOP
ERROR_AMP
VFB
COMP
-
+
RBOT
RC
VREF
0.64V
CC CC2
Connection Example for External Phase Compensation Circuit
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NO.EY-352-190307
■ Calculation of RC
The phase compensation resistance (RC) to set the calculated unity-gain frequency can be calculated by
Equation 9.
RC = 2 ×π× fUNITY × VOUT × COUT_EFF / (gm_ea × VREF × gm_pwr) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 9
g
m_ea : Error amplifier of gm
REF : Reference voltage (0.64 V)
gm_pwr : power level of gm
V
g
m_pwr × ∆VS = ∆IL
gm_ea / ∆VS = 0.05 × 10 ^ (-6) × fOSC / VOUT
gm_ea × gm_pwr = 0.05 × 10 ^ (-6) ×∆IL × fOSC / VOUT ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 10
∆VS : Output amplitude of the slope circuit
RC can be calculated by substituting Equation 10 to Equation 9.
RC = 2 ×π× fUNITY × VOUT × COUT_EFF / (VREF × 0.05 × 10 ^ (-6) × ∆IL × fOSC / VOUT
)
= 2 ×π× 70 kHz × 3.3 V × 100.5 µF / (0.64 × 0.05 × 10 ^ (-6) × 2.38A × 500 kHz / 3.3 V)
=12.63 ≒13 kΩ
■ Calculation of CC
CC must be calculated by Equation 11 so that the zero frequency of the error amplifier meets the highest pole
frequency (fP_OUT). Then, fP_OUT = 5.0 kHz is determined by calculation of Equation 3.
CC = 1 / (2 ×π× RC × fP_OUT) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 11
= 1/ (2 × 3.14 ×13 kΩ × 5.0 kHz)
= 2.45 ≒ 2.7 nF
■ Calculation of CC2
CC2 can be calculated by two different calculation methods to vary from the zero frequency (fZ_ESR) depending
on the ESR of a capacitor. fZ_ESR can be calculated by Equation 12.
fZ_ESR = 1 / (2 ×π× RCOUT_ESR × COUT_EFF) ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 12
= 528 kHz
[When the zero frequency is lower than fOSC / 2]
CC2 sets the pole to fZ_ESR
.
C
C2 = RCOUT_ESR × COUT_EFF / RCꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 13
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R1273L-Y
NO.EY-352-190307
[When the zero frequency is higher fOSC / 2]
C
C2 sets the pole to fOSC / 2 so as to be a noise filter for the COMP pin.
fOSC / 2 = 1 / (2 ×π× RC × CC2)
C2 = 2 / (2 ×π× RC × fOSC)ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 14
C
In the reference example, CC2 is used as the noise filter for the COMP pin because of being higher than fOSC/2.
CC2 = 49 ≒ 47 pF
■ Calculation of CSPD
C
SPD sets the zero frequency to meet the unity-gain frequency.
R
TOP = RBOT × (VOUT / VREF -1)
CSPD = 1 / (2 ×π× fUNITY × RTOP)ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏEquation 15
When RBOT = 22 kΩ,
RTOP = 22 k × (3.3 V / 0.64 V -1)
= 91.4 kΩ
CSPD = 1 / (2 ×π× 70 kHz × 91.4 kΩ)
= 24.8 ≒ 27 pF
Cautions in Selecting External Components
Inductor
● Choose an inductor that has small DC resistance, has sufficient allowable current and is hard to cause
magnetic saturation. The inductance value must be determined with consideration of load current under the
actual condition. If the inductance value of an inductor is extremely small, the peak current of LX may
increase along with the load current. As a result, the current limit circuit may start to operate when the peak
current of LX reaches to “LX limit current”.
Capacitor
● Choose a capacitor that has a sufficient margin to the drive voltage ratings with consideration of the DC
bias characteristics and the temperature characteristics.
● The use of a ceramic capacitor for CIN is recommended. If combined use of a ceramic and an electrolyte
capacitors, the stable operation will improve since the margin becomes bigger. Choose the electrolyte
capacitor with the lowest possible ESR with consideration of the allowable ripple current rating (IRMS). IRMS
can be calculated by the following equation.
IRMS ≒ IOUT/ VIN x √{ VOUT x (VIN – VOUT) }
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TECHNICAL NOTES
The performance of power source circuits using this IC largely depends on peripheral circuits. When selecting
the peripheral components, please consider the conditions of use. Do not allow each component, PCB pattern
or the IC to exceed their respected rated values (voltage, current, and power) when designing the peripheral
circuits.
● External components must be connected as close as possible to the ICs and make wiring as short as
possible. Especially, the capacitor connected in between VIN pin and GND pin must be wiring the shortest.
If their impedance is high, internal voltage of the IC may shift by the switching current, and the operating
may be unstable. Make the power supply and GND lines sufficient.
● Place a capacitor (COUT) to keep a distance between CIN and COUT in order to avoid the high-frequency
noise by input.
● AGND and PGND must be wired to the GND line at the low impedance point of the same layer with CIN and
COUT
.
● Place a capacitor (CBST) as close as possible to the LX pin and the BST pin. If controlling a slew rate of the
high-side transistor for EMI, a resistor (RBST) should be in series between the BST pin and the capacitor
(CBST).
● The NC pin must be set to “Open”.
● The MODE pin requires the H / L voltages with the high stability when the forced PWM mode (MODE = “H”)
or the VFM mode (MODE = “L”) is enabled. If the voltage with the high stability cannot be applied,
connection to the VCC pin as “H” level or the AGND pin as “L” level is recommended. If connecting to the
PGND pin as noisy, a malfunction may occur. Avoid the use of the MODE pin being “Open”.
● If VOUT is a minus potential, the setup cannot occur.
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R1273L-Y
NO.EY-352-190307
Reference PCB Layouts
R1273LxxxA
PCB Layout -1st Layer (Top Layer)
PCB Layout -2nd Layer
30
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NO.EY-352-190307
PCB Layout -3rd Layer
PCB Layout -4th Layer (Bottom Layer)
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TYPICAL CHARACTERISTICS
Typical Characteristics are intended to be used as reference data, they are not guaranteed.
1) FB Voltage vs. Temperature
2) Oscillation Frequency vs. Temperature
250 kHz (RT = 135 kΩ)
600 kHz (RT = 55 kΩ)
3) Soft-start time 1 vs. Temperature
Fixed soft-start time
(CSS = Open)
Adjustable soft-start time
(CSS = 4.7 nF)
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R1273L-Y
NO.EY-352-190307
4) Current limit threshold voltage vs. Temperature
Current limit threshold voltage
(R1273Lxx2x)
Overcurrent limit threshold voltage
(R1273Lxx2x)
5) LX GND/VIN short threshold voltage vs. Temperature
LX GND short threshold voltage
(VIN-LX)
LX VIN short threshold voltage
(LX-PGND)
6) Current consumption vs. Temperature
Current consumption (VFM)
(VIN = 12V)
Current consumption (PWM)
(VIN = 12V)
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NO.EY-352-190307
7) UVLO vs. Temperature
UVLO release voltage
UVLO threshold voltage
8) CE input voltage vs. Temperature
CE “H” input voltage
CE “L” input voltage
9) Driver On-resistance
High-side Driver On-resistance
Low-side Driver On-resistance
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NO.EY-352-190307
10) Output current vs. Efficiency
OUT = 3.3V
V
fOSC = 500kHz / VIN = 8V/12V/16V
11) Load transient response
VIN = 12V / VOUT = 3.3V
VIN = 12V / VOUT = 3.3V
fOSC = 500kHz / MODE = L VFM/PWM auto-switching fOSC = 500kHz / MODE = L VFM/PWM auto-switching
VIN = 12V / VOUT = 3.3V
VIN = 12V / VOUT = 3.3V
fOSC = 500kHz / MODE = H Forced PWM
fosc = 500kHz / MODE = H Forced PWM
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R1273L-Y
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12) Output voltage vs. Output current
VOUT = 3.3V
fOSC = 500kHz / VIN=12V
13) Input transient response
VOUT = 3.3V
VOUT = 3.3V
fOSC = 500kHz / MODE = L VFM/PWM auto-switching fOSC = 500kHz / MODE = L VFM/PWM auto-switching
IOUT=0.1A VFM mode
IOUT=0.1A VFM mode
VOUT = 3.3V
VOUT = 3.3V
f
I
OSC = 500kHz / MODE = H Forced PWM
OUT=1A PWM mode
fOSC = 500kHz / MODE = H Forced PWM
IOUT=1A PWM mode
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R1273L-Y
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14) Input voltage vs. Output voltage
OUT = 3.3V
fOSC = 500kHz / MODE = L VFM/PWM auto-switching fOSC = 500kHz / MODE = H Forced PWM
V
VOUT = 3.3V
37
POWER DISSIPATION
QFN0505-32B
Ver. A
The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following measurement conditions are based on JEDEC STD. 51-7.
Measurement Conditions
Item
Measurement Conditions
Mounting on Board (Wind Velocity = 0 m/s)
Environment
Board Material
Board Dimensions
Glass Cloth Epoxy Plastic (Four-Layer Board)
76.2 mm × 114.3 mm × 0.8 mm
Outer Layer (First Layer and Fourth Layer): Less than 95% of 50 mm Square
Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square
Copper Ratio
Through-holes
φ 0.3 mm × 6 pcs
Measurement Result
(Ta = 25°C, Tjmax = 125°C)
Item
Measurement Result
Power Dissipation
2300 mW
Thermal Resistance (θja)
θja = 43°C/W
Thermal Characterization Parameter (ψjt)
ψjt = 9°C/W
θja: Junction-to-Ambient Thermal Resistance
ψjt: Junction-to-Top Thermal Characterization Parameter
3000
2500
2300
2000
1500
1000
500
0
105
0
25
50
75
100
125
Ambient Temperature (°C)
Power Dissipation vs. Ambient Temperature
Measurement Board Pattern
i
PACKAGE DIMENSIONS
QFN0505-32B
Ver. C
∗
QFN0505-32B Package Dimensions (Unit: mm)
*
∗ The tabs for VIN, LX, and AGND pins on the bottom of the package, shown by blue circle, should be connected to the
same potential of each tab.
i
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production without notice for reasons such as improvement. Therefore, before deciding to use the products, please
refer to Ricoh sales representatives for the latest information thereon.
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3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise
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4. The technical information described in this document shows typical characteristics of and example application circuits
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characteristics in the evaluation stage.
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Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since
Halogen Free
April 1, 2012.
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