R5109N431C-TR-FE [RICOH]
Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO8, HALOGEN FREE AND ROHS COMPLIANT, SSOP-8;
| 型号： | R5109N431C-TR-FE |
| 厂家： | 
RICOH ELECTRONICS DEVICES DIVISION |
| 描述： | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO8, HALOGEN FREE AND ROHS COMPLIANT, SSOP-8 光电二极管 |
| 文件： | 总40页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R510xx SERIES
Microprocessor Supervisory Circuit
OUTLINE
NO.EA-210-111103
The R510xx Series are CMOS-based microprocessor supervisory circuit, or high accuracy and ultra low
supply current voltage detector with built-in delay circuit and watchdog timer. When the supply voltage is down
across the threshold, or the watchdog timer does not detect the system clock from the microprocessor, the reset
output is generated.
The voltage detector circuit is used for the system reset, etc. The detector threshold is fixed internally, and the
accuracy is ±1.0%. The released delay time (Power-on Reset Delay) circuit is built-in, and output delay time is
adjustable with an external capacitor, and the accuracy is ±16%∗. When the supply voltage becomes higher
than the released voltage, the reset state will be maintained during the delay time. The output type of the reset
is selectable, Nch open-drain, or CMOS.
The time out period of the watchdog timer can be also set with an external capacitor, and the accuracy is
±33%∗.
There are 5 products by the difference of packages and the function of voltage detector and watchdog timer.
The packages of R5105N and R5106N are SOT-23-6. The packages of R5107G, R5108G and R5109G are
SSOP-8G.
FEATURES
• Supply Current......................................................................Typ. 11μA (R5109G: 11.5μA)
• Operating Voltage Range .....................................................0.9V to 6.0V (R5108G: 1.5V to 6.0V)
< Voltage Detector Part >
• Detector Threshold Range....................................................Stepwise setting with a step of 0.1V in the
range of 1.5V to 5.5V
• Detector Threshold Accuracy................................................±1.0%
• Power-on Reset Delay Time accuracy .................................±16%∗ (−40°C ≤ Topt ≤ 105°C)
• Power-on reset delay time of the voltage detector...............Typ. 370ms with an external capacitor : 0.1μF
< Watchdog Timer Part >
• Built-in a watchdog timer's time out period accuracy ...........±33%∗ (−40°C ≤ Topt ≤ 105°C)
• Timeout period for watchdog timer .......................................Typ. 310ms with an external capacitor : 0.1μF
• Reset timer for watchdog timer.............................................Typ. 34ms with an external capacitor : 0.1μF
• Packages..............................................................................SOT-23-6 (R5105N, R5106N)
SSOP-8G (R5107G, R5108G, R5109G)
∗) Accuracy to center value of (Min.+Max.)/2
APPLICATIONS
• Supervisory circuit for equipment with using microprocessors.
1
R510xx
BLOCK DIAGRAMS
R5105Nxx1A
R5105Nxx1C
3
6
3
6
V
DD
V
DD
C
D
C
D
Vref2
Vref2
Vref1
Vref1
5
1
5
1
GND
SCK
GND
SCK
2
4
2
4
C
TW
C
TW
WATCHDOG
TIMER
CLOCK
DETECTOR
WATCHDOG
TIMER
CLOCK
DETECTOR
RESETB
RESETB
R5106Nxx1A
R5106Nxx1C
3
3
VDD
VDD
SW1
SW2
SW1
SW2
Vref2
Vref1
Vref2
Vref1
5
5
1
GND
SCK
GND
SCK
6
4
6
4
C
T
C
T
WATCHDOG
TIMER
CLOCK
DETECTOR
WATCHDOG
TIMER
CLOCK
DETECTOR
1
RESETB
RESETB
INH
INH
2
2
∗SW1: "L"=ON, SW2: "H"=ON
R5107Gxx1A
R5107Gxx1C
MR
MR
VDD
VDD
C
D
C
D
GND
SCK
GND
SCK
Vref2
Vref2
Vref1
Vref1
CTW
CTW
WATCHDOG
TIMER
CLOCK
WATCHDOG
TIMER
CLOCK
DETECTOR
DETECTOR
RESETB
INH RESETB
INH
2
R510xx
R5108Gxx1A
R5108Gxx1C
SENSE
SENSE
V
DD
V
DD
C
D
C
D
Vref2
Vref1
Vref2
Vref1
GND
SCK
GND
SCK
C
TW
C
TW
WATCHDOG
TIMER
CLOCK
DETECTOR
WATCHDOG
TIMER
CLOCK
DETECTOR
INH
INH
RESETB
RESETB
R5109Gxx1A
R5109Gxx1C
V
DD
VDD
C
D
C
D
Vref2
Vref1
Vref2
Vref1
GND
GND
C
TW
C
TW
WATCHDOG
TIMER
CLOCK
WATCHDOG
TIMER
CLOCK
SCK1
SCK2
SCK1
SCK2
DETECTOR
DETECTOR
CLOCK
DETECTOR
CLOCK
DETECTOR
RESETB
RESETB
INH
INH
3
R510xx
SELECTION GUIDE
The detector threshold, and the output type for the ICs can be selected at the users’ request. The selection
can be made with designating the part number as shown below;
Product Name
R5105Nxx1∗-TR-FE
R5106Nxx1∗-TR-FE
R5107Gxx1∗-TR-FE
R5108Gxx1∗-TR-FE
R5109Gxx1∗-TR-FE
Package
SOT-23-6
SOT-23-6
SSOP-8G
SSOP-8G
SSOP-8G
Quantity per Reel
3,000 pcs
Pb Free
Yes
Halogen Free
Yes
Yes
Yes
Yes
Yes
3,000 pcs
Yes
3,000 pcs
Yes
3,000 pcs
Yes
3,000 pcs
Yes
xx: The detector threshold can be designated in the range from 1.5V(15) to 5.5V(55) in 0.1V steps.
∗ : Designation of Output Type
(A) Nch Open Drain
(C) CMOS
SERIES SELECTION
R5105N
R5106N
R5107G
R5108G
R5109G
Package
With INH pin (Inhibit)
2 clock input
SOT-23-6
SSOP-8G
No
Yes
No
Yes
No
With MR pin (Manual Reset)
With SENSE pin
No
Yes
No
No
Yes
CD pin and
CTW pin are
combined uses.
Operating
Voltage Range
1.5V to 6.0V
Supply Current
Remarks
11.5μA
4
R510xx
PIN CONFIGURATIONS
• SOT-23-6
• SSOP-8G
8 7 6
6
5
4
5
(mark side)
1 2 3 4
1
2
3
PIN DESCRIPTIONS
• R5105N (SOT-23-6)
Pin No.
Symbol
Description
Clock Input Pin from Microprocessor
1
SCK
External Capacitor Pin for setting Reset and Watchdog Timer
Timeout Period
2
3
CTW
VDD
Power supply Pin
Output Pin for Reset signal of Watchdog timer and Voltage Detector.
(Output "L" at detecting Detector Threshold and Watchdog Timer
Reset.)
4
RESETB
5
6
GND
Ground Pin
CD
External Capacitor Pin for Setting delay time of Voltage Detector
• R5106N (SOT-23-6)
Pin No.
Symbol
Description
Clock Input Pin from Microprocessor
Inhibit Pin ("L": Inhibit the watchdog timer)
Power supply Pin
1
2
3
SCK
INH
VDD
Output Pin for Reset signal of Watchdog timer and Voltage Detector.
(Output "L" at detecting Detector Threshold and Watchdog Timer
Reset.)
4
RESETB
5
6
GND
Ground Pin
External Capacitor Pin for Setting Reset and Watchdog Timeout
Periods and delay time of Voltage Detector
CT
5
R510xx
• R5107G (SSOP-8G)
Pin No.
Symbol
Description
Output Pin for Reset signal of Watchdog timer and Voltage Detector.
(Output "L" at detecting Detector Threshold and Watchdog Timer Reset.)
1
RESETB
2
3
4
5
6
7
8
MR
CD
Manual Reset Pin (Active"L")
External Capacitor Pin for Setting Delay Time of Voltage Detector
Ground Pin
GND
SCK
INH
CTW
VDD
Clock Input Pin from Microprocessor
Inhibit Pin ("L": Inhibit the watchdog timer)
External Capacitor Pin for Setting Reset and Watchdog Timeout Periods
Power supply Pin
• R5108G (SSOP-8G)
Pin No.
Symbol
Description
Output Pin for Reset signal of Watchdog timer and Voltage Detector.
(Output "L" at detecting Detector Threshold and Watchdog Timer Reset.)
1
RESETB
2
3
4
5
6
7
8
SENSE
CD
Voltage Detector Voltage SENSE Pin (Active"L")
External Capacitor Pin for Setting Delay Time of Voltage Detector
Ground Pin
GND
SCK
INH
Clock Input Pin from Microprocessor
Inhibit Pin ("L": Inhibit the watchdog timer)
External Capacitor Pin for Setting Reset and Watchdog Timeout Periods
Power supply Pin
CTW
VDD
• R5109G (SSOP-8G)
Pin No.
Symbol
Description
Output Pin for Reset signal of Watchdog timer and Voltage Detector.
(Output "L" at detecting Detector Threshold and Watchdog Timer Reset.)
1
RESETB
2
3
4
5
6
7
8
INH
CD
Inhibit Pin ("L": Inhibit the watchdog timer)
External Capacitor Pin for Setting Delay Time of Voltage Detector
Ground Pin
GND
SCK1
SCK2
CTW
Clock Input Pin 1 from Microprocessor
Clock Input Pin 2 from Microprocessor
External Capacitor Pin for Setting Reset and Watchdog Timeout Periods
Power supply Pin
VDD
6
R510xx
ABSOLUTE MAXIMUM RATINGS
Topt=25°C
Symbol
Item
Rating
−0.3 to 7.0
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
−0.3 to 7.0
−0.3 to 7.0
−0.3 to 7.0
−0.3 to 7.0
−0.3 to 7.0
20
Unit
V
VDD
Supply Voltage
Output Voltage
VCD
Voltage of CD Pin
V
VCTW
VCT
Voltage of CTW Pin
Voltage of CT Pin
V
V
VRESETB
VSCK
Voltage of RESETB Pin
Voltage of SCK Pin
Voltage of INH Pin
Voltage of MR Pin
Voltage of SENSE Pin
Current of RESETB Pin
V
V
VINH
V
Input Voltage
VMR
V
VSENSE
IRESETB
V
Output Current
mA
mW
mW
°C
°C
Power Dissipation (SOT-23-6)∗
420
PD
Power Dissipation (SSOP-8G)∗
Operating Temperature Range
Storage Temperature Range
380
Topt
Tstg
−40 to 105
−55 to 125
∗ ) For Power Dissipation, please refer to PACKAGE INFORMATION.
ABSOLUTE MAXIMUM RATINGS
Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the
permanent damages and may degrade the life time and safety for both device and system using the device
in the field.
The functional operation at or over these absolute maximum ratings is not assured.
7
R510xx
ELECTRICAL CHARACTERISTICS
VDD=6.0V, CTW=0.1μF, CD=0.1μF, CT=0.1μF, In case of Nch Open Drain Output type, the output pin is pulled up
with a resistance of 100kΩ (R510xxxx1A), unless otherwise noted.
The specification in
• R5105Nxx1A/C
Symbol
is checked and guaranteed by design engineering at −40°C ≤ Topt ≤ 105°C.
Topt=25°C
Item
Conditions
Min.
Typ.
Max.
Unit
VDD
ISS
Operating Voltage
Supply Current
0.9
6.0
V
VDD= -VDET+0.5V,
Clock pulse input
11
15
μA
VD Part
Symbol
Item
Conditions
Min.
Typ.
Max.
Unit
Topt=25°C
×0.990
×1.010
-VDET Detector Threshold
V
−40°C ≤ Topt ≤ 105°C
×0.972
×1.015
-VDET
×0.03
-VDET
×0.05
-VDET
×0.07
V
Detector Threshold Hysteresis
Δ-VDET/ Detector Threshold
VHYS
−40°C ≤ Topt ≤ 105°C
CD=0.1μF ∗1
±100
370
0.8
ppm/°C
ms
Temperature Coefficient
ΔTopt
tPLH
Output Delay Time
340
467
VDD=1.2V
Nch
0.38
mA
VDS=0.1V
Output Current
(RESETB Output pin)
IRESETB
VDD=6.0V
Pch ∗2
0.65
0.9
mA
VDS=0.5V
WDT Part
Symbol
Item
Conditions
Min.
Typ.
Max.
Unit
CTW=0.1μF ∗1
tWD
tWR
Watchdog Timeout period
Reset Hold Time of WDT
230
310
450
ms
CTW=0.1μF ∗1
29
VDD×0.8
0
34
48
6.0
ms
V
VSCKH SCK Input "H"
VSCKL
tSCKW
SCK Input "L"
V
VDD×0.2
VSCKL=VDD×0.2
VSCKH=VDD×0.8
SCK Input Pulse Width
500
ns
All of unit are tested and specified under load conditions such that Topt=25°C except for Detector Threshold
Temperature Coefficient.
∗1) The specification does not contain the temperature characteristics of the external capacitor.
∗2) In case of CMOS type (R5105Nxx1C)
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the
recommended operating conditions, even if when they are used over such conditions by momentary
electronic noise or surge. And the semiconductor devices may receive serious damage when they continue
to operate over the recommended operating conditions.
8
R510xx
• R5106Nxx1A/C
Topt=25°C
Symbol
Item
Conditions
Min.
Typ.
11
Max.
Unit
VDD
ISS
Operating Voltage
0.9
6.0
V
VDD= -VDET+0.5V,
Clock pulse input
Supply Current
15
μA
VD Part
Symbol
Item
Conditions
Topt=25°C
Min.
Typ.
Max.
Unit
×0.990
×0.972
×1.010
×1.015
-VDET Detector Threshold
V
−40°C ≤ Topt ≤ 105°C
-VDET
×0.03
-VDET
×0.05
-VDET
×0.07
V
Detector Threshold Hysteresis
Δ-VDET/ Detector Threshold
VHYS
−40°C ≤ Topt ≤ 105°C
CT=0.1μF ∗1
±100
ppm/°C
Temperature Coefficient
ΔTopt
tPLH
Output Delay Time
340
0.38
0.65
370
0.8
0.9
467
ms
mA
mA
Nch
VDD=1.2V, VDS=0.1V
VDD=6.0V, VDS=0.5V
Output Current
(RESETB Output pin)
IRESETB
Pch ∗2
WDT Part
Symbol
Item
Conditions
Min.
Typ.
Max.
Unit
CT=0.1μF ∗1
CT=0.1μF ∗1
tWD
tWR
Watchdog Timeout period
Reset Hold Time of WDT
230
310
450
ms
29
34
48
6.0
ms
V
VSCKH SCK Input "H"
VDD×0.8
VSCKL
VINHH
VINHL
RINH
SCK Input "L"
0
1.0
0
V
VDD×0.2
6.0
INH Input "H"
V
INH Input "L"
0.35
164
V
INH pull-up Resistance
60
110
kΩ
VSCKL=VDD×0.2
VSCKH=VDD×0.8
tSCKW
SCK Input Pulse Width
500
ns
All of unit are tested and specified under load conditions such that Topt=25°C except for Detector Threshold
Temperature Coefficient.
∗1) The specification does not contain the temperature characteristics of the external capacitor.
∗2) In case of CMOS type (R5106Nxx1C)
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the
recommended operating conditions, even if when they are used over such conditions by momentary
electronic noise or surge. And the semiconductor devices may receive serious damage when they continue
to operate over the recommended operating conditions.
9
R510xx
• R5107Gxx1A/C
Symbol
Topt=25°C
Item
Conditions
Min.
Typ.
Max.
Unit
VDD
ISS
Operating Voltage
0.9
6.0
V
VDD= -VDET+0.5V,
Clock pulse input
Supply Current
11
15
μA
VD Part
Symbol
Item
Conditions
Topt=25°C
Min.
Typ.
Max.
Unit
×0.990
×0.972
×1.010
×1.015
-VDET Detector Threshold
V
−40°C ≤ Topt ≤ 105°C
-VDET
×0.03
-VDET
×0.05
-VDET
×0.07
V
Detector Threshold Hysteresis
VHYS
Δ-VDET/
ΔTopt
Detector Threshold
−40°C ≤ Topt ≤ 105°C
CD=0.1μF ∗1
±100
ppm/°C
Temperature Coefficient
tPLH
Output Delay Time
340
0.38
0.65
1.0
0
370
0.8
0.9
467
ms
mA
mA
V
Nch
VDD=1.2V, VDS=0.1V
VDD=6.0V, VDS=0.5V
Output Current
(RESETB Output pin)
IRESETB
Pch ∗2
MR Input "H" ∗3
VMRH
VMRL
tMRW
RMR
6.0
MR Input "L"
MR Input Pulse Width ∗4
0.35
V
3
μs
kΩ
MR Pull-up Resistance
60
110
164
WDT Part
Symbol
Item
Conditions
Min.
230
29
Typ.
310
34
Max.
450
Unit
ms
ms
V
CTW=0.1μF ∗1
CTW=0.1μF ∗1
tWD
tWR
Watchdog Timeout period
Reset Hold Time of WDT
48
VSCKH SCK Input "H"
6.0
VDD×0.8
0
VSCKL
VINHH
VINHL
RINH
SCK Input "L"
V
VDD×0.2
6.0
INH Input "H"
1.0
V
INH Input "L"
0
0.35
152
V
INH pull-up Resistance
64
110
kΩ
VSCKL=VDD×0.2
VSCKH=VDD×0.8
tSCKW
SCK Input Pulse Width
500
ns
All of unit are tested and specified under load conditions such that Topt=25°C except for Detector Threshold
Temperature Coefficient and MR Input Pulse Width.
∗1) The specification does not contain the temperature characteristics of the external capacitor.
∗2) In case of CMOS type (R5107Gxx1C)
∗3) In case of Nch open drain type (R5107Gxx1A)
∗4) MR input pulse width specification guarantee the minimum input pulse width of MR pin for output "L" from RESETB pin.
If the "L" pulse width of MR is short, tPLH may be short. Refer to the timing diagram for details.
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the
recommended operating conditions, even if when they are used over such conditions by momentary
electronic noise or surge. And the semiconductor devices may receive serious damage when they continue
to operate over the recommended operating conditions.
10
R510xx
• R5108Gxx1A/C
Symbol
Topt=25°C
Item
Conditions
Min.
Typ.
Max.
Unit
VDD
ISS
Operating Voltage
1.5
6.0
V
VDD= -VDET+0.5V,
Clock pulse input
Supply Current
11
15
μA
VD Part
Symbol
Item
Conditions
Topt=25°C
Min.
Typ.
Max.
Unit
VDD=5V,
SENSE pin
Threshold
×0.990
×1.010
-VDET Detector Threshold
V
−40°C≤Topt≤105°C ×0.972
×1.015
Detector Threshold
-VDET
×0.05
-VDET
×0.03
-VDET
×0.07
V
VHYS
Hysteresis
Δ-VDET/ Detector Threshold
−40°C ≤ Topt ≤ 105°C
CD=0.1μF ∗1
±100
370
0.8
ppm/°C
ms
Temperature Coefficient
Output Delay Time
ΔTopt
tPLH
340
467
VDD=1.2V
VDS=0.1V
Nch
0.38
mA
Output Current
(RESETB Output pin)
IRESETB
VDD=6.0V
VDS=0.5V
Pch ∗2
0.65
0.9
0.6
mA
V
VDDL
Minimum Operating Voltage
0.9
RESETB ≤ 0.1V, pull-up=100kΩ
WDT Part
Symbol
Item
Conditions
CTW=0.1μF ∗1
CTW=0.1μF ∗1
Min.
230
29
Typ.
310
34
Max.
450
Unit
ms
ms
V
tWD
tWR
Watchdog Timeout period
Reset Hold Time of WDT
48
VSCKH SCK Input "H"
6.0
VDD×0.8
0
VSCKL
VINHH
VINHL
RINH
SCK Input "L"
V
VDD×0.2
6.0
INH Input "H"
1.0
V
INH Input "L"
0
0.35
164
V
INH pull-up Resistance
60
110
kΩ
VSCKL=VDD×0.2
VSCKH=VDD×0.8
tSCKW
SCK Input Pulse Width
500
ns
All of unit are tested and specified under load conditions such that Topt=25°C except for Detector Threshold
Temperature Coefficient.
∗1) The specification does not contain the temperature characteristics of the external capacitor.
∗2) In case of CMOS type (R5108Gxx1C)
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within
the recommended operating conditions. The semiconductor devices cannot operate normally over the
recommended operating conditions, even if when they are used over such conditions by momentary
electronic noise or surge. And the semiconductor devices may receive serious damage when they
continue to operate over the recommended operating conditions.
11
R510xx
• R5109Gxx1A/C
Symbol
Topt=25°C
Item
Conditions
Min.
Typ.
Max.
Unit
VDD
ISS
Operating Voltage
Supply Current
0.9
6.0
V
VDD= -VDET+0.5V,
Clock pulse input
11.5
15.5
μA
VD Part
Symbol
Item
Conditions
Min.
Typ.
Max.
Unit
Topt=25°C
×0.990
×1.010
-VDET Detector Threshold
V
−40°C ≤ Topt ≤ 105°C
×0.972
×1.015
-VDET
×0.03
-VDET
×0.05
-VDET
×0.07
V
Detector Threshold Hysteresis
Δ-VDET/ Detector Threshold
VHYS
−40°C ≤ Topt ≤ 105°C
CD=0.1μF ∗1
±100
370
0.8
ppm/°C
ms
Temperature Coefficient
ΔTopt
tPLH
Output Delay Time
340
467
VDD=1.2V
Nch
0.38
mA
VDS=0.1V
Output Current
(RESETB Output pin)
IRESETB
VDD=6.0V
Pch ∗2
0.65
0.9
mA
VDS=0.5V
WDT Part
Symbol
Item
Conditions
CTW=0.1μF ∗1
CTW=0.1μF ∗1
Min.
230
29
Typ.
310
34
Max.
450
48
Unit
ms
ms
V
tWD
tWR
Watchdog Timeout period
Reset Hold Time of WDT
VSCKH SCK Input "H"
SCK1, SCK2
6.0
VDD×0.8
VSCKL
VINHH
VINHL
RINH
SCK Input "L"
SCK1, SCK2
0
1.0
0
V
VDD×0.2
6.0
INH Input "H"
V
INH Input "L"
0.35
164
V
INH pull-up Resistance
60
110
kΩ
VSCKL=VDD×0.2
VSCKH=VDD×0.8
tSCKW
SCK Input Pulse Width
500
ns
All of unit are tested and specified under load conditions such that Topt=25°C except for Detector Threshold
Temperature Coefficient.
∗1) The specification does not contain the temperature characteristics of the external capacitor.
∗2) In case of CMOS type (R5109Gxx1C)
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the
recommended operating conditions, even if when they are used over such conditions by momentary
electronic noise or surge. And the semiconductor devices may receive serious damage when they continue
to operate over the recommended operating conditions.
12
R510xx
TIMING CHART
• R5105N
+VDET
VDD
-VDET
t
PHL
t
PHL
VCD
+VTCD
-VTCD
tWD
tWDI
Vref2H
VCTW
Vref2L
t
PLH
t
PLH
VSCK
tWR
VRESETB
(1)
(2)
(3)
(4) (1)
∗) VTCD : Threshold voltage of CD pin when a power-on reset pulse inverting.
∗) Vref2H : CTW pin voltage at the end of WDT timeout period.
∗) Vref2L : CTW pin voltage at the begin of WDT timeout period.
OPERATION
(1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released
delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) When the SCK pulse is input, the watchdog timer (WDT) is cleared, and CTW pin mode changes from the
discharge mode to the charge mode. When the CTW pin voltage becomes higher than VrefH, the mode will
change into the discharge mode, and next watchdog time count starts.
13
R510xx
(3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of CTW pin,
RESETB="L".
(4) When the VDD pin becomes lower than the detector threshold voltage(-VDET), RESETB outputs "L".
• Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s) = 3.1×106×C (F)
tWR (s) = tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s) = tWD/10
• Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation
describes the relation between the capacitance value and the released delay time (tPLH).
tPLH (s) =3.7×106× C (F)
When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin
starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay
time will be shorter than tPLH which is expected.
Power on Reset Operation against the input glitch (tPLH1<tPLH)
+VDET
-VDET
VDD
0V
Complete
Discharge
+VTCD
-VTCD
VCD
0V
Incomplete
Discharge
VRESETB
0V
t
PLH1
t
PLH
14
R510xx
• Minimum Operating Voltage
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB
pin being 0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100kΩ in the case of the Nch open-drain
output type.)
• RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
• Clock Pulse Input
Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.
15
R510xx
• R5106N
+VDET
DD
V
-VDET
VINH
t
PLH
tWDI
tWD
V
V
ref2H
ref2L
VCT
t
PHL
VSCK
t
PLH
tWR
VRESETB
(1) (2)
(3) (4)
(5)
(6)
(7)
∗) Vref2H : CT pin voltage at the end of WDT timeout period.
∗) Vref2L : CT pin voltage at the begin of WDT timeout period.
OPERATION
(1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released
delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) When the SCK pulse is input, the watchdog timer (WDT) is cleared, and CT pin mode changes from the
discharge mode to the charge mode. When the CT pin voltage becomes higher than Vref2H, the mode will
change into the discharge mode, and next watchdog time count starts.
(3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of CT pin,
RESETB="L".
(4) When the VDD pin becomes lower than the detector threshold voltage(-VDET), RESETB outputs "L".
(5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
(6) During the "L" period of INH pin, the voltage detector monitors the supply voltage.
16
R510xx
(7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock, or
charge cycle to the CT pin starts, the capacitor connected to the CT pin is charged with the current of setting
Reset time of WDT.
• Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CT pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s) = 3.1×106×C (F)
tWR (s) = tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s) = tWD/10
• Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CT pin. The next equation
describes the relation between the capacitance value and the released delay time (tPLH).
tPLH (s) =3.7×106× C (F)
The capacitor connected to CT pin determines tWD, tWR, and tPLH.
When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CT pin
starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay
time will be shorter than tPLH which is expected.
Power on Reset Operation against the input glitch (tPLH1 < tPLH)
+VDET
-VDET
VDD
0V
Complete
Discharge
+VTCT
-VTCT
VCT
0V
Incomplete
Discharge
VRESETB
0V
t
PHL
t
PHL
t
PLH
t
PLH1
17
R510xx
• Minimum Operating Voltage
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB
pin being 0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100kΩ in the case of the Nch open-drain
output type.)
• Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be
dominant by the voltage detector's operation. Therefore, if the supply voltage is set at more than the detector
threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor
(TYP.110kΩ) internally.
• RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
• Clock Pulse Input
Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.
18
R510xx
• R5107G
+VDET
VDD
-VDET
V
INH
V
MR
t
PHL
t
PHL
t
PLH
t
PLH
+VTCD
-VTCD
VCD
tWDI
tWD
tWD
V
ref2H
VCTW
V
ref2L
tWR
tWR
VSCK
t
MR
t
PLH
VRESETB
(1) (2)
(4)
(3)(5)
(6)
(7)
(8)
(9)
∗) VTCD : Threshold voltage of CD pin when a power-on reset pulse inverting.
∗) Vref2H : CTW pin voltage at the end of WDT timeout period.
∗) Vref2L : CTW pin voltage at the begin of WDT timeout period.
19
R510xx
OPERATION
(1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released
delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) When the SCK pulse is input, the watchdog timer is cleared, and CTW pin mode changes from the discharge
mode to the charge mode. When the CTW pin voltage becomes higher than Vref2H, the mode will change into
the discharge mode, and next watchdog time count starts.
(3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of CTW pin,
RESETB="L".
(4) When the VDD pin becomes lower than the detector threshold voltage (-VDET), RESETB outputs "L" after the
tPHL.
(5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
(6) During the "L" period of INH pin, the voltage detector monitors the supply voltage.
(7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock, or
charge cycle to the CTW pin starts, the capacitor connected to the CTW pin is charged with the current of
setting Reset time of WDT.
(8) If "L" signal is input to the MR pin, the RESETB outputs "L" after the tMR, regardless the SCK clock state and
VDD voltage.
(9) When the signal to the MR pin is set from "L" to "H", the RESETB outputs "H" after the tPLH, the watchdog
starts supervising the system clock.
• Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s) = 3.1 × 106 × C (F)
tWR (s) = tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s) = tWD/10
20
R510xx
• Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation
describes the relation between the capacitance value and the released delay time (tPLH).
tPLH (s) =3.7 × 106 × C (F)
The capacitor connected to CD pin determines tWD, tWR, and tPLH.
When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin
starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay
time will be shorter than tPLH which is expected.
Power on Reset Operation against the input glitch (tPLH1 < tPLH)
+VDET
-VDET
VDD
0V
Complete
Discharge
+VTCD
-VTCD
VCD
0V
Incomplete
Discharge
VRESETB
0V
t
PLH1
t
PLH
• Minimum Operating Voltage
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB
pin being 0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100kΩ in the case of the Nch open-drain
output type.)
21
R510xx
• Manual Reset (MR) Function
By setting MR pin as "L", the output of RESETB can be forced to set "L". After pull-down the MR pin to "L", the
delay time (tMR) to the output "L" from RESETB is 1μs as maximum. MR pin is pulled-up via the built-in resistor.
(Typ. 110kΩ ). If MR pin voltage > VDD voltage, a current flows into MR pin. However, the current value is limit by
the pull-up resistor, therefore there is not bad impact on the operation. When the "L" signal is input to MR pin,
the discharge of CD pin capacitor (CD) starts. If the term of "L" for MR pin is short, CD will not be discharged
enough. As a result, the delay time after setting "H" for MR pin will be shorter than expected. Because of this,
confirm the operation under the same conditions as users' applications. For example, in case of CD is set at
0.1μF, and the condition to maintain the delay time value after MR pin's returning to "H", is described as the
minimum "L" term of MR pin, or 150μs. When MR input pulse (tMRW) is less than 3.0μs, output delay time (tPLH)
might not exist.
Power on Reset Operation with MR pin input (tPLH1 < tPLH, tMRW1 < tMRW)
VMR
0V
Incomplete
Discharge
Complete
Discharge
+VTCD
-VTCD
VCD
0V
t
MR
t
MR
t
MR
VRESETB
0V
t
MRW1
t
MRW1
t
PLH1
t
MRW
t
PLH
• Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be
dominant by the voltage detector's operation. Therefore, if the supply voltage is set at more than the detector
threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor (Typ.110kΩ)
internally.
• RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
• Clock Pulse Input
Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.
22
R510xx
• R5108G
VDD
V
INH
+VDET
VSENSE
-VDET
t
PLH
t
PLH
+VTCD
- VTCD
VCD
tWDI
tWD
V
ref2H
VCTW
V
ref2L
t
PHL
tWR
VSCK
t
PLH
V
RESETB
(1)
(2)
(4)
(3) (5)
(6)
∗) VTCD : Threshold voltage of CD pin when a power-on reset pulse inverting.
∗) Vref2H : CTW pin voltage at the end of WDT timeout period.
∗) Vref2L : CTW pin voltage at the begin of WDT timeout period.
23
R510xx
OPERATION
(1) When the power supply, the SENSE pin voltage becomes more than the released voltage (+VDET), after the
released delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) When the SCK pulse is input, the watchdog timer is cleared, and CTW pin mode changes from the discharge
mode to the charge mode. When the CTW pin voltage becomes higher than Vref2H, the mode will change into
the discharge mode, and next watchdog time count starts.
(3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of CTW pin,
RESETB="L".
(4) When the SENSE pin becomes lower than the detector threshold voltage (-VDET), RESETB outputs "L" after
the tPHL.
(5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
(6) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock.
• Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s) = 3.1 × 106 × C (F)
tWR (s) = tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s) = tWD/10
• Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation
describes the relation between the capacitance value and the released delay time (tPLH).
tPLH (s) =3.7 × 106 × C (F)
The capacitor connected to CD pin determines tWD, tWR, and tPLH.
When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin
starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay
time will be shorter than tPLH which is expected.
24
R510xx
Power on Reset Operation against the input glitch (tPLH1 < tPLH)
+VDET
-VDET
VDD
0V
Complete
Discharge
+VTCD
-VTCD
VCD
0V
Incomplete
Discharge
VRESETB
0V
t
PLH1
t
PLH
• Minimum Operating Voltage
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB
pin being 0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100kΩ in the case of the Nch open-drain
output type.)
• Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be
dominant by the voltage detector's operation. Therefore, if the SENSE pin voltage is set at more than the
detector threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor
(Typ.110kΩ) internally.
• SENSE Function
Built-in Voltage detector monitors the input voltage for SENSE pin. To obtain the normal detector threshold,
VDD ≥ 1.5V must be secured.
• RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
• Clock Pulse Input
Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.
25
R510xx
• R5109G
DD +VDET
V
-VDET
VINH
t
PHL
t
PHL
t
PHL
+VTCD
V
CD -VTCD
tWDI
tWD
Vref2H
VCTW
Vref2L
VSCK1
VSCK2
t
PLH
tWR
t
PLH
t
PLH
VRESETB
(1)
(2) (14) (2) (3)
(4) (1) (2)(5)
(6)
(7)(8)(9) (9) (10) (11)(12)(13)
(4)
∗) VTCD : Threshold voltage of CD pin when a power-on reset pulse inverting.
∗) Vref2H : CTW pin voltage at the end of WDT timeout period.
∗) Vref2L : CTW pin voltage at the begin of WDT timeout period.
26
R510xx
OPERATION
(1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released
delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) After the SCK1 pulse is input, when the SCK2 pulse is input, the watchdog timer is cleared, and CTW pin
mode changes from the discharge mode to the charge mode. When the CTW pin voltage becomes higher
than Vref2H, the mode will change into the discharge mode, and next watchdog time count starts.
(3) After the SCK1 pulse is input, unless the SCK2 pulse is input, WDT will not be cleared, and during the
charging period of CTW pin, RESETB="L".
(4) When the VDD pin becomes lower than the detector threshold voltage (-VDET), RESETB outputs "L" after the
tPHL.
(5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
(6) During the "L" period of INH pin, the voltage detector monitors the supply voltage.
(7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock, or
charge cycle to the CTW pin starts, the capacitor connected to the CTW pin is charged with the current of
setting Reset time of WDT.
(8) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared.
(9) Without the input of SCK1 pulse input, even if the SCK2 pulse is input, the WDT will not be cleared.
(10) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared.
(11) If SCK1 pulse and SCK2 pulse are input at the same time, the WDT will not be cleared.
(12) After from the discharge of the external capacitor even if the clock pulse is input during the time period "tWDI",
the clock pulse is ignored.
(13) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared.
(14) The WDT supervises SCK1 pulse and SCK2 pulse by turns, therefore, for example, if only SCK1 pulse is
input twice or more without SCK2 pulse, the second or later consecutive SCK1 pulse will be ignored. After
the SCK1 pulse is input, and when the SCK2 pulse is input, the WDT will be cleared. In the same way, if
only SCK2 pulse is input twice or more without SCK1 pulse, the second or later consecutive SCK2 pulse
will be ignored.
Too close timing of SCK1 pulse input and SCK2 pulse input means the rising edge interval time range from
0ns to 50ns. (Guaranteed by design, not mass production tested.)
Even if the SCK1 and SCK2 are input at almost the same time as above, the WDT will still try to supervise
these two clock by turns.
Therefore, after the SCK1 pulse is input, if SCK1 pulse and SCK2 pulse are input at almost the same time,
the WDT will be cleared. (as the status (8))
Likewise, after the SCK1 pulse and SCK2 pulse are input at almost the same time, when the SCK2 pulse is
input, the WDT will be cleared. (as the status (10))
27
R510xx
If the almost same timing input of SCK1 and SCK2 continues twice, the WDT will be cleared. (as the status
(13))
0~50ns
SCK1
SCK2
t
Example timing of too close input pulses
(This pattern will be recognized the clock timing is same by the WDT)
• Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s) = 3.1 × 106 × C (F)
tWR (s) = tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s) = tWD/10
• Released Delay Time (Power-on Reset delay time)
The released delay time can be set with an external capacitor connected to the CD pin. The next equation
describes the relation between the capacitance value and the released delay time (tPLH).
tPLH (s) =3.7 × 106 × C (F)
The capacitor connected to CD pin determines tWD, tWR, and tPLH.
When the VDD voltage becomes equal or less than (-VDET), discharge of the capacitor connected to the CD pin
starts. Therefore, if the discharge is not enough and VDD voltage returns to (+VDET) or more, thereafter the delay
time will be shorter than tPLH which is expected.
28
R510xx
Power on Reset Operation against the input glitch (tPLH1 < tPLH)
+VDET
-VDET
VDD
0V
Complete
Discharge
+VTCD
-VTCD
VCD
0V
Incomplete
Discharge
VRESETB
0V
t
PLH1
t
PLH
• Minimum Operating Voltage
We specified the minimum operating voltage as the minimum input voltage in which the condition of RESETB
pin being 0.1V or lower than 0.1V. (Herein, pull-up resistance is set as 100kΩ in the case of the Nch open-drain
output type.)
• Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be
dominant by the voltage detector's operation. Therefore, if the supply voltage is set at more than the detector
threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor (Typ.110kΩ)
internally.
• RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
• Clock Pulse Input
Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.
After the SCK1 clock pulse is input, when the SCK2 pulse is input, the watchdog timer will be cleared. If the
system requires only one clock supervise, SCK1 pin and SCK2 pin must connect each other. In this case, the
watchdog timer is cleared with every other clock pulse. Depending on the timing of these two clock pulses,
SCK1 pulse and SCK2 pulse are recognized at almost the same time by the watchdog timer, during the
watchdog timeout period, after the SCK1 clock pulse, two or more SCK2 clock pulses are desirable to put into.
29
R510xx
TYPICAL APPLICATIONS
• R5105N
Power Supply
Microprocessor
Power Supply
Microprocessor
V
DD
V
DD
R
3
6
RESETB
R5105Nxx1A
4
1
3
6
RESETB
R5105Nxx1C
4
1
V
DD
V
DD
RESET
I/O
RESET
I/O
Series
Series
SCK
SCK
C
D
C
D
CTW
2
CTW
2
GND
5
GND
5
CD
CD
C
TW
C
TW
• R5106N
Power Supply
Microprocessor
Power Supply
Microprocessor
V
DD
V
DD
R
3
2
RESETB
4
1
3
2
RESETB
R5106Nxx1C
4
1
V
DD
V
DD
RESET
I/O
RESET
I/O
R5106Nxx1A
Series
Series
SCK
SCK
SW
SW
INH
INH
CT
6
CT
6
GND
5
GND
5
CT
CT
• R5107G
Power Supply
Microprocessor
Power Supply
Microprocessor
V
DD
VDD
R
8
6
2
3
RESETB
R5107Gxx1A
1
5
8
6
2
3
RESETB 1
V
DD
VDD
INH
MR
CD
RESET
I/O
RESET
I/O
INH
MR
R5107Gxx1C
Series
5
7
Series
SCK
SCK
CTW
SW SW
SW SW
C
D
CTW
7
GND
4
GND
4
C
TW
CTW
C
D
CD
30
R510xx
• R5108G
Power Supply
Microprocessor
Power Supply
Microprocessor
V
DD
V
DD
R
8
2
6
3
RESETB
1
5
8
2
6
3
RESETB
1
5
V
DD
V
DD
RESET
I/O
RESET
I/O
SENSE
INH
SENSE
INH
R5108Gxx1A
R5108Gxx1C
SCK
C
SCK
Series
Series
SW
SW
C
D
C
D
TW
7
CTW
7
GND
4
GND
4
C
TW
C
TW
CD
CD
• R5109G
Power Supply
Microprocessor 1
Power Supply
Microprocessor 1
V
DD
V
DD
R
8
2
RESETB
SCK1
1
5
V
DD
RESET
I/O
8
2
RESETB
SCK1
1
5
V
DD
RESET
I/O
INH
INH
R5109Gxx1A
Series
R5109Gxx1C
Series
Microprocessor 2
Microprocessor 2
SCK2
6
7
SCK2
6
7
SW
V
DD
SW
C
D
V
DD
3
CTW
GND
4
C
D
3
CTW
GND
4
RESET
I/O
RESET
I/O
CD
C
TW
CD
C
TW
31
R510xx
TEST CIRCUITS
• R5105N
R (R5105Nxx1A)
A
3
6
RESETB
R5105Nxx1A/C
4
1
V
DD
Clock Input
Series
SCK
C
D
CTW
2
GND
5
CD
CTW
Supply Current Test Circuit
• R5106N
R (R5106Nxx1A)
A
3
2
RESETB
R5106Nxx1A/C
4
1
V
DD
Clock Input
Series
SCK
SW
INH
CT
6
GND
5
CT
• R5107G
R (R5107Gxx1A)
Clock Input
A
8
6
2
3
RESETB
1
5
V
DD
INH
MR
R5107Gxx1A/C
Series
SCK
C
D
CTW
7
GND
4
CD
CTW
32
R510xx
• R5108G
R (R5108Gxx1A)
Clock Input
A
8
2
6
3
RESETB
1
5
V
DD
SENSE
R5108Gxx1A/C
Series
SCK
INH
C
D
CTW
7
GND
4
CD
C
TW
• R5109G
R(R5109Gxx1A)
A
8
2
RESETB
SCK1
1
V
DD
Clock Input
Clock Input
5
6
7
R5109Gxx1A/C
Series
INH
SCK2
C
D
CTW
3
GND
4
C
TW
C
D
33
R510xx
TYPICAL CHARACTERISTICS
1) Supply Current vs. Input Voltage
R510xx151x
R510xx301x
20
20
18
16
14
12
10
8
105°C
105°C
18
25°C
25°C
16
-40°C
-40°C
14
12
10
8
6
6
4
4
2
2
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage VDD (V)
Input Voltage VDD (V)
2) Detector Threshold vs. Temperature
R510xx151x
R510xx271x
1.53
2.74
2.73
2.72
2.71
2.70
2.69
2.68
2.67
2.66
1.52
1.51
1.50
1.49
1.48
1.47
-40 -25
0
25
50
75
105
-40 -25
0
25
50
75
105
Temperature Topt (°C)
Temperature Topt (°C)
R510xx421x
4.28
4.26
4.24
4.22
4.20
4.18
4.16
4.14
4.12
-40 -25
0
25
50
75
105
Temperature Topt (°C)
34
R510xx
3) Detector Threshold Hysteresis vs. Temperature
R510xx151x
R510xx271x
7
7
6
5
4
3
6
5
4
3
-40 -25
0
25
50
75
105
-40 -25
0
25
50
75
105
Temperature Topt (°C)
Temperature Topt (°C)
R510xx421x
7
6
5
4
3
-40 -25
0
25
50
75
105
Temperature Topt (°C)
4) Nch Driver Output Current vs. VDS
R510xx
20
18
16
14
12
10
8
VDD=6.0V
VDD=5.0V
VDD=4.0V
VDD=3.0V
VDD=2.0V
VDD=1.5V
VDD=1.0V
6
4
2
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VDS (V)
35
R510xx
5) Nch Driver Output Current vs. Input Voltage
R510xx
R510xx
VDS=0.3V
VDS=0.5V
20
18
16
14
12
10
8
20
18
16
14
12
10
8
Topt=-40°C
Topt=-40°C
Topt=25°C
Topt=105°C
Topt=25°C
Topt=105°C
6
6
4
4
2
2
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage VDD (V)
Input Voltage VDD (V)
6) Pch Driver Output Current vs. Input Voltage
R510xx
R510xx
VDS=0.3V
VDS=0.5V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Topt=-40°C
Topt=25°C
Topt=105°C
Topt=-40°C
Topt=25°C
Topt=105°C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage VDD (V)
Input Voltage VDD (V)
R510xx
VDS=1.0V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Topt=-40°C
Topt=25°C
Topt=105°C
0
1
2
3
4
5
6
Input Voltage VDD (V)
36
R510xx
7) Released Delay Time vs. Input Voltage
R510xx
8) Released Delay Time vs. Temperature
R510xx
Topt=25°C
V
DD=6V
500
500
480
460
440
420
400
380
360
340
320
300
480
460
440
420
400
380
360
340
320
300
0
1
2
3
4
5
6
7
-40 -25
0
25
50
75
105
Input Voltage VDD (V)
Temperature Topt (°C)
9) Detector Output Delay Time vs. Temperature 10) WDT Reset Timer vs. Temperature
R510xx
R510xx
100
90
80
70
60
50
40
30
20
10
0
50
48
46
44
42
40
38
36
34
32
30
1µs
-VDET+1V
-VDET 1V
Input Voltage
-
-40 -25
0
25
50
75
105
-40 -25
0
25
50
75
105
Temperature Topt (°C)
Temperature Topt (°C)
11) WDT Timeout Period vs. Temperature
12) WDT Reset Timer vs. Input Voltage
R510xx
R510xx
400
380
360
340
320
300
280
260
240
220
200
50
48
46
44
42
40
38
36
34
32
30
-40 -25
0
25
50
75
105
1
2
3
4
5
6
Temperature Topt (°C)
Input Voltage VDD (V)
37
R510xx
13) WDT Timeout Period vs. Input Voltage
R510xx
14) Output Delay Time vs. External Capacitance
R510xx
1000
400
380
360
340
320
300
280
260
240
220
200
100
tPLH
10
1
1µs 1µs
Input
Voltage
-VDET+1V
-VDET 1V
0.1
-
0.01
0.001
tPHL
1
2
3
4
5
6
0.1
1
10
100
External Capacitance C
D
(nF)
Input Voltage VDD (V)
TECHNICAL NOTES
• R5105N, R5106N, R5107G, R5109G
When R510xxxx1A (Nch Open Drain Output Type) is used in Figure A or Figure B, if impedance of Voltage
Supply pin, VDD and VDD of this IC is large, detector threshold level would shift by voltage dropdown caused by
the consumption current of the IC itself. Released voltage may also shift and delay time for start-up might be
generated by this usage.
When R510xxxx1C (CMOS Output Type) is used in Figure A or Figure B, Output level could be unstable by
cross conduction current which is generated at detector threshold level or at released voltage level, therefore,
do not use this IC with the connection in Figure A or Figure B.
The connection in Figure C may cause the oscillation in both R510xxxx1A (Nch Open Drain Output) and
R510xxxx1C (CMOS Output), therefore do not use R510xx Series with the connection in Figure C.
VDD
VDD
VDD
R1
R1
R1
VDD
VDD
VDD
R2
R510xx Series
RESETB
R510xx Series
RESETB
R510xx Series
RESETB
R2
GND
GND
GND
Figure A
Figure B
Figure C
38
R510xx
• R5108G
When R5108Gxx1A/C is used in the circuit as SENSE pin and VDD pin are connected each other such as in
Figure A, if the value of R1 is set excessively large, the dropdown voltage caused by the consumption current of
IC itself, may vary the detector threshold and the released voltage. Also, if the value of R1 is set excessively
large, there may cause oscillation generated by cross conduction current with released operation.
When R5108Gxx1A/C is used in the circuit as SENSE pin and VDD pin are connected each other such as in
Figure B, if the value of R1 is set excessively large, the dropdown voltage caused by the consumption current of
IC itself, may vary the detecor threshold and the released voltage.
Also, if the value of R1 is set excessively large, there may be delay in start-up and may cause oscillation
generated by cross conduction current. Furthermore, if the value of R1 is set large and the value of R2 is set
small, released voltage level may shift and the minimum operating voltage may differ. If the value of R2 is set
excessively small from R1, release may not occur and may cause oscillation.
V
DD
V
DD
R1
R1
V
DD
V
DD
R2
R5108G Series
SENSE RESETB
R5108G Series
SENSE RESETB
GND
GND
Figure A
Figure B
39
1.The products and the product specifications described in this document are subject to change or
discontinuation of production without notice for reasons such as improvement. Therefore, before
deciding to use the products, please refer to Ricoh sales representatives for the latest
information thereon.
2.The materials in this document may not be copied or otherwise reproduced in whole or in part
without prior written consent of Ricoh.
3.Please be sure to take any necessary formalities under relevant laws or regulations before
exporting or otherwise taking out of your country the products or the technical information
described herein.
4.The technical information described in this document shows typical characteristics of and
example application circuits for the products. The release of such information is not to be
construed as a warranty of or a grant of license under Ricoh's or any third party's intellectual
property rights or any other rights.
5.The products listed in this document are intended and designed for use as general electronic
components in standard applications (office equipment, telecommunication equipment,
measuring instruments, consumer electronic products, amusement equipment etc.). Those
customers intending to use a product in an application requiring extreme quality and reliability,
for example, in a highly specific application where the failure or misoperation of the product
could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system,
traffic control system, automotive and transportation equipment, combustion equipment, safety
devices, life support system etc.) should first contact us.
6.We are making our continuous effort to improve the quality and reliability of our products, but
semiconductor products are likely to fail with certain probability. In order to prevent any injury to
persons or damages to property resulting from such failure, customers should be careful enough
to incorporate safety measures in their design, such as redundancy feature, firecontainment
feature and fail-safe feature. We do not assume any liability or responsibility for any loss or
damage arising from misuse or inappropriate use of the products.
7.Anti-radiation design is not implemented in the products described in this document.
8.Please contact Ricoh sales representatives should you have any questions or comments
concerning the products or the technical information.
RICOH COMPANY., LTD. Electronic Devices Company
■Ricoh awarded ISO 14001 certification.
■
Ricoh presented with the Japan Management Quality Award for 1999.
The Ricoh Group was awarded ISO 14001 certification, which is an international standard for
environmental management systems, at both its domestic and overseas production facilities.
Our current aim is to obtain ISO 14001 certification for all of our business offices.
Ricoh continually strives to promote customer satisfaction, and shares the achievements
of its management quality improvement program with people and society.
Ricoh completed the organization of the Lead-free production for all of our products.
After Apr. 1, 2006, we will ship out the lead free products only. Thus, all products that
will be shipped from now on comply with RoHS Directive.
http://www.ricoh.com/LSI/
RICOH COMPANY, LTD.
Electronic Devices Company
● Higashi-Shinagawa Office (International Sales)
3-32-3, Higashi-Shinagawa, Shinagawa-ku, Tokyo 140-8655, Japan
Phone: +81-3-5479-2857 Fax: +81-3-5479-0502
RICOH EUROPE (NETHERLANDS) B.V.
● Semiconductor Support Centre
Prof. W.H.Keesomlaan 1, 1183 DL Amstelveen, The Netherlands
P.O.Box 114, 1180 AC Amstelveen
Phone: +31-20-5474-309 Fax: +31-20-5474-791
RICOH ELECTRONIC DEVICES KOREA Co., Ltd.
11 floor, Haesung 1 building, 942, Daechidong, Gangnamgu, Seoul, Korea
Phone: +82-2-2135-5700 Fax: +82-2-2135-5705
RICOH ELECTRONIC DEVICES SHANGHAI Co., Ltd.
Room403, No.2 Building, 690#Bi Bo Road, Pu Dong New district, Shanghai 201203,
People's Republic of China
Phone: +86-21-5027-3200 Fax: +86-21-5027-3299
RICOH COMPANY, LTD.
Electronic Devices Company
● Taipei office
Room109, 10F-1, No.51, Hengyang Rd., Taipei City, Taiwan (R.O.C.)
Phone: +886-2-2313-1621/1622 Fax: +886-2-2313-1623
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