RV5C387A-F_技术文档

I²C bus SERIAL INTERFACE REAL-TIME CLOCK IC

WITH VOLTAGE MONITORING FUNCTION

RV5C387A

APPLICATION MANUAL

ELECTRONIC DEVICES DIVISION

NO.EA-054-9908

NOTICE

1. The products and the product specifications described in this application manual are subject to change or

discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to

use the products, please refer to Ricoh sales representatives for the latest information thereon.

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consent of Ricoh.

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otherwise taking out of your country the products or the technical information described herein.

4. The technical information described in this application manual shows typical characteristics of and example

application circuits for the products. The release of such information is not to be construed as a warranty of or a

grant of license under Ricoh's or any third party's intellectual property rights or any other rights.

5. The products listed in this document are intended and designed for use as general electronic components in

standard applications (office equipment, computer equipment, measuring instruments, consumer electronic

products, amusement equipment etc.). Those customers intending to use a product in an application requiring

extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of

the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic

control system, automotive and transportation equipment, combustion equipment, safety devices, life support

system etc.) should first contact us.

6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor

products are likely to fail with certain probability. In order prevent any injury to persons or damages to property

resulting from such failure, customers should be careful enough to incorporate safety measures in their design,

such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or

responsibility for any loss or damage arising from misuse or inappropriate use of the products.

7. Anti-radiation design is not implemented in the products described in this application manual.

8. Please contact Ricoh sales representatives should you have any questions or comments concerning the

products or the technical information.

June 1995

RV5C387A

APPLICATION MANUAL

CONTENTS

......................................................................................................

OUTLINE

1

..................................................................................................

FEATURES

........................................................................................

BLOCK DIAGRAM

2

............................................................................................

APPLICATIONS

2

...................................................................................

PIN CONFIGURATION

2

......................................................................................

PIN DESCRIPTIONS

3

...................................................................

ABSOLUTE MAXIMUM RATINGS

4

.................................................

RECOMMENDED OPERATING CONDITIONS

4

...........................................................

DC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

5

6

..............................................................................

GENERAL DESCRIPTION

7

......................................................................

FUNCTIONAL DESCRIPTIONS

9

_{1. Address Mapping}.........................................................................................

9

_{2. Register Settings}........................................................................................

10

22

31

36

38

41

42

44

46

50

.....................................................................................................

USAGES

_{1. Interfacing with the CPU}...............................................................................

.................

2. Configuration of Oscillation Circuit and Correction of Time Count Deviations

_{3. Oscillation Halt Sensing and Supply Voltage Monitoring}..........................................

_{4. Alarm and Periodic Interrupt}...........................................................................

_{5. 32-kHz Clock Output}...................................................................................

_{6. Typical Applications}....................................................................................

_{7. Typical Characteristics}.................................................................................

_{8. Typical Software-based Operations}..................................................................

.............................................................................

PACKAGE DIMENSIONS

TAPING SPECIFICATION

I²C bus SERIAL INTERFACE REAL-TIME CLOCK IC

WITH VOLTAGE MONITORING FUNCTION

RV5C387A

OUTLINE

The RV5C387A is a CMOS real-time clock IC connected to the CPU by two signal, SCL and SDA, and configured to

perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to

generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm circuits

generate interrupt signals at preset times. The oscillation circuit is driven under constant voltage so that fluctuations

in oscillation frequency due to voltage are small and supply current is also small (TYP. 0.35µA for the RV5C387A at

3 volts). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as

power-on. The supply voltage monitoring circuit is configured to record a drop in supply voltage below two

selectable supply voltage monitoring threshold settings. The 32-kHz clock output function (Nch. open drain) is

intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended

to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal

oscillator. The 32-kHz clock circuit can be disabled by certain register settings. This model comes in an ultra-

compact 10-pin SSOP-G (with a height of 1.20mm and a pin pitch of 0.5mm).

FEATURES

• Timekeeping supply voltage ranging from 1.45 to 5.5 volts

• Low supply current: TYP. 0.35µA (MAX. 0.8µA) at 3 volts

• Only two signal lines (SCL, SDA) required for connection to the CPU.

(I²C bus compatible, 400kHz at VDD≥2.5V, address 7bits)

• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,

and weeks) (in BCD format)

• 1900/2000 identification bit for Year 2000 compliance

• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)

to the CPU and provided with an interrupt flag and an interrupt halt circuit

• 2 alarm circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute

alarm settings)

• 32-kHz clock circuit (Nch. open drain output)

• Oscillation halt sensing circuit which can be used to judge the validity of internal data

• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings

• Automatic identification of leap years up to the year 2099

• Selectable 12-hour and 24-hour mode settings

• High precision oscillation adjustment circuit

• Built-in oscillation stabilization capacitors (C^Gand CD)

• CMOS process

• Ultra-compact 10-pin SSOP-G(with a height of 1.20mm and size 4.0mm×2.9mm)

1

RV5C387A

Note

· I²C bus is a trademark of PHILIPS ELECTRONICS N.V.

· Purchase of I²C components of Ricoh Company, Ltd. conveys a license under the Philips I²C Patent Rights to

use these components in an I²C system, provided that the system comforms to the I²C Standard

Specification as defined by Philips.

BLOCK DIAGRAM

ALARM_W REGISTER

COMPARATOR_W

32KOUT

32kHz

(MIN,HOUR,WEEK)

OUTPUT

CONTROL

VDD

VSS

ALARM_D REGISTER

(MIN,HOUR)

VOLTAGE

DETECT

COMPARATOR_D

OSCIN

DIVIDER

TIME COUNTER

(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)

OSC

CORREC

-TION

DIV

OSCOUT

SCL

SDA

OSC

DETECT

ADDRESS

DECODER

ADDRESS

REGISTER

INTRA

INTRB

INTRC

I/O

CONTROL

INTERRUPT CONTROL

SHIFT REGISTER

APPLICATIONS

• Communication devices (multi function phone, portable phone, PHS or pager)

• OA devices (fax, portable fax)

• Computer (desk-top and mobile PC, portable word-processor, PDA, electric note or video game)

• AV components (portable audio unit, video camera,camera, digital camera or remote controller)

• Home appliances (rice cooker, electric oven)

• Other (car navigation system, multi-function watch)

PIN CONFIGURATION

• 10-pin SSOP-G

1

2

3

4

5

10

9

32KOUT

SCL

VDD

OSCIN

OSCOUT

8

SDA

7

INTRB

INTRA

INTRC

VSS

6

2

RV5C387A

PIN DESCRIPTIONS

Pin No. Symbol

Item

Description

This pin is used to input shift clock pulses to synchronize data input/output to and

from the SDA pin with this clock. Allows a maximum input voltage of 5.5 volts

regardless of supply voltage.

2

3

SCL

SDA

Serial Clock Line

This pin inputs and outputs written or read data in synchronization with shift clock

pulses from the SCL pin. Allows a maximum input voltage of 5.5 volts regardless

of supply voltage.

Serial Data Line

This pin outputs periodic interrupt pulses to the CPU. This pin is off when power

is activated from 0V. This pin functions as an Nch open drain output.

6

7

4

INTRA Interrupt Output A

INTRB Interrupt Output B

INTRC Interrupt Output C

This pin outputs alarm interrupt (ALARM_W) to the CPU. This pin is off when

power is activated from 0V. This pin functions as an Nch open drain output.

This pin outputs alarm interrupt (ALARM_D) to the CPU. This pin is off when

power is activated from 0V. This pin functions as an Nch open drain output.

The 32KOUT pin is used to output 32.768-kHz clock pulses. Enabled at power-on

1

32KOUT 32-kHz Clock Output from 0 volts. Nch. open drain output. The RV5C387A is designed to be disable 32-

kHz clock output in response to a command from the host computer.

9

8

OSCIN

Oscillatory Circuit The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal

OSCOUT Input/Output

oscillator (with all other oscillation circuit components built into the RV5C387A).

10

5

VDD

VSS

Positive Power Supply Input

Negative Power Supply Input

The VDD pin is connected to the power supply. The VSS pin is grounded.

3

RV5C387A

ABSOLUTE MAXIMUM RATINGS

(Vss=0V)

Symbol

VDD

Item

Supply Voltage

Conditions

Ratings

Unit

–0.3 to +6.5

V

VI

Input Voltage 2

Output Voltage

SCL, SDA

SDA, INTRA, INTRB

INTRC, 32KOUT

VO

–0.3 to +6.5

V

PD

Power Dissipation

Topt=25˚C

300

mW

˚C

Topt

Tstg

Operating Temperature

Storage Temperature

–40 to +85

–55 to +125

˚C

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum ratings are threshold limit values that must not be exceeded even for an instant under

any conditions. Moreover, such values for any two items must not be reached simultaneously. Operation

above these absolute maximum ratings may cause degradation or permanent damage to the device. These

are stress ratings only and do not necessarily imply functional operation below these limits.

RECOMMENDED OPERATING CONDITIONS

(Vss=0V,Topt=–40 to +85˚C)

Symbol

VDD

Item

Supply Voltage

Conditions

MIN.

2.0

TYP.

MAX.

5.5

Unit

V

VCLK

fXT

Timekeeping Voltage

Oscillation Frequency

Pull-up Voltage

1.45

5.5

V

32.768

kHz

V

VPUP

SCL, SDA, INTRA, INTRB, INTRC

5.5

4

RV5C387A

DC ELECTRICAL CHARACTERISTICS

Unless otherwise specified :Vss=0V,VDD=3V,Topt=–40 to +85˚C

Symbol

VIH

Item

Pin name

Conditions

MIN.

0.8VDD

–0.3

0.5

TYP.

MAX.

5.5

Unit

“H” Input Voltage

“L” Input Voltage

V

SCL,SDA

VDD=2.5 to 5.5V

VIL

0.2VDD

IOL1

IOL2

IOL3

32KOUT

“L” Output Current

INTRA, INTRB, INTRC VOL=0.4V

SDA

1.0

mA

4.0

VI=5.5V or Vss

VDD=5.5V

IIL

Input Leakage Current SCL

SDA, INTRA, INTRB

–1

1

µA

Vo=5.5V or Vss

VDD=5.5V

IOZ

INTRC

VDD=3V,

SCL=SDA=3V,

IDD

VDD

0.35

0.8

µA

Output=OPEN

32KOUT=OFF mode*¹

Supply Voltage Monitoring

Voltage (“H”

VDETH

VDETL

Topt=–30 to +70˚C

1.90

1.45

2.10

1.60

2.30

1.80

V

VDD

)

Supply Voltage Monitoring

Voltage (“L”

)

CG

CD

Internal Oscillation Capacitance 1 OSCIN

Internal Oscillation Capacitance 2 OSCOUT

12

pF

1) For standby current for outputting 32.768-kHz clock pulses from the 32KOUT pin, see “USAGES, 7. Typical Characteristics”.

*

5

RV5C387A

AC ELECTRICAL CHARACTERISTICS

Unless otherwise specified : VSS=0V, Topt=–40 to +85˚C

I/O conditions: V^IH=0.8×VDD, VIL=0.2×VDD, VOL=0.2×VDD, CL=50pF

VDD≥2.0V

TYP. MAX. MIN.

VDD≥2.5V

TYP. MAX.

Symbol

Item

Conditions

Unit

MIN.

fSLC

tLOW

SCL clock frequency

100

400

kHz

µs

ns

µs

ns

SCL clock “L” time

4.7

4.0

4.7

250

0

1.3

0.6

200

0

tHIGH

SCL clock “H” time

tHD ; STA

tSU ; STO

tSU ; STA

tSU ; DAT

tHD ; DAT

tPL ; DAT

tPZ ; DAT

tR

Start condition hold time

Stop condition setup time

Start condition setup time

Data setup time

Data hold time

SDA “L” stable time after falling of SCL

SDA off stable time after falling of SCL

Rising time of SCL and SDA (input)

Falling time of SCL and SDA (input)

2.0

0.9

1000

300

tF

Spike width that can be removed

with input filter

tSP

50

ns

S

Sr

P

SCL

tHD;STA

tSP

t^LOW

tHIGH

SDA(IN)

tHD;STA

tSU;DAT

tHD;DAT

tSU;STA

tSU;STO

SDA(OUT)

tPZ;DAT

tPL;DAT

Start condition

Stop condition

P

S

Sr Repeated start condition

)

For read/write timing, see “USAGES, 1.5 Considerations in Reading and Writing Time Data”.

*

6

RV5C387A

GENERAL DESCRIPTION

1. Interface with CPU

The RV5C387A is connected to the CPU by two signal lines SCL and SDA, through which it reads and writes data

from and to the CPU. Since the output of the I/O pin of SDA is open drain, data interfacing with a CPU different

supply voltage is possible by applying pull-up resistors on the circuit board. The maximum clock frequency of

400kHz (at VDD≥2.5V) of SCL enables data transfer in I²C bus fast mode.

2. Clock and Calendar Function

The RV5C387A reads and writes time data from and to the CPU in units ranging from seconds to the last two digits

of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a

multiple of 4. Also available is the 1900/2000 identification bit for Year 2000 compliance. Consequently, leap years

up to the year 2099 can automatically be identified as such.

)

The year 2000 is a leap year while the year 2100 is not a leap year.

*

3. Alarm Function

The RV5C387A incorporates an alarm circuit configured to generate interrupt signals to the CPU for output from

the INTRB or INTRC pin at preset times. The alarm circuit allows two types of alarm settings specified by the

Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm

settings including combinations of multiple day-of-week settings such as “Monday, Wednesday, and Friday” and

“Saturday and Sunday”. The Alarm_D registers allow hour and minute alarm settings. The Alarm_W signal outputs

from INTRB pin, and the Alarm_D signal outputs from INTRC pin. The current INTRB or INTRC pin conditions

specified by these two registers can be checked from the CPU by using a polling function.

4. High-precision Oscillation Adjustment Function

The RV5C387A has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external

crystal oscillator to configure an oscillation circuit. To correct deviations in the oscillation frequency of the crystal

oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to

1.5ppm at 25˚C) from the CPU within a maximum range of approximately 189ppm in increments of approximately

3ppm. Such oscillation frequency adjustment in each system has the following advantages:

·

Allows timekeeping with much higher precision than conventional real-time clocks while using a crysta

l oscillator with a wide range of precision variations.

·

Corrects seasonal frequency deviations through seasonal oscillation adjustment.

Allows timekeeping with higher precision particularly in systems with a temperature sensing function

through oscillation adjustment in tune with temperature fluctuations.

7

RV5C387A

5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function

The RV5C387A incorporates an oscillation halt sensing circuit equipped with internal registers configured to record

any past oscillation halt, thereby identifying whether they are powered on from 0 volts or battery backed-up. As

such, the oscillation halt sensing circuit is useful for judging the validity of time data.

The RV5C387A also incorporates a supply voltage monitoring circuit equipped with internal registers configured to

record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can

be selected between 2.1 and 1.6 volts through internal register settings.

The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to

the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply

voltage monitoring circuit can be applied to battery supply voltage monitoring.

6. Periodic Interrupt Function

The RV5C387A incorporates a periodic interrupt circuit configured to generate periodic interrupt signals aside from

interrupt signals generated by the alarm circuit for output from the INTRA pin. Periodic interrupt signals have five

selectable frequency settings of 2Hz (once per 0.5 seconds), 1Hz (once per 1 second), 1/60Hz (once per 1 minute),

1/3600Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also

have two selectable waveforms of a normal pulse form (with a frequency of 2Hz or 1Hz) and special form adapted to

interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The register

records of periodic interrupt signals can be monitored by using a polling function.

7. 32-kHz Clock Output Function

The RV5C387A incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequen-

cy of a 32.768-kHz crystal oscillator for output from the 32KOUT pin. The 32KOUT pin is Nch. open drain output.

The 32-kHz clock output can be disabled by certain register settings. But it cannot be disabled without manipulation

of any two registers with different addresses, to prevent disabling in such events as the runaway of the CPU. The

32-kHz clock circuit is enabled at power-on.

8

RV5C387A

FUNCTIONAL DESCRIPTIONS

1. Address Mapping

Address

Register

A2

A1

A0

D7

D6

D5

D4

D3

D2

A3

D1

D0

0

1

0

Second Counter

Minute Counter

–*²

S40

S20

S10

S8

S4

S2

S1

0

1

0

–

M40

–

M20

M10

H10

M8

H8

M4

H4

M2

H2

M1

H1

H20

Hour Counter

2

P/A

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Day-of-week Counter

Day-of-month Counter

–

D20

–

W4

D4

W2

D2

W1

D1

D10

D8

Month Counter and Century Bit 19/20

–

MO10 MO8 MO4 MO2 MO1

Year Counter

Y80

–

Y40

F6

Y20

F5

Y10

F4

Y8

F3

Y4

F2

Y2

F1

Y1

F0

3

Oscillation Adjustment Register

*

Alarm_W (minute register)

Alarm_W (hour register)

–

WM40 WM20 WM10 WM8 WM4 WM2 WM1

WH20

9

1

0

1

–

WH10 WH8 WH4 WH2 WH1

WP/A

A

B

1

0

1

0

1

Alarm_W (Day-of-week register

)

–

WW6 WW5 WW4 WW3 WW2 WW1 WW0

DM40 DM20 DM10 DM8 DM4 DM2 DM1

DH20

Alarm_D (minute register)

C

1

0

Alarm_D (hour register)

–

DH10 DH8

DH4

DH2

DH1

DP/A

D

E

F

1

0

1

0

1

–

Control Register 1*³

Control Register 2*³

WALE DALE 12/24 CLEN2 TEST CT2

CT1

CT0

VDSL VDET SCRATCH XSTP CLEN1 CTFG WAFG DAFG

1) All the data listed above accept both reading and writing.

*

2) The data marked with “–” is invalid for writing and reset to 0 for reading.

3) When the XSTP bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register 1, control register 1 and control register 2

excluding the XSTP bit.

9

RV5C387A

2. Register Settings

2.1 Control Register 1 (at Address Eh)

D7

WALE

0

D6

DALE

0

D5

12/24

0

D4

CLEN2

0

D3

TEST

0

D2

CT2

0

D1

CT1

0

D0

CT0

0

(For writing)

(For reading)

Default settings*¹

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

2.1-1 WALE and DALE

Alarm_W Enable Bit and Alarm_D Enable Bit

WALE, DALE

Description

Disabling the alarm interrupt circuit (under the control of the settings of the

Alarm_W registers and the Alarm_D registers).

0

(Default setting)

Enabling the alarm interrupt circuit (under the control of the settings of the

Alarm_W registers and the Alarm_D registers)

1

2.1-2 12/24

12-/24-hour Mode Selection Bit

12/24

Description

0

1

Selecting the 12-hour mode with a.m. and p.m. indications.

Selecting the 24-hour mode

(Default setting)

Setting the 12/24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.

Table of Time Digit Indications

24-hour mode

12-hour mode

24-hour mode

12-hour mode

00

01

02

03

04

05

06

07

08

09

10

11

12 (AM12)

01 (AM 1)

02 (AM 2)

03 (AM 3)

04 (AM 4)

05 (AM 5)

06 (AM 6)

07 (AM 7)

08 (AM 8)

09 (AM 9)

10 (AM10)

11 (AM11)

12

13

14

15

16

17

18

19

20

21

22

23

32 (PM12)

21 (PM 1)

22 (PM 2)

23 (PM 3)

24 (PM 4)

25 (PM 5)

26 (PM 6)

27 (PM 7)

28 (PM 8)

29 (PM 9)

30 (PM10)

31 (PM11)

)

Setting the 12/24 bit should precede writing time data.

*

10

RV5C387A

2.1-3 CLEN2

32-kHz Clock Output Bit 2

CLEN2

Description

(Default setting)

0

1

Enabling the 32-kHz clock circuit

Disabling the 32-kHz clock circuit

For the RV5C387A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, specifies generating

clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.

Conversely, setting both the CLEN1 and the CLEN2 bit to 1 specifies disabling (“H”) such output.

2.1-4 TEST

Test Bit

TEST

Description

0

1

Normal operation mode

Test mode

(Default setting)

The TEST bit is used only for testing in the factory and should normally be set to 0.

11

RV5C387A

2.1-5 CT2, CT1, and CT0

Periodic Interrupt Selection Bits

Description

Interrupt Cycle and Fall Timing

CT2

CT1

CT0

Waveform Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

Off (“H”)

Fixed at low (“L”)

(Default setting)

Pulse Mode 2Hz (Duty cycle of 50%)

Pulse Mode 1Hz (Duty cycle of 50%)

Level Mode Once per 1 second (Synchronized with second counter increment)

Level Mode Once per minute (at 00 seconds of every minute)

Level Mode Once per hour (at 00 minutes and 00 seconds of every hour)

Level Mode Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)

1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter

as illustrated in the timing chart on the next page.

2) Level Mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute,

1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of

periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting

of 1 second are output in synchronization with the increment of the second counter as illustrated

in the timing chart on the next page.

3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows:

Pulse Mode: the “L” period of output pulses will increment or decrement by a maximum of 3.784ms.

For example, 1-Hz clock pulses will have a duty cycle of 50 0.3784%.

Level Mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784ms.

12

RV5C387A

Relation Between the Mode Waveform and the CTFG Bit

• Pulse mode

CTFG bit

INTRA pin

Approx. 92µs

Rewriting of the second counter

(Increment of second counter)

)

In the pulse mode, the increment of the second counter is delayed by approximately 92µs from the falling edge of clock pulses. Consequently, time

readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.

*

• Level mode

CTFG bit

INTRA pin

Setting CTFG bit to 0

(Increment of

second counter)

(Increment of

second counter)

(Increment of

second counter)

13

RV5C387A

2.2 Control Register 2 (at Address Fh)

D7

VDSL

0

D6

D5

D4

XSTP

1

D3

CLEN1

0

D2

CTFG

0

D1

WAFG

0

D0

DAFG

0

(For write operation)

(For read operation)

Default setting*¹

VDET SCRATCH

0

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

2.2-1 VDSL

Supply Voltage Monitoring Threshold Selection Bit

VDSL

Description

0

1

Selecting the supply voltage monitoring threshold setting of 2.1 volts.

Selecting the supply voltage monitoring threshold setting of 1.6 volts.

(Default setting)

The VDSL bit is intended to select the supply voltage monitoring threshold settings.

2.2-2 VDET

Supply Voltage Monitoring Result Indication Bit

VDET

Description

(Default setting)

0

1

Indicating supply voltage above the supply voltage monitoring threshold settings.

Indicating supply voltage below the supply voltage monitoring threshold settings.

Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the

setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit.

Conversely, setting the VDET bit to 1 causes no event.

2.2-3 SCRATCH

Scratch Bit

SCRATCH

Description

0

1

(default settings)

The SCRATCH bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH bit will

be set to 0 when the XSTP bit is set to 1 in the control register 2.

14

RV5C387A

2.2-4 XSTP

Oscillation Halt Sensing Bit

XSTP

Description

0

1

Sensing a normal condition of oscillation

Sensing a halt of oscillation

(Default setting)

The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation halt sensing circuit

operates only when the CE pin is “L”.

· The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as

power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the restart of

oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data after power-on or

a drop in supply voltage.

· When the XSTP bit is set to 1, all bits will be reset to 0 in the oscillation adjustment register, control register 1,

and control register 2, stopping the output from the INTRA, INTRB, INTRC pin and starting the output of 32.768-

kHz clock pulses from the 32KOUT pin.

· The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely, setting

the XSTP bit to 1 causes no event.

2.2-5 CLEN1

32-kHz Clock Output Bit 1

CLEN1

Description

(Default setting)

0

1

Enabling the 32-kHz clock output

Disabling the 32-kHz clock output

Setting the CLEN1 bit or the CLEN2 bit (D4 in control register 1) to 0, specifies generating clock pulses with the

oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both

the CLEN1 bit and the CLEN2 bit to 1 specifies disabling (“L”) such output.

15

RV5C387A

2.2-6 CTFG

Periodic Interrupt Flag Bit

CTFG

Description

0

1

Periodic interrupt output “H” (OFF)

Periodic interrupt output “L” (ON)

(Default setting)

The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTRA pin (“L”). The CTFG bit

accepts only the writing of 0 in the level mode, which disables (“H”) the INTRA pin until it is enabled (“L”) again in

the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.

2.2-7 WAFG and DAFG

Alarm_W Flag Bit and Alarm_D Flag Bit

WAFG, DAFG

Description

0

1

Indicating a mismatch between current time and preset alarm time

Indicating a match between current time and preset alarm time

(Default setting)

The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused

approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers

and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTRB

or INTRC pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG

bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is

disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with

the output of the INTRB and INTRC pins as shown in the timing chart below.

Output Relationships Between the WAFG or DAFG Bit and INTRB, INTRC

Approx.61µs

Settings of WAFG (DAFG) bit

Output of INTRB (INTRC) pin

Writing of 0 to WAFG

(DAFG) bit

Writing of 0 to WAFG

(DAFG) bit

(Match between current time

(

Match between current time

(

Match between current time

and preset alarm time

)

and preset alarm time

)

and preset alarm time

)

16

RV5C387A

2.3 Time Counters (at Addresses 0h to 2h)

· Time digit display (BCD format) as follows:

The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00.

The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.

The hour digits range as shown in “2.1-2 12/24: 12-/ 24-hour Mode Selection Bit” and are carried to the

day-of-month and day-of-week digits in transition from PM11 to AM12 or from 23 to 00.

· Any writing to the second counter resets divider units of less than 1 second.

· Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction.

Therefore, such incorrect writing should be replaced with the writing of existent time data.

2.3-1 Second Counter (at Address 0h)

D7

—

D6

S40

D5

S20

D4

S10

D3

S8

D2

S4

D1

S2

D0

S1

(For writing)

(For reading)

Default settings*

0

S40

S20

S10

S8

S4

S2

S1

Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite

2.3-2 Minute Counter (at Address 1h)

D7

—

D6

D5

D4

D3

M8

D2

M4

D1

M2

D0

M1

(For writing)

M40

M20

M10

(For reading)

Default settings*

0

M40

M20

M10

M8

M4

M2

M1

Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite

2.3-3 Hour Counter (at Address 2h)

D7

—

D6

—

D5

D4

D3

H8

D2

H4

D1

H2

D0

H1

(For writing)

P/A or H20

H10

(For reading)

Default settings*

0

P/A or H20

H10

H8

H4

H2

H1

Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

17

RV5C387A

2.4 Day-of-week Counter (at Address 3h)

D7

—

D6

—

D5

—

D4

—

D3

—

D2

W4

D1

W2

D0

W1

(For writing)

(For reading)

Default settings*

0

W4

W2

W1

Indefinite Indefinite Indefinite

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

· The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits.

· Day-of-week display (incremented in septimal notation):

...

(W4, W2, W1) = (0, 0, 0) → (0, 0, 1) → → (1, 1, 0) → (0, 0, 0)

· Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0)

· The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.

2.5 Calendar Counters (at Addresses 4h to 6h)

· The calendar counters are configured to display the calendar digits in BCD format by using the automatic

calendar function as follows:

The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and

December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years;

from 1 to 28 for February in ordinary years.

The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. The

month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1.

...

The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, , 92, and 96 in leap years) and are carried to the

19/20 digits in reversion from 99 to 00.

The 19/20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.

· Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to

malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar data.

2.5-1 Day-of-month Counter (at Address 4h)

D7

—

D6

—

D5

D4

D3

D8

D2

D4

D1

D2

D0

D1

(For writing)

D20

D10

(For reading)

Default settings*

0

D20

D10

D8

D4

D2

D1

Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite

2.5-2 Month Counter + Century Bit (at Address 5h)

D7

D6

—

D5

—

D4

D3

D2

D1

D0

(For writing)

19/20

MO10

MO8

MO4

MO2

MO1

(For reading)

Default settings*

19/20

0

MO10

MO8

MO4

MO2

MO1

Indefinite

Indefinite Indefinite Indefinite Indefinite Indefinite

18

RV5C387A

2.5-3 Year Counter (at Address 6h)

D7

Y80

D6

Y40

D5

Y20

D4

Y10

D3

Y8

D2

Y4

D1

Y2

D0

Y1

(For writing)

(For reading)

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

Default settings*

Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

2.6 Oscillation Adjustment Register (at Address 7h)

D7

—

D6

F6

D5

F5

D4

F4

D3

F3

D2

F2

D1

F1

D0

F0

(For writing)

(For reading)

Default settings*

F6

0

F5

0

F4

0

F3

0

F2

0

F1

0

F0

0

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

2.6-1 F6 to F0

The oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the

oscillation adjustment register when the second digits read 00, 20, or 40 seconds. Normally, the second counter is

incremented once per 32768 32.768-kHz clock pulses generated by the crystal oscillator. Writing to the F6 to F0 bits

activates the oscillation adjustment circuit.

· The oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of

writing to the oscillation adjustment register.

· The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) –1) × 2.

The F6 bit setting of 1 causes a decrement of time counts by (( F5, F4, F3, F2, F1, F0) +1) × 2.

The settings of “ , 0, 0, 0, 0, 0, ” ( “ ” representing either “0” or “1” ) in the F6, F5, F4, F3, F2, F1, and F0 bits

*

cause neither an increment nor decrement of time counts.

Example:

When the second digits read 00, 20, or 40, the settings of “0, 0, 0, 0, 1, 1, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits

cause an increment of the current time counts of 32768 by (7–1) × 2 to 32780 (a current time count loss). When the

second digits read 00, 20, or 40, the settings of “0, 0, 0, 0, 0, 0, 1” in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither

an increment nor a decrement of the current time counts of 32768.

When the second digits read 00, 20, or 40, the settings of “1, 1, 1, 1, 1, 1, 0” in the F6, F5, F4, F3, F2, F1, and F0 bits

cause a decrement of the current time counts of 32768 by (–2) × 2 to 32764 (a current time count gain).

19

RV5C387A

An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768 ×

20=3.051ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3ppm.

Consequently, deviations in time counts can be corrected with a precision of 1.5ppm. Note that the oscillation

adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-

kHz clock pulses. For further details, see “USAGE, 2.4 Oscillation Adjustment Circuit”.

2.7 Alarm_W Registers (at Addresses 8h to Ah)

2.7-1 Alarm_W Minute Register (at Address 8h)

D7

—

0

D6

D5

D4

D3

WM8

D2

WM4

D1

WM2

D0

WM40

Indefinite

WM20

Indefinite

WM10

Indefinite

WM1

(For writing)

WM8

WM4

WM2

WM1

(For reading)

Default settings*

0

Indefinite

2.7-2 Alarm_W Hour Register (at Address 9h)

D7

—

0

D6

—

0

D5

D4

D3

WH8

D2

WH4

D1

WH2

D0

WH1

WH20,WP/A

Indefinite

WH10

Indefinite

(For writing)

WH8

WH4

WH2

WH1

(For reading)

Default settings*

0

Indefinite

2.7-3 Alarm_W Day-of-week Register (at Address Ah)

D7

—

0

D6

D5

D4

D3

WW3

D2

WW2

D1

WW1

D0

WW6

WW5

WW4

WW0

(For writing)

WW6

WW5

WW4

WW3

WW2

WW1

WW0

(For reading)

Default settings*

0

Indefinite

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

· The D5 bit of the Alarm_W hour register represents WP/A when the 12-hour mode is selected (0 for a.m. and 1

for p.m.). and WH20 when the 24-hour mode is selected (tens in the hour digits).

· The Alarm_W registers should not have any non-existent alarm time settings. (Note that any mismatch between

current time and preset alarm time specified by the Alarm_W registers may disable the alarm circuit.)

· When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2

12/24: 12-/24-hour Mode Selection Bit”).

· WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0, 0) to (1,

1, 0).

· WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W registers.

20

RV5C387A

Example of Alarm Time Setting

Day-of-week

12-hour mode

24-hour mode

Preset alarm time

Sun. Mon. Tue. Wed. Thu. Fri. Sat.

WW0 WW1 WW2 WW3 WW4 WW5 WW6

10-hour 1-hour 10-min 1-min 10-hour 1-hour 10-min 1-min

00:00 a.m. on all days

01:30 a.m. on all days

11:59 a.m. on all days

1

0

1

2

1

0

3

5

0

9

0

1

0

1

0

3

5

0

9

00:00 p.m. on

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

3

2

3

2

1

0

3

5

0

9

1

2

3

0

3

5

0

9

Mondays to Fridays

01:30 p.m. on Sundays

11:59 p.m. on Mondays,

Wednesdays, and Fridays

Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an

example and not mandatory.

2.8 Alarm_D Registers (at Addresses Bh to Ch)

2.8-1 Alarm_D Minute Register (at Address Bh)

D7

—

0

D6

D5

D4

D3

DM8

D2

DM4

D1

DM2

D0

DM1

DM40

Indefinite

DM20

Indefinite

DM10

Indefinite

(For writing)

DM8

DM4

DM2

DM1

(For reading)

Default settings*

0

Indefinite

2.8-2 Alarm_D Hour Register (at Address Ch)

D7

—

0

D6

—

0

D5

D4

D3

DH8

D2

DH4

D1

DH2

D0

DH1

DH20,DP/A

Indefinite

DH10

(For writing)

DH10

DH8

DH4

DH2

DH1

(For reading)

Default settings*

0

Indefinite

)

Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop.

*

· The D5 bit represents DP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.). and DH20 when the 24-

hour mode is selected (tens in the hour digits).

· The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between

current time and preset alarm time specified by the Alarm_D registers may disable the alarm circuit.)

· When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively (see “2.1-2

12/24: 12-/24-hour Mode Selection Bit”).

21

RV5C387A

USAGES

1. Interfacing with the CPU

The RV5C387A employs the I²C bus system to be connected to the CPU via 2-wires. Connection and transfer

system of I²C bus are described in the following sections.

Note

I²C bus is a trademark of PHILIPS ELECTRONICS N.V.

1.1 Connection of I²C bus

2-wires, SCL and SDA which are connected to I²C bus are used for transmit clock pulses and data respectively.

All ICs that are connected to these lines are designed that will be not be clamped when a voltage beyond supply

voltage is applied to input or output pins. Open drain pins are used for output. This construction allows

communication of signals between ICs with different supply voltages by adding a pull-up resistor to each signal line

as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines when power to each of

these is turned off separately.

VDD1

V^DD2

V^DD3

V^DD4

1) For data interface, the following conditions must be met:

*

V^DD4≥VDD1

V^DD4≥VDD2

V^DD4≥VDD3

2) When the master is one, the micro controller is ready for

driving SCL to “H” and R^Pof SCL may not be required.

R^P

RP

SCL

SDA

Other

Peripheral

Device

Microcontroller

RV5C387A

22

RV5C387A

Cautions on Determining RP Resistance

(1) Voltage drop at RP due to sum of input current or output current at off conditions on each IC pin

connected to the I²C bus shall be adequately small.

(2) Rising time of each signal shall be kept short even when all capacity of the bus is driven.

(3) Current consumed in I²C bus is small compared to the consumption current permitted for the entire

system.

When all ICs connected to I²C bus are CMOS type, condition (1) may usually be ignored since input current

and off state output current is extremely small for the many CMOS type ICs.

Thus the maximum resistance of RP may be determined based on (2) while the minimum on (3) in most

cases.

In actual cases a resistor may be place between the bus and input/output pins of each IC to improve noise

margins in which case the RP minimum value may be determined by the resistance.

Consumption current in the bus to review (3) above may be expressed by the formula below:

(Sum of input current and off state output current of all devices in stand-by mode)

× Bus stand-by duration

.

Bus consumption current =

Bus stand-by duration + bus operation duration

Supply voltage × bus operation duration × 2

RP resistance × 2 × (bus stand-by duration + bus operation duration)

+

supply voltage × bus capacity × charging/discharging times per unit time

Operation of “× 2” in the second member denominator in the above formula is derived from assumption that

“L” duration of SDA and SCL pins are the half of bus operation duration. “× 2” in the numerator of the same

member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per

unit time) means number of transition from “H” to “L” of the signal line.

Calculation example is shown below:

Pull-up resistor (RP)=10kΩ, Bus capacity=50pF (both for SCL and SDA), VDD=3V

In as system with sum of input current and off state output current of each pin=0.1µA, I²C bus is used for

10ms every second while the rest of 990ms is in the stand-by mode. In this mode number of transitions of the

SCL pin from “H” to “L” state is 100 while SDA 50, every second.

0.1µA × 990ms

990ms + 10ms

.

Bus consumption current =

3V × 10ms × 2

10kΩ × 2 × (990ms + 10ms)

+

=

3V × 50pF × (100 + 50)

0.099µA + 3.0µA + 0.0225µA = 3.12µA

Generally, the second member of the above formula is larger enough than the first and the third members,

bus consumption current may be determined by the second member in many cases.

23

RV5C387A

1.2 Transmission System of I²C bus

1.2-1 Start and stop conditions

In I²C bus, SDA must be kept at a certain state while SCL is at the “H” state as shown below during data

transmission.

SCL

SDA

tSU;DAT

tHDL;DAT or tHDH;DAT

The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L”

when the SCL is “H” activates the start condition and access is started. Changing the SDA from “L” to “H” when the

SCL is “H” activates stop condition and accessing stopped. Generation of start and stop conditions are always made

by the master (see the figure below).

Start condition

Stop condition

SCL

SDA

tHD;STA

t^SU;STO

1.2-2 Data transmission and its acknowledge

After start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially transmitted.

The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted.

The acknowledge signal is sent immediately after falling to “L” of SCL8bit clock pulses of data transmission, by

releasing the SDA by the transmission side that has asserted the bus at that time and by turning the SDA to “L” by

the receiving side. When transmission of 1byte data next to preceding 1byte of data is received the receiving side

releases the SDA pin at falling edge of the SCL9bit of clock pulses or when the receiving side switches to the

transmission side it starts data transmission. When the master is the receiving side, it generates no acknowledge

signal after the last 1byte of data from the slave to tell the transmitter that data transmission has completed when

the slave side (transmission side) continues to release the SDA pin so that the master will be able to generate stop

condition.

SCL from the master

1

2

8

9

SDA from

the transmission side

SDA from

the receiving side

Start condition

Acknowledge signal

24

RV5C387A

1.2-3 Data transmission format in I²C bus

I²C bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte is

allocated to this 7bit of slave address and to the command (R/W) for which data transmission direction is

designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and

after bytes are read, when 8bit is “H” and write when “L”.

The slave address of the RV5C387A is specified at (0110010).

At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start

condition is generated without generating stop condition, repeated start condition is met and transmission/receiving

data may be continued by setting the slave address again. Use this procedures when the transmission direction

needs to be changed during one transmission.

Data is written into

the slave from the master

S

0

A

A P

Slave address

Data

(0110010)

R/W=0 (Write)

When data is read from

the slave immediately

after 7bit addressing

from the master

1

A

A P

Slave address

Data

Inform read has been completed by

not generating an acknowledge signal,

to the slave side.

(0110010)

R/W=1 (Read)

When the transmission

direction is to be changed

during transmission.

S

A

0

A

A Sr

1

Slave address

Data

Slave address

(0110010)

Data

R/W=0 (Write)

A

R/W=1 (Read)

A

P

Inform read has been completed by

not generating an acknowledge signal, to the slave side.

Master to slave

Start condition

Slave to master

Stop condition

A

Acknowledge signal

S

P

Sr Repeated start condition

25

RV5C387A

1.2-4 Data transmission write format in the RV5C387A

Although the I²C bus standard defines a transmission format for the slave address allocated for each IC,

transmission method of address information in IC is not defined. The RV5C387A transmits data the internal address

pointer (4bit) and the transmission format register (4bit) at the 1byte next to one which transmitted a slave address

and a write command. For write operation only one transmission format is available and (0000) is set to the

transmission format register. The 3byte transmits data to the address specified by the internal address pointer

written to the 2byte. Internal address pointer settings are automatically incremented for 4byte and after. Note that

when the internal address pointer is Fh, it will change to 0h on transmitting the next byte.

Example of data writing (When writing to internal address Eh to Fh)

R/W=0 (Write)

S

0

1

0

1

0

A

1

0

A

A P

Data

Transmission of

slave address

(0110010)

Setting of Setting of

Writing of data to the

internal address Eh.

Writing of data to the

internal address Fh.

Eh to the

internal

address

pointer

0h to the

trans-

mission

format

register

Master to slave

Start condition

Slave to master

S

A

P Stop condition

A

Acknowledge signal

26

RV5C387A

1.2-5 Data transmission read format of the RV5C387A

The RV5C387A allows the following three readout methods of data from an internal register.

1) The first method to reading data from the internal register is to specify an internal address by setting the internal

address pointer and the transmission format register described 1.2-4, generate the repeated start condition (see

section 1.2-3) to change the data transmission direction to perform reading. The internal address pointer is set to

Fh when the stop condition is met. Therefore, this method of reading allows no insertion of the stop condition

before the repeated start condition. Set 0h to the transmission format register.

Example 1 of data read (when data is read from 2h to 4h)

R/W=0 (Write)

Repeated start condition

R/W=1 (Read)

S

0 1 1 0 0 1 0 0 A 0 0 1 0 0 0 0 0 A Sr 0 1 1 0 0 1 0 1 A

Transmission of

slave address

(0110010)

Setting of Setting of

Transmission of

slave address

(0110010)

2h to the

internal

address

pointer

0h to the

trans-

mission

format

register

Data

A

Data

A

Data

A P

Reading of data from

the internal address 2h.

the internal address 3h.

the internal address 4h.

Master to slave

Start condition

Slave to master

S

A

Sr Repeated start condition

P Stop condition

A

Acknowledge signal

27

RV5C387A

2) The second method to reading data from the internal register is to start reading immediately after writing to the

internal address pointer and the transmission format register. Although this method is not based on the I²C bus

standard in a strict sense it still effective to shorten read time to ease load to the master. Set 4h to the

transmission format register when this method is used.

Example 2 of data read (when data is read from internal addresses Eh to 1h).

R/W=0 (Write)

S

0

1

0

1

0

A

1

0

1

0

A

Data

Transmission of

slave address

(0110010)

Setting of Setting of

Reading of data from

the internal address Eh

Eh to the

internal

address

pointer

4h to the

trans-

mission

format

register

Data

A

Data

A

Data

A P

Reading of data from

the internal address Fh.

the internal address 0h.

the internal address 1h.

Master to slave

Start condition

Acknowledge signal

Slave to master

P

Stop condition

S

A

28

RV5C387A

3) The third method to reading data from the internal register is to start reading immediately after writing to the

slave address and the R/W bit. Since the internal address pointer is set to Fh by default as described in 1), this

method is only effective when reading is started from the internal address Fh.

Example 3 of data read (when data is read from internal addresses Fh to 3h).

R/W=1 (Read)

S

0

1

0

1

0

1

A

Data

Transmission of

slave address

(0110010)

Reading of data from

the internal address Fh.

Reading of data from

the internal address 0h.

Data

A

Data

A

Data

A P

Reading of data from

the internal address 1h.

the internal address 2h.

the internal address 3h.

Master to slave

Start condition

Acknowledge signal

Slave to master

P Stop condition

S

A

29

RV5C387A

1.2-6 Data transmission under special condition

The RV5C387A holds the clock tentatively for duration from start condition to stop condition to avoid invalid read or

write clock on carrying clock. When clock is carried during this period, which will be adjusted within approx. 61µs

from stop condition. To prevent invalid read or write clock shall be made during one transmission operation (from

start condition to stop condition). When 0.5 to 1.0 second elapses after start condition any access to the RV5C387A

is automatically released to release tentative hold of the clock, set Fh to the address pointer, and access from the

CPU is forced to be terminated (the same action as made stop condition is received: automatic resume function from

the I²C bus interface). Therefore, one access must be completed within 0.5 seconds. The automatic resume

function prevents delay in clock even if the SCL is stopped from sudden failure of the system during clock read

operation.

Also a second start condition after the first condition and before the stop condition is regarded as the “repeated start

condition.” Therefore, when 0.5 to 1.0 seconds passed after the first start condition, access to the RV5C387A is

automatically released.

If access is tried after automatic resume function is activated, no acknowledge signal will be output for writing while

FFh will be output for reading.

Access to the Real-time Clock

1) No stop condition shall be generated until clock read/write is started and completed.

2) One cycle read/write operation shall be completed within 0.5 seconds.

3) Do not make Start Condition within 61µs from Stop Condition. When clock is carried during the access,

which will be adjusted within approx. 61µs from Stop Condition.

The user shall always be able to access the real-time clock as long as these three conditions are met.

Bad example of reading from seconds to hours (invalid read)

(Start condition) → (Read of seconds) → (Read of minutes) → (Stop condition) → (Start condition) → (Read

of hour) → (Stop condition)

Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to

06:00:00 P.M. At this time second digit is hold so the read as 05:59:59. Then the RV5C387A confirms (Stop

condition) and carries second digit being hold and the time changes to 06:00:00 P.M. Then, when the hour

digit is read, it changes to 6. The wrong results of 06:59:59 will be read.

30

RV5C387A

2. Configuration of Oscillation Circuit and Correction of Time Count Deviations

2.1 Configuration of Oscillating Circuit

RV5C387A

Typical externally-equipped element

X'tal: 32.768kHz

VDD

V^DD

10

9

(R1=30kΩ TYP.)

(CL=6pF to 8pF)

OSCIN

Standard values of internal elements

RF=15MΩ TYP.

CG

32kHz

R^F

8

RD=120kΩ TYP.

OSCOUT

A

RD

CD

CG, CD=12pF TYP.

The oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the VSS pin

input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of 1.2

volts on the positive side of the VSS pin input.

Considerations in Handling Crystal Oscillators

Generally, crystal oscillators have basic characteristics including an equivalent series resistance (R1)

indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center

frequency. Particularly, crystal oscillators intended for use with the RV5C387A are recommended to have a

typical R1 value of 30kΩ and a typical CL value of 6 to 8pF. To confirm these recommended values, contact

the manufacturers of crystal oscillators intended for use with these particular models.

Considerations in Installing Components around the Oscillation Circuit

1) Install the crystal oscillator in the closest possible vicinity to the real-time clock ICs.

2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area

marked “←A→” in the above figure).

3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed

circuit board.

4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.

5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.

Other Relevant Considerations

1) For external input of 32.768-kHz clock pulses to the OSCIN pin:

DC coupling: Prohibited due to an input level mismatch.

AC coupling: Permissible except that the oscillation halt sensing circuit does not guarantee perfect

operation because it may cause sensing errors due to such factors as noise.

2) To maintain stable characteristics of the crystal oscillator, avoid driving any other IC through 32.768-kHz

clock pulses output from the OSCOUT pin.

31

RV5C387A

2.2 Measurement of Oscillation Frequency

RV5C387A

VDD

OSCIN

32.768kHz

OSCOUT

Frequency

counter

32KOUT

VSS

1) The RV5C387A is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin at power-on conditionally on setting the XSTP bit to

1 in the control register 2.

*

2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation fre-

quency of the oscillation circuit.

3) The 32KOUT pin should be connected to the VDD pin with a pull-up resistor.

2.3 Adjustment of Oscillation Frequency

The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of

the RV5C387A in the system into which they are to be built and on the allowable degree of time count errors. The

flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the

relevant system.

Start

YES

Allowable time count precision is on order of oscillation

To Course (A)

To Course (B)

To Course (C)

NO

Use 32-kHz

clock circuit?

frequency variations of crystal oscillator *

¹plus

NO

frequency variations of real-time clock? *²*³

YES

Use 32-kHz clock circuit without regard

to its frequency precision?

NO

YES

NO

Allowable time count precision is on order of oscillation

frequency variations of crystal oscillator *¹plus

frequency variations of real-time clock? *²*³

To Course (D)

1) Generally, crystal oscillators for commercial use are classified in terms of their center frequency depending on their load capacitance (CL) and further

divided into ranks on the order of ±10, ±20, and ±50ppm depending on the degree of their oscillation frequency variations.

2) Basically, the RV5C387A is configured to cause frequency variations on the order of ±5 to ±10ppm at normal temperature.

3) Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics

and other properties of crystal oscillators.

*

32

RV5C387A

Course (A)

When the time count precision of each real-time clock is not to be adjusted, the crystal oscillator intended for use

with that real-time clock may have any CL value requiring no presetting. The crystal oscillator may be subject to

frequency variations which are selectable within the allowable range of time count precision. Several crystal

oscillators and real-time clocks should be used to find the center frequency of the crystal oscillators by the method

described in “2.2 Measurement of Oscillation Frequency” and then calculate an appropriate oscillation adjustment

value by the method described in “2.4 Oscillation Adjustment Circuit” for writing this value to the RV5C387A.

Course (B)

When the time count precision of each real-time clock is to be adjusted within the oscillation frequency variations of

the crystal oscillator plus the frequency variations of the real-time clock ICs, it becomes necessary to correct

deviations in the time count of each real-time clock by the method described in “2.4 Oscillation Adjustment Circuit”.

Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation

frequency variations and their C^Lvalues. The real-time clock IC and the crystal oscillator intended for use with that

real-time clock IC should be used to find the center frequency of the crystal oscillator by the method described in

“2.2 Measurement of Oscillation Frequency” and then confirm the center frequency thus found to fall within the

range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation

circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to

approximately 1.5ppm.

Course (C)

Course (C) together with Course (D) requires adjusting the time count precision of each real-time clock as well as

the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the

crystal oscillator intended for use with the real-time clocks should be adjusted by adjusting the oscillation stabilizing

capacitors C^Gand CD connected to both ends of the crystal oscillator. The RV5C387A, which incorporates the CG

and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value.

Generally, the relationship between the CL value and the CG and CD values can be represented by the following

equation:

CL = ^{CG × CD}+ CS

CG + CD

where “CS” represents the floating capacity of the printed circuit board

The crystal oscillator intended for use with the RV5C387A is recommended to have the CL value on the order of 6 to

8pF. Its oscillation frequency should be measured by the method described in “2.2 Measurement of Oscillation

Frequency”. Any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time

count gain or loss, respectively) should be replaced with another one having a smaller and greater CL value,

respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the

oscillation adjustment circuit (see “2.4 Oscillation Adjustment Circuit”) should be written to the oscillation

adjustment register.

33

RV5C387A

Another advisable way to select a crystal oscillator having an optimum CL value is to contact the manufacturer of the

crystal oscillator intended for use with the RV5C387A.

Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external

oscillation stabilization capacitor CGOUT as illustrated in the diagram below.

1) The CGOUT should have a capacitance ranging from 0 to 15pF.

*

RV5C387A

VDD

V^DD

10

OSCIN

9

CGOUT*¹

CG

CD

32kHz

R^F

8

OSCOUT

RD

Course (D)

It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in the

time count of each real-time clock in the same manner as in Course (B) by the method described in “2.4 Oscillation

Adjustment Circuit”.

2.4 Oscillation Adjustment Circuit

The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the

number of 1-second clock pulses once per 20 seconds. When such oscillation adjustment is not to be made, the

oscillation adjustment circuit can be disabled by writing the settings of “ , 0, 0, 0, 0, 0, ” (“ ” representing “0” or

*

“1”) to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation

adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for

writing to the oscillation adjustment circuit.

2.4-1 When Oscillation Frequency *¹is Higher than Target Frequency *²(There is a Time Count Gain)

(Oscillation frequency – Target frequency + 0.1)

Oscillation adjustment value*³=

Oscillation frequency × 3.051 × 10^–6

.

= (Oscillation frequency – Target frequency) × 10 + 1

1) Oscillation frequency:

2) Target frequency:

Frequency of clock pulses output from the 32KOUT pin at normal temperature in the manner described in “2.2

Measurement of Oscillation Frequency”.

*

Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature characteristics as to have

the highest oscillation frequency at normal temperature. Consequently, the crystal oscillator is recommended to have

target frequency settings on the order of 32.768 to 32.76810kHz (+3.05ppm relative to 32.768kHz). Note that the target

frequency differs depending on the environment or location where the equipment incorporating the real-time clocks is

expected to be operated.

3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the oscillation adjustment register and is represented in 7-bit coded

decimal notation.

*

34

RV5C387A

2.4-2 When Oscillation Frequency is Equal to Target Frequency (There is Neither a Time Count Gain nor

a Time Count Loss)

Writing the oscillation adjustment value setting of “0”, “+1”, “–64”, or “–63” to the oscillation adjustment register

disables the oscillation adjustment circuit.

2.4-3 When Oscillation Frequency is Lower than Target Frequency (There is a Time Count Loss)

(Oscillation frequency – Target frequency)

Oscillation adjustment value*³=

Oscillation frequency × 3.051 × 10^–6

.

= (Oscillation frequency – Target frequency) × 10

Oscillation adjustment value calculations are exemplified below.

(1)For an oscillation frequency of 32768.85Hz and a target frequency of 32768.05Hz:

–6

.

Oscillation adjustment value

=

(32768.85 – 32768.05 + 0.1) / (32768.85

.

×

3.051

×

10 ) = (32768.85 – 32768.05)

×

10 + 1

.

= 9.001 = 9

In this instance, write the settings of “0, 0, 0, 1, 0, 0, 1” to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation

adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain

represents a distance from 01h.

(2)For an oscillation frequency of 32763.95Hz and a target frequency of 32768.05Hz:

Oscillation adjustment value = (32763.95 – 32768.05) / (32763.95

.

× 3.051 × × 10

10^–6) = (32763.95 – 32768.05)

.

= –41.015 = –41

To represent an oscillation adjustment value of –41 in 7-bit coded decimal notation, subtract 41(29h) from

128(80h) to obtain 57h. In this instance, write the settings of “1, 0, 1, 0, 1, 1, 1” in the F6, F5, F4, F3, F2, F1, and F0

bits in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of

any time count loss represents a distance from 80h.

Oscillation adjustment involves an adjustment differential of approximately 1.5ppm from the target frequency

at normal temperature.

Notes

1) Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the 32KOUT

pin.

2) Oscillation adjustment value range: When the oscillation frequency is higher than the target frequency

(causing a time count gain), an appropriate time count gain ranges from –3.05ppm to –189.2ppm with the

settings of “0, 0, 0, 0, 0, 1, 0” to “0, 1, 1, 1, 1, 1, 1” written to the F6, F5, F4, F3, F2, F1, and F0 bits in the

oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm.

Conversely, when the oscillation frequency is lower than the target frequency (causing a time count loss),

an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of “1, 1, 1, 1, 1, 1, 1”

to “1, 0, 0, 0, 0, 1, 0” written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register,

thus allowing correction of a time count loss of up to –189.2ppm.

35

RV5C387A

3. Oscillation Halt Sensing and Supply Voltage Monitoring

The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The

supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or

1.6 volts. For these functions, the real-time clock has two flag bits (ie. the XSTP bit for the former and the VDET bit

for the latter) in which 1 is set once and this setting is maintained until 0 is written.

When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage

monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below.

XSTP

VDET

Conditions of supply voltage and oscillation

No drop in supply voltage below threshold voltage and no halt in oscillation

Drop in supply voltage below threshold voltage and no halt in oscillation

Halt on oscillation

0

1

0

1

*

Threshold voltage (2.1 or 1.6 volts)

Supply voltage

Oscillation by 32.768-kHz clock pulses

Normal voltage detector

Supply voltage monitoring (VDET)

Oscillation halt sensing (XSTP)

Internal initialization Setting XSTP and

Setting VDET bit to 0

Setting XSTP and

VDET bits to 0

period

VDET bits to 0

(1 to 2 seconds)

When the XSTP bit is set to 1 in the control register 2, the F6 to F0, WALE, DALE, CLEN2, 12/24, TEST, CT2, CT1,

CT0, VDSL, VDET, SCRATCH, CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment

register, the control register 1, and the control register 2. The XSTP bit is also set to 1 at power-on from 0 volts. Note

that the XSTP bit may be locked to 0 and the internal register broken upon instantaneous power-down.

36

RV5C387A

Considerations in Using Oscillation Halt Sensing Circuit

Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:

1) Instantaneous power-down on the VDD

2) Condensation on the crystal oscillator

3) On-board noise to the crystal oscillator

4) Applying to individual pins voltage exceeding their respective maximum ratings

In particular, note that the XSTP bit may fail to be set to 1 in the presence of any applied supply voltage as

illustrated below in such events as backup battery installation. Further, give special considerations to prevent

excessive chattering to pewer supply.

VDD

< Supply Voltage Sensing Circuit >

The supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per

second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts for the VDSL bit setting of

0 (the default setting) or 1, respectively, in the control register 2, thus minimizing supply current requirements as

illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the

control register 2

VDD

Threshold voltage

of 2.1 or 1.6 volts

7.8ms

XSTP

Internal initialization period

(1 or 2 seconds)

1s

Sampling operation by supply voltage

monitoring circuit

VDET

(D6 at address Fh)

Setting 0 to XSTP

and VDET bits

Setting VDET bit to 0

37

RV5C387A

4. Alarm and Periodic Interrupt

The RV5C387A incorporates the alarm circuit and the periodic interrupt circuit that are configured to generate

alarm signals and periodic interrupt signals, respectively, for output from the INTRB or INTRC pin as described below.

1) Alarm Circuit

The alarm interrupt circuit is configured to generate alarm signals for output from the INTRB or INTRC, which

is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-

of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers

intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour

and minute digit settings). The Alarm_W is output form the INTRB pin, and the Alarm_D is output from INTRC

pin.

2) Periodic Interrupt Circuit

The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals

in the level mode for output from the INTRA pin depending on the CT², CT1, and CT0 bit settings in the control

register 1.

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the

control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the

control register 1) as listed in the table below.

Flag Bits

Enable Bits

Output Pin

Alarm signals

(under control of Alarm_W registers)

WAFG bit

(D1 at address Fh)

WALE bit

(D7 at address Eh)

INTRB

Alarm signals

(under control of Alarm_D registers)

DALE bit

(D0 at address Fh)

DALE bit

(D6 at address Eh)

INTRC

INTRA

CTFG bit

CT2, CT1, and CT0 bits (D2 to D0 at address Eh)

Periodic interrupt signals

(D2 of Internal Address Fh) (these bit settings of 0 disable the periodic interrupt circuit)

· At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the control register 1, the INTRA,

INTRB or INTRC pin is driven high (disabled).

38

RV5C387A

4.1 Alarm Interrupt

The alarm circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the control register 1) and the

flag bits (i.e. the WAFG and DAFG bits in the control register 2). The enable bits can be used to enable this circuit

when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm

interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high

(disable) the alarm circuit when set to 0.

The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm circuit will

continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and

preset alarm time.

The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W registers for the

day-of-week digit settings and both the Alarm_W registers and the Alarm_D registers for the hour and minute digit

settings) with the WALE and DALE bits once set to 0 and then to 1 in the control register 1. Note that the WALE

and DALE bits should be once set to 0 in order to disable the alarm circuit upon the coincidental occurrence of a

match between current time and preset alarm time in the process of setting the alarm function.

Interval (1 minute) during which

a match between current time

and preset alarm time occurs

MAX.61.1µs

INTRB or INTRC pin

Match between

Setting WALE

and DALE

bit to 1

Setting WALE Setting WALE

Setting WALE

and DALE

bit to 0

current time and

preset alarm time

in the day-of-week

and hour settings

current time and

preset alarm time

in the day-of- week

and hour settings

and DALE

bit to 0

and DALE

bit to 1

INTRB or INTRC pin

Match between

Setting WALE

and DALE

bit to 1

Setting WAFG

and DAFG

bit to 0

current time and

preset alarm time

in the day-of-week

and hour settings

current time and

preset alarm time

in the day-of- week

and hour settings

39

RV5C387A

4.2 Periodic Interrupt

Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform

modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the

level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is set to high (OFF).

Waveform Mode, Cycle and Falling Timing

Description

CT2

CT1

CT0

Waveform Mode

Interrupt Cycle and Fall Timing

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

Off (“H”)

(Default setting)

—

Fixed at low (“L”)

1

Pulse Mode

*

2Hz (Duty cycle of 50%)

1

1Hz (Duty cycle of 50%)

2

Level Mode

*

Once per 1 second (Synchronized with second counter increment)

Once per minute (at 00 seconds of every minute)

Once per hour (at 00 minutes and 00 seconds of every hour)

Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)

*

1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter

as illustrated in the timing chart on the next page.

2) Level Mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1

hour, and 1 month. The increment of the second counter is synchronized with the falling edge of

periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of

1 second are output in synchronization with the increment of the second counter as illustrated in

the timing chart on the next page.

3) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 seconds as follows:

Pulse Mode: the “L” period of output pulses will increment or decrement by a maximum of 3.784ms.

For example, 1-Hz clock pulses will have a duty cycle of 50 0.3784%

Level Mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784ms.

40

RV5C387A

Relation Between the Mode Waveform and the CTFG Bit

• Pulse Mode

CTFG bit

INTRA pin

Approx. 92µs

Rewriting of the second counter

(Increment of second counter)

)

In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time

readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.

*

• Level Mode

CTFG bit

INTRA pin

Setting CTFG bit to 0

(Increment of

second counter)

(Increment of

second counter)

(Increment of

second counter)

5. 32-kHz Clock Output

32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the control register 2 or the

CLEN2 bit in the control register 1 is set to 0. If the conditions described above are not satisfied, the output is set to

high.

CLEN1

CLEN2

32KOUT pin output

(D3 at Address Fh)

(D4 at Address Eh)

(Nch Open Drain output)

1

OFF(“H”)

0 (Default)

*

Clock pulses

0 (Default)

*

The 32KOUT pin output is synchronized with the CLEN1, CLEN2 bit, settings as illustrated in the timing chart

below.

CLEN1 or CLEN2

32KOUT pin

MAX. 61.0µs

MAX. 45.8µs

41

RV5C387A

6. Typical Applications

6.1 Typical Power Circuit Configurations

Sample circuit configuration 1

RV5C387A

1) Install bypass capacitors for high-frequency and low-

frequency applications in parallel in close vicinity to the

RV5C387A .

*

OSCIN

System power supply

32.768kHz

OSCOUT

VDD

1

*

VSS

Sample circuit configuration 2

RV5C387A

1) Connection in the example shown left may not affect the

RV5C387A since it is designed to be operational even

when the pin voltage exceeds VDD.

*

OSCIN

System power supply

32.768kHz

OSCOUT

VDD

1

*

VSS

42

RV5C387A

6.2 Connection of INTRA, INTRB or INTRC Pin

The INTRA, INTRB or INTRC pin follows the N-channel open drain output logic and contains no protective diode on

the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply

voltage.

System power supply

RV5C387A

1) Depending on whether the INTRA, INTRB or INTRC pin is to be

*

A

used during battery backup, it should be connected to a pull-up

1

INTRA or INTRB or INTRC

*

B

resistor at the following different positions:

1) Position A in the left diagram when it is not to be used during

battery backup.

OSCIN

Backup power supply

32.768kHz

2) Position B in the left diagram when it is to be used during

battery backup.

OSCOUT

VDD

VSS

6.3 Connection of 32KOUT Pin

The 32KOUT pin follows the Nch. open drain output and contains no protective diode on the power supply side. As

such, it can be connected to a device with a supply voltage of up to 5.5 volts regardless of supply voltage, provided

that such connection involves considerations for the supply current requirements of a pull-up resistor, which can be

roughly calculated by the following equation:

I=0.5×(VDD or VCC)/Rp

RV5C387A

System power supply (VCC)

1) Depending on whether the 32KOUT pin is to be used during

*

battery backup, it should be connected to a pull-up resistor at

Rp

A

the following different positions:

1

32KOUT

OSCIN

*

1) Position A in the left diagram when it is not to be used during

battery backup.

B

Backup battery

(VDD)

2) Position B in the left diagram when it is to be used during

battery backup.

32.768kHz

OSCOUT

VDD

VSS

43

RV5C387A

7. Typical Characteristics

• Test Circuit

RV5C387A

X'tal: 32.768kHz

(R1=30kΩ TYP.)

(CL=6pF to 8pF)

Topt : 25˚C

VDD

OSCIN

32.768kHz

Output Pins: open

OSCOUT

Frequency

counter

32KOUT

VSS

7.2 Timekeeping Current vs. Supply Voltage

(with 32-kHz clock output)

7.1 Timekeeping Current vs. Supply Voltage

(with no 32-kHz clock output)

(SCL=SDA=“H”,

Output=Open, Topt=25˚C)

(SCL=SDA=“H”,

Output=Open, Topt=25˚C)

1

2

0.8

0.6

0.4

0.2

0

1.5

1

0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Supply Voltage VDD(V)

7.4 Timekeeping Current vs. Operating Temperature

(with no 32-kHz clock output)

7.3 CPU Access Current vs. SCLK Clock Frequency

(Output=Open)

(Output=Open, Topt=25˚C)

20

2

15

10

1.5

1

VDD=5V

VDD=3V

5

0

0.5

0

100

200

300

400

500

–60 –40 –20

0

20 40 60 80 100

SCL Clock Frequency (kHz)

Operating Temperature Topt(˚C)

44

RV5C387A

7.5 Oscillation Frequency Deviation vs. External C

G

7.6 Oscillation Frequency Deviation vs. Supply Voltage

(VDD=3V, Topt=25˚C,

External CG=0pF as standard)

(Topt=25˚C, VDD=3V as standard)

5

10

4

3

5

0

–5

2

–10

1

–15

–20

–25

–30

–35

–40

0

–1

–2

–3

–4

–5

0

5

10

15

20

0

1

2

3

4

5

6

External CG(pF)

Supply Voltage VDD(V)

7.7 Oscillation Frequency Deviation vs.

Operating Temperature

7.8 Oscillation Start Time vs. Supply Voltage

(Topt=25˚C, VDD=3V as standard)

(Topt=25˚C)

500

20

0

400

300

200

100

0

–20

–40

–60

–80

–100

–120

–140

–60 –40 –20

0

20 40 60 80 100

0

1

2

3

4

5

6

Temperature Topt(˚C)

Supply Voltage VDD(V)

7.9 V^OLvs. IOL

7.10 VOL vs. IOL

(32KOUT Pin)

(INTRA, INTRB, INTRC Pin)

(Topt=25˚C)

30

10

8

25

20

15

6

VDD=5V

4

VDD=3V

VDD=5V

10

5

VDD=3V

2

0

0.2

0.4

0.6

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

VOL (V)

45

RV5C387A

8. Typical Software-based Operations

8.1 Initialization at Power-on

Start

1

*

Power-on

2

NO

*

XSTP=1?

YES

4

3

*

NO

VDET=0?

Set Oscillation Adjustment Register

and Control Registers 1 and 2, etc.

YES

Warning of Backup Battery

Run-down

1) After power-on from 0 volts, the start of oscillation and the process of internal initialization require a time span on the order of 1 to 2 seconds, so that

access should be done after the lapse of this time span or more.

*

2) The XSTP bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0 volt. The XSTP bit may fail to be set to 1 in the

presence of any excessive chattering in power supply in such events as installing backup battery. Should there be any possibility of this failure occurring,

it is recommended to initialize the RV5C387A regardless of the current XSTP bit setting. For further details, see “3. Oscillation Halt Sensing and Supply

Voltage Monitoring”.

3) This step is not required when the supply voltage monitoring circuit is not used.

*

4) This step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings.

8.2 Writing of Time and Calendar Data

1) When writing to clock and calendar counters, do not insert stop condition

until all times from second to year have been written to prevent error in

writing time. (Detailed in “1.2-6 Data transmission under special

condition”.

*

1

Start condition

*

2) Any writing to the second counter will reset divider units lower than the

second digits.

*

Write to clock and

calendar counters

2

3) Take care so that process from start condition to stop condition will be

complete within 0.5sec. (Detailed in “1.2-6 Data transmission under

special condition”.

*

The RV5C387A may also be initialized not at power-on but in the process

of writing time and calendar data.

Stop condition

3

*

46

RV5C387A

8.3 Reading Time and Calendar Data

8.3-1 Ordinary Process of Reading Time and Calendar Data

1) When reading from clock and calendar counters, do not insert stop

condition until all times from second to year have been read to prevent

error in reading time. (Detailed in “1.2-6 Data transmission under special

condition”.

*

Start condition

1

*

2) Take care so that process from start condition to stop condition will be

complete within 0.5sec. (Detailed in “1.2-6 Data transmission under

special condition”.

*

Read from clock and

calendar counters

Stop condition

2

*

8.3-2 Basic Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt

1) This step is intended to select the level mode as a waveform mode for the

*

Set Periodic Interrupt

Cycle Selection Bits

periodic interrupt function.

1

*

2) This step must be completed within 0.5 second.

3) This step is intended to set the CTFG bit to 0 in the Control Register 2 to

cancel an interrupt to the CPU.

*

Generate Interrupt in CPU

NO

CTFG=1?

YES

Read from Time Counter

and Calendar Counter

Other Interrupt

Processes

2

*

Write “×,1,×,1,×,0,1,1”

to Control Register 2

3

*

47

RV5C387A

8.3-3 Applied Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt

Time data need not be read from all the time counters when used for such ordinary purposes as time count

indication. This applied process can be used to read time and calendar data with substantial reductions in the load

involved in such reading.

For Time Indication in “Day-of-month, Day-of-week, Hour,

Minute, and Second” Format:

Write “×,×,×,×,0,1,0,0”

to Control Register 1

Write “×,1,×,1,×,0,1,1”

to Control Register 2

1

*

Generate Interrupt to CPU

NO

CTFG=1?

YES

2

NO

*

Other Interrupt

Processes

Second Digit = 00?

YES

3

*

Use Previous Minute,

Hour, Day-of-week,

Read Minute, Hour, Day-of-week,

and Day-of-month Counters

and Day-of-month Data

4

Write “×,1,×,1,×,0,1,1”

to Control Register 2

*

1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function.

2) This step must be completed within 0.5sec.

*

3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data.

4) This step is intended to set the CTFG bit to 0 in the control register 2 to cancel an interrupt to the CPU.

48

RV5C387A

8.4 Interrupt Process

8.4-1 Periodic Interrupt

1) This step is intended to select the level mode as a waveform mode for the

periodic interrupt function.

Set Periodic Interrupt

Cycle Selection Bits

*

1

*

2) This step is intended to set the CTFG bit to 0 in the control register 2 to

cancel an interrupt to the CPU.

Generate Interrupt to CPU

NO

CTFG=1?

YES

Periodic Interrupt Process

Other Interrupt

Processes

2

Write “×,1,×,1,×,0,1,1”

to Control Register 2

*

8.4-2 Alarm Interrupt

1) This step is intended to once disable the alarm interrupt circuit by setting

the WALE and DALE bits to 0 in anticipation of the coincidental occurrence

of a match between current time and preset alarm time in the process of

setting the alarm interrupt function.

1

*

WALE or DALE=0

*

Set Alarm Minute, Hour,

and Day-of-week Registers

2) This step is intended to enable the alarm interrupt function after completion

of all alarm interrupt settings.

*

3) This step is intended to once cancel the alarm interrupt function by writing

the settings of “×,1,×,1,×,1,0,1” and “×,1,×,1,×,1,1,0” to the Alarm_W

registers and the Alarm_D registers, respectively.

2

WALE or DALE=1

*

Generate Interrupt to CPU

NO

WAFG or DAFG=1?

YES

Conduct Alarm Interrupt

Other Interrupt

Processes

Write “

to Control Register 2

×,1,×,1,×,1,0,1”

3

*

49

RV5C387A

PACKAGE DIMENSIONS(Unit : mm)

• RV5C387A (10-pin SSOP-G)

0° to 10°

+0.3

2.9

-

0.1

10

6

+0.1

5

1

0.127

-

0.05

0.5

0.1

0.2±0.1

M

0.15

TAPING SPECIFICATION(Unit : mm)

• RV5C387A (10-pin SSOP-10G)

The RV5C387A has one designated taping direction. The product designation for the taping components is

“RV5C387A-E2”.

+0.1

–0

4.0±0.1

ø1.5

0.3

2.0±0.05

4.4

8.0±0.1

2.0MAX.

User Direction of Feed

50

RICOH COMPANY, LTD.

ELECTRONIC DEVICES DIVISION

HEADQUARTERS

13-1, Himemuro-cho, Ikeda City, Osaka 563-8501, JAPAN

Phone +81-727-53-6003 Fax +81-727-53-2120

YOKOHAMA OFFICE (International Sales)

3-2-3, Shin-Yokohama, Kohoku-ku, Yokohama City, Kanagawa 222-8530,

JAPAN

Phone +81-45-477-1697 Fax +81-45-477-1694 · 1695

http://www.ricoh.co.jp/LSI/english/

RICOH CORPORATION

ELECTRONIC DEVICES DIVISION

SAN JOSE OFFICE

1996 Lundy Avenue, San Jose, CA 95131, U.S.A.

Phone +1-408-944-3306 Fax +1-408-432-8375

http://www.ricoh-usa.com/semicond.htm


型号：	RV5C387A-F
厂家：	RICOH ELECTRONICS DEVICES DIVISION
描述：	Real Time Clock, 0 Timer(s), CMOS, PDSO10, 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10 时钟 ISM频段光电二极管外围集成电路
文件：	总54页 (文件大小：419K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RV5C387A-F [RICOH]

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