5962-8957401EA [ROCHESTER]
ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16, 0.300 INCH, CERAMIC, DIP-16;
| 型号： | 5962-8957401EA |
| 厂家： | 
Rochester Electronics |
| 描述： | ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16, 0.300 INCH, CERAMIC, DIP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
SN54ALS165 . . . J PACKAGE
SN74ALS165 . . . D OR N PACKAGE
(TOP VIEW)
• Complementary Outputs
• Direct Overriding Load (Data) Inputs
• Gated Clock Inputs
SH/LD
V
CC
• Parallel-to-Serial Data Conversion
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
E
CLK INH
D
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
F
C
G
B
H
A
Q
SER
description
H
GND
Q
H
The ′ALS165 are parallel-load 8-bit serial shift
registers that, when clocked, shift the data toward
serial (Q and Q ) outputs. Parallel-in access to
SN54ALS165 . . . FK PACKAGE
(TOP VIEW)
H
H
each stage is provided by eight individual direct
data (A–H) inputs that are enabled by a low level
at the shift/load (SH/LD) input. The ′ALS165 have
a clock-inhibit function and complemented serial
outputs.
3
2
1
20 19
18
E
F
D
4
5
6
7
8
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD is
held high and the clock inhibit (CLK INH) input is
held low. The functions of CLK and CLK INH are
interchangeable. Since a low CLK and a
low-to-high transition of CLK INH also
accomplishes clocking, CLK INH should be
changed to the high level only while CLK is high.
Parallel loading is inhibited when SH/LD is held
high. The parallel inputs to the register are
enabled while SH/LD is low independently of the
levels of the CLK, CLK INH, or serial (SER) inputs.
17
16
15
14
C
NC
G
NC
B
H
A
9 10 11 12 13
NC – No internal connection
The SN54ALS165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS165 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
FUNCTION
CLK CLK INH
SH/LD
L
X
H
X
L
X
X
H
↑
Parallel load
No change
No change
H
H
H
H
†
Shift
Shift
†
↑
L
†
Shift = content of each internal register shifts
toward serial outputs. Data at SER is shifted
into first register.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
†
logic symbol
SRG8
1
C1 [LOAD]
SH/LD
15
CLK INH
2
≥1
C2/
CLK
10
SER
11
A
2D
1D
1D
12
B
13
C
14
D
3
E
4
F
5
G
6
9
7
Q
Q
H
1D
H
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
1
SH/LD
15
CLK INH
2
CLK
SER
9
7
S
S
S
S
S
S
S
S
Q
Q
H
H
C1
C1
C1
C1
C1
C1
C1
C1
10
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
Data
Inputs
L
D
E
F
H
L
H
H
G
H
L
L
L
Q
H
H
L
H
L
H
L
H
L
H
L
Q
H
H
H
H
Inhibit
Serial Shift
Load
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
recommended operating conditions
SN54ALS165
MIN NOM MAX
SN74ALS165
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
14
14
15
15
11
35
0
11
11
12
11
10
10
10
4
45
CLK high
CLK low
CLK low
t
Pulse duration, CLK (see Figure 1)
ns
w(CLK)
t
t
t
t
t
t
Pulse duration, SH/LD low
ns
ns
ns
ns
ns
ns
°C
w(load)
su1
su2
su3
su4
h
Setup time, clock enable (see Figure 1)
Setup time, parallel input (see Figure 1)
Setup time, serial input (see Figure 2)
Setup time, shift (see Figure 2)
Hold time at any input
11
15
4
T
A
Operating free-air temperature
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS165
SN74ALS165
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
20
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.1
–112
24
–0.1
–112
24
mA
mA
mA
‡
V
O
= 2.25 V
–20
–30
O
See Note 1
12
12
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
is measured first with the parallel inputs at
NOTE 1: With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, I
4.5 V, then with the parallel inputs grounded.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
switching characteristics (see Figures 1, 2, and 3)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
†
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54ALS165 SN74ALS165
MIN
35
4
MAX
MIN
45
4
MAX
f
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
23
23
14
15
14
18
17
17
20
22
13
14
13
16
15
16
Any
Any
SH/LD
CLK
4
4
3
3
ns
ns
ns
3
3
3
3
Q
H
H
H
3
3
2
2
Q
H
3
3
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PARAMETER MEASUREMENT INFORMATION
3.5 V
(disable while
clock is high)
CLK INH
CLK
V
ref
0.3 V
t
su1
3.5 V
V
ref
V
ref
V
ref
0.3 V
t
t
t
w(CLK)
su2
w(CLK)
F and H
Inputs
(see Notes
A and B)
3.5 V
0.3 V
V
ref
V
V
V
ref
ref
ref
t
su2
t
w(load)
t
w(load)
3.5 V
0.3 V
SH/LD
V
V
V
ref
V
ref
ref
ref
t
t
t
t
t
t
PHL
PLH
PHL
PLH
PHL
PLH
V
OH
OL
OH
OL
Output
V
V
V
V
V
ref
ref
ref
ref
ref
Q
H
V
t
t
t
t
t
PHL
PHL
PLH
PHL
PLH
t
PLH
Output
V
V
ref
V
ref
V
ref
V
ref
V
ref
V
ref
Q
H
V
NOTES: A. The remaining six data inputs and SER are low.
B. Prior to test, high-level data is loaded into the H input.
C. The input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, t = t = 2 ns.
r
f
D.
V
ref
= 1.3 V
Figure 1. Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS165, SN74ALS165
PARALLEL-LOAD 8-BIT REGISTERS
SDAS157B – JUNE 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
3.5 V
0.3 V
V
ref
SH/LD
t
su4
3.5 V
0.3 V
SER
CLK
V
ref
t
t
su3
su3
3.5 V
0.3 V
V
V
ref
ref
t
n
NOTES: A. The eight data inputs and CLK INH are low. Results are monitored at Q at t
.
H
n + 7
B. The input pulse generators have the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t = t = 2 ns.
r
f
C.
V
ref
= 1.3 V
Figure 2. Voltage Waveforms
From Output
Under Test
Test
Point
C
L
R
L
(see Note A)
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Load Circuit for Switching Tests
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
1 of 2
Products
Development Tools
Applications
Search
FEATURES | DESCRIPTION | DATASHEETS |
PRICING/AVAILABILITY | APPLICATION NOTES |
RELATED DOCUMENTS
PRODUCT FOLDER PRODUCT INFO:
|
PRODUCT SUPPORT: TRAINING
SN54ALS165, Parallel-Load 8-Bit Registers
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54ALS165
Voltage Nodes (V) 5
Vcc range (V)
Input Level
Output Level
Output
4.5 to 5.5
TTL
TTL
2S
FEATURES
Back to Top
Complementary Outputs
l
l Direct Overriding Load (Data) Inputs
l Gated Clock Inputs
l Parallel-to-Serial Data Conversion
l Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
DESCRIPTION
Back to Top
The 'ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data
toward serial (Q and Q\ ) outputs. Parallel-in access to each stage is provided by eight
H
H
individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD\)
input. The 'ALS165 have a clock-inhibit function and complemented serial outputs.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is
held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH
are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also
accomplishes clocking, CLK INH should be changed to the high level only while CLK is high.
Parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are
enabled while SH/LD\ is low independently of the levels of the CLK, CLK INH, or serial (SER)
inputs.
2 of 2
The SN54ALS165 is characterized for operation over the full military temperature range of -
55°C to 125°C. The SN74ALS165 is characterized for operation from 0°C to 70°C.
TECHNICAL DOCUMENTS
Back to Top
To view the following documents, Acrobat Reader 3.x is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
DATASHEET
Back to Top
Full datasheet in Acrobat PDF: sdas157b.pdf (114 KB) (
)
Updated: 12/01/1994
Full datasheet in Zipped PostScript: sdas157b.psz (102 KB)
APPLICATION NOTES
Back to Top
View Application Reports for Digital Logic
l Advanced Schottky (ALS and AS) Logic Families (SDAA010 - Updated: 08/01/1995)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive
l
Outputs (SCBA012A -
)
Updated: 08/01/1997
Designing With Logic (SDYA009C -
)
Updated: 06/01/1997
l
l Input and Output Characteristics of Digital Integrated Circuits (SDYA010 -
Updated:
)
10/01/1996
l Live Insertion (SDYA012 -
)
Updated: 10/01/1996
RELATED DOCUMENTS
Back to Top
l Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB -
Updated:
)
05/06/1999
l Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB -
)
Updated: 04/17/2000
l MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000)
More Power In Less Space - Technical Article (SCAU001A, 850 KB -
)
l
Updated: 03/01/1996
PRICING/AVAILABILITY
Back to Top
BUDGETARY
PRICE
US$/UNIT
QTY=1000+
ORDERABLE
TEMP
(ºC)
PACK
QTY
DSCC
NUMBER
PACKAGE PINS
STATUS
PRICING/AVAILABILITY
DEVICE
-55
TO
125
5962-
89574012A
SNJ54ALS165FK
SNJ54ALS165J
SNJ54ALS165W
FK
J
20
16
16
ACTIVE
ACTIVE
ACTIVE
9.87
6.44
8.94
165
1
Check stock or order
Check stock or order
Check stock or order
-55
TO
125
5962-
8957401EA
-55
TO
125
5962-
8957401FA
W
1
Table Data Updated on: 11/19/2000
© Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy
| Important Notice
相关型号：
5962-8957401EX
ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16, 0.300 INCH, CERAMIC, DIP-16
TI
5962-8957401FA
Parallel In Serial Out, ALS Series, 8-Bit, Right Direction, Complementary Output, TTL, CDFP16
WEDC
©2020 ICPDF网 联系我们和版权申明