74ABT2244CSJX [ROCHESTER]
ABT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20;
| 型号： | 74ABT2244CSJX |
| 厂家： | 
Rochester Electronics |
| 描述： | ABT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总11页 (文件大小：967K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2007
74ABT2244
tm
Octal Buffer/Line Driver with 25Ω Series Resistors
in the Outputs
Features
General Description
■ Guaranteed latchup protection
The ABT2244 is an octal buffer and line driver designed
to drive the capacitive inputs of MOS memory drivers,
address drivers, clock drivers, and bus-oriented trans-
mitters/receivers.
■ High-impedance, glitch-free bus loading during entire
power up and power down cycle
■ Nondestructive, hot-insertion capability
The 25Ω series resistors in the outputs reduce ringing
and eliminate the need for external resistors.
Ordering Information
Package
Order Number
74ABT2244CSC
74ABT2244CSJ
74ABT2244CMSA
74ABT2244CMTC
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
M20D
MSA20
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Schematic of Each Output
Pin Descriptions
Truth Table
Pin Names
Description
OE , OE
Output Enable Input (Active LOW)
OE
I
O
OE
I
O
4–7
1
2
1
0–3
0–3
2
4–7
I –I
Inputs
0
7
H
L
L
X
Z
H
L
L
X
Z
O –O
Outputs
0
7
H
H
L
H
H
L
L
L
H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
T
Storage Temperature
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
STG
T
Ambient Temperature Under Bias
Junction Temperature Under Bias
A
T
J
V
V
Pin Potential to Ground Pin
CC
CC
(1)
V
Input Voltage
Input Current
IN
IN
(1)
I
V
Voltage Applied to Any Output
O
–0.5V to 5.5V
Disabled or Power-off State
–0.5V to V
CC
HIGH State
Current Applied to Output in LOW State (Max.)
DC Latchup Source Current (Across Comm Operating Range)
Over Voltage Latchup (I/O)
twice the rated I (mA)
OL
–300mA
10V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
T
Free Air Ambient Temperature
Supply Voltage
–40°C to +85°C
A
V
+4.5V to +5.5V
CC
∆V / ∆t
Minimum Input Edge Rate
Data Input
50mV/ns
20mV/ns
Enable Input
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
2
DC Electrical Characteristics
V
Symbol
Parameter
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min. Typ. Max. Units
CC
V
Input HIGH Voltage
2.0
V
V
V
V
IH
V
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
V
V
Min.
Min.
I
I
I
I
= –18mA
= –3mA
–1.2
CD
OH
IN
2.5
2.0
OH
OH
OL
= –32mA
= 15mA
V
Output LOW Voltage
Input HIGH Current
Min.
0.8
1
V
OL
(3)
I
Max.
V
V
V
= 2.7V
µA
IH
IN
IN
IN
= V
1
CC
I
Input HIGH Current Breakdown
Test
Max.
Max.
= 7.0V
7
µA
µA
BVI
(3)
I
Input LOW Current
V
V
I
= 0.5V
–1
–1
IL
IN
IN
= 0.0V
V
Input Leakage Test
0.0
= 1.9µA, All Other Pins
475
V
ID
ID
Grounded
I
Output Leakage Current
0–5.5V
V
V
V
V
V
= 2.7V; OEn = 2.0V
10
–10
–275
50
µA
OZH
OUT
OUT
OUT
OUT
OUT
I
= 0.5V; OEn = 2.0V
= 0.0V
OZL
I
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Max.
Max.
0.0
–100
mA
µA
µA
µA
mA
µA
OS
I
= V
CEX
CC
I
= 5.5V, All Others GND
100
50
ZZ
I
Power Supply Current
Max. All Outputs HIGH
All Outputs LOW
CCH
I
I
30
CCL
Power Supply Current
Max. OEn = V , All Others at V
CC
50
CCZ
CC
or GND
I
I
Additional
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
Max. V = V – 2.1V
2.5
2.5
50
mA
mA
µA
CCT
I
CC
I
CC
Enable Input V = V – 2.1V
I
CC
Data Input V = V – 2.1V,
I
CC
All Others at V or GND
CC
(3)
Dynamic I No Load
Max. Outputs OPEN, OEn = GND(2)
,
0.1
mA/
MHz
CCD
CC
One-Bit Toggling,
50% Duty Cycle
Notes:
1. Either voltage limit or current limit is sufficient to protect inputs.
2. For 8-bit toggling, I < 0.8mA/MHz.
CCD
3. Guaranteed, but not tested.
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
3
AC Electrical Characteristics
SOIC and SSOP packages.
T = +25°C,
T = –40°C to +85°C,
A
A
V
= +5V,
V
= 4.5V–5.5V,
CC
CC
C = 50pF
C = 50pF
L
L
Symbol
Parameter
Min.
1.0
1.0
1.5
2.1
1.7
1.7
Typ.
2.2
2.9
3.7
4.3
3.5
3.7
Max.
3.9
Min.
1.0
1.0
1.5
2.1
1.7
1.7
Max.
3.9
Units
t
t
Propagation Delay,
Data to Outputs
ns
PLH
PHL
PZH
4.4
4.4
t
Output Enable Time
6.0
6.0
ns
ns
t
7.0
7.0
PZL
PHZ
t
Output Disable Time
5.8
5.8
t
5.8
5.8
PLZ
Capacitance
Conditions
(T = 25°C)
Symbol
Parameter
Typ.
Units
A
C
C
Input Capacitance
V
V
= 0V
5.0
9.0
pF
pF
IN
CC
(4)
Output Capacitance
= 5.0V
OUT
CC
Note:
4. C
is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.
OUT
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
4
AC Loading
*Includes jig and probe capacitance
Figure 2.Test Input Signal Levels
Figure 1. Standard AC Test Load
t
t
t
f
Amplitude
Rep. Rate
w
r
3.0V
1MHz
500ns
2.5ns
2.5ns
Figure 3.Test Input Signal Requirements
AC Waveforms
Figure 4. Propagation Delay Waveforms for
Figure 5. 3-STATE Output HIGH and LOW Enable
and Disable Times
Inverting and Non-Inverting Functions
Figure 6. Propagation Delay, Pulse Width Waveforms
Figure 7. Setup Time, Hold Time
and Recovery Time Waveforms
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
5
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
6
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
7
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
9
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1992 Fairchild Semiconductor Corporation
74ABT2244 Rev. 1.4
www.fairchildsemi.com
10
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