74ACT245SC_NL [ROCHESTER]
ACT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20;
| 型号： | 74ACT245SC_NL |
| 厂家： | 
Rochester Electronics |
| 描述： | ACT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总13页 (文件大小：1066K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74AC245, 74ACT245
Octal Bidirectional Transceiver with 3-STATE
Inputs/Outputs
Features
General Description
■ I and I reduced by 50%
The AC/ACT245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for
bus-oriented applications. Current sinking capability is
24mA at both the A and B ports. The Transmit/Receive
(T/R) input determines the direction of data flow through
the bidirectional transceiver. Transmit (active-HIGH)
enables data from A ports to B ports; Receive (active-
LOW) enables data from B ports to A ports. The Output
Enable input, when HIGH, disables both A and B ports
by placing them in a HIGH Z condition.
CC
OZ
■ Non-inverting buffers
■ Bidirectional data path
■ A and B outputs source/sink 24mA
■ ACT245 has TTL-compatible inputs
Ordering Information
Package
Order Number
74AC245SC
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC245SJ
M20D
74AC245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74AC245PC
N20A
M20B
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT245SC
74ACT245SJ
74ACT245MSA
74ACT245MTC
M20D
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin
Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A –A
Side A 3-STATE Inputs or 3-STATE
Outputs
0
7
B –B
Side B 3-STATE Inputs or 3-STATE
Outputs
0
7
Truth Table
Inputs
OE
L
T/R
Outputs
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
−0.5V to +7.0V
CC
IK
DC Input Diode Current
V = −0.5V
−20mA
+20mA
I
V = V + 0.5
I
CC
V
DC Input Voltage
−0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= −0.5V
−20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
−0.5V to V + 0.5V
O
CC
I
±50mA
±50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
−65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
AC
CC
2.0V to 6.0V
4.5V to 5.5V
ACT
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
−40°C to +85°C
A
∆V / ∆t
Minimum Input Edge Rate, AC Devices:
from 30% to 70% of V , V @ 3.3V, 4.5V, 5.5V
125mV/ns
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
3
DC Electrical Characteristics for AC
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
3.0
V
= 0.1V or
OUT
1.5
2.1
2.1
V
IH
V
– 0.1V
CC
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
– 0.1V
V
V
IL
OUT
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
5.5
V
= V or V ,
0.36
0.36
±0.1
0.44
0.44
±1.0
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(2)
I
Maximum Input
Leakage Current
V = V , GND
µA
IN
I
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65V Max.
= 3.85V Min.
75
mA
mA
µA
OLD
OLD
(3)
I
−75
40.0
OHD
(2)
OHD
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
I
Maximum I/O
5.5
V (OE) = V , V ;
±0.3
±3.0
µA
OZT
I
IL IH
Leakage Current
V = V , GND;
I CC
V
= V , GND
CC
O
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
4
DC Electrical Characteristics for ACT
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
4.5
V
= 0.1V or
OUT
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
IH
V
− 0.1V
CC
5.5
4.5
5.5
4.5
5.5
4.5
V
Maximum LOW
Level Input Voltage
V
V
= 0.1V or
− 0.1V
1.5
V
V
IL
OUT
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= −50µA
4.49
5.49
OH
OUT
V
= V or V ,
3.86
3.76
IN
IL
IH
I
= −24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(4)
I
I
= −24mA
OH
V
Maximum LOW
4.5
5.5
4.5
= 50µA
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
Level Output Voltage
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 24mA
OL
5.5
5.5
V
= V or V ,
0.36
0.44
IN
IL
IH
(4)
I
= 24mA
OL
I
Maximum Input
Leakage Current
V = V , GND
±0.1
±1.0
µA
IN
I
CC
I
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V − 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OHD
(5)
Output Current
I
= 3.85V Min.
−75
40.0
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
I
Maximum I/O
5.5
V (OE) = V , V ;
±0.3
±3.0
µA
OZT
I
IL IH
Leakage Current
V = V , GND;
I CC
V
= V , GND
CC
O
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
5
AC Electrical Characteristics for AC
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(6)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
9.0
Units
CC
t
Propagation Delay,
3.3
1.5
1.5
1.5
1.5
2.5
1.5
2.5
1.5
2.0
1.5
2.0
1.5
5.0
3.5
5.0
3.5
7.0
5.0
7.5
5.5
6.5
5.5
7.0
5.5
8.5
6.5
1.0
1.0
1.0
1.0
2.0
1.0
2.0
1.0
1.0
1.0
1.5
1.0
ns
PLH
PHL
PZH
A to B or B to A
n
n
n
n
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
7.0
t
Propagation Delay,
A to B or B to A
n
8.5
9.0
ns
ns
ns
ns
ns
n
n
n
6.0
7.0
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
11.5
8.5
12.5
9.0
t
12.0
9.0
13.5
9.5
PZL
t
12.0
9.0
12.5
10.0
13.0
10.0
PHZ
t
11.5
9.0
PLZ
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics for ACT
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(7)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
t
Propagation Delay,
5.0
1.5
4.0
7.5
1.5
8.0
ns
PLH
PHL
PZH
A to B or B to A
n
n
n
n
t
Propagation Delay,
A to B or B to A
n
5.0
1.5
4.0
8.0
1.0
9.0
ns
n
n
n
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
1.5
1.5
1.5
2.0
5.0
5.5
5.5
5.0
10.0
10.0
10.0
10.0
1.5
1.5
1.0
1.5
11.0
12.0
11.0
11.0
ns
ns
ns
ns
t
PZL
PHZ
t
t
PLZ
Note:
7. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Conditions
Typ.
4.5
Units
C
Input Capacitance
V
= OPEN
pF
pF
pF
IN
I/O
PD
CC
CC
CC
C
C
Input/Output Capacitance
V
V
= 5.0V
= 5.0V
15.0
45.0
Power Dissipation Capacitance
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
6
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.65
0.51
0.35
1.27
PIN ONE
INDICATOR
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
7
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
9
Physical Dimensions (Continued)
26.92
24.89
PIN #1
7.11
6.09
3.43
3.17
5.33 MAX
(0.97)
1.78
7.87
7.62
7° TYP
1.14
7° TYP
3.55
2.54
0.36
3.17
0.38 MIN
10.92 MAX
0.56
0.20
0.35
.001[.025]
C
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
11
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SyncFET™
®
FPS™
Power220®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
Power247®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
Ultra FRFET™
UniFET™
VCX™
FAST®
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1988 Fairchild Semiconductor Corporation
74AC245, 74ACT245 Rev. 1.5.0
www.fairchildsemi.com
12
相关型号：
74ACT245SJX
Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
ROCHESTER
74ACT245SJX_NL
Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
FAIRCHILD
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