74ACT299MTC [ROCHESTER]
Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, PDSO20, 4.40 MM, LEAD FREE, MO-153AC, TSSOP-20;
| 型号： | 74ACT299MTC |
| 厂家： | 
Rochester Electronics |
| 描述： | Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, PDSO20, 4.40 MM, LEAD FREE, MO-153AC, TSSOP-20 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总15页 (文件大小：1175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74AC299, 74ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
Features
General Description
■ I and I reduced by 50%
The AC/ACT299 is an 8-bit universal shift/storage regis-
ter with 3-STATE outputs. Four modes of operation are
possible: hold (store), shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multi-
plexed to reduce the total number of package pins. Addi-
CC
OZ
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load
and store
tional outputs are provided for flip-flops Q , Q to allow
0
7
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24mA
easy serial cascading. A separate active LOW Master
Reset is used to reset the register.
■ ACT299 has TTL-compatible inputs
Ordering Information
Package
Order Number
74AC299SC
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC299SJ
M20D
74AC299MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC299PC
N20A
M20B
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT299SC
74ACT299MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT299PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
Description
CP
DS
DS
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
0
7
S , S
0
1
MR
Asynchronous Master Reset
3-STATE Output Enable Inputs
OE , OE
1
2
I/O –I/O
Parallel Data Inputs or 3-STATE
Parallel Outputs
0
7
Q , Q
Serial Outputs
0
7
Functional Description
The AC/ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S
0
Truth Table
and S , as shown in the Truth Table. All flip-flop outputs
1
are brought out through 3-STATE buffers to separate I/O
pins that also serve as data inputs in the parallel load
Inputs
Response
MR
S
S
CP
1
0
mode. Q and Q are also brought out on other pins for
0
7
expansion in serial shifting of longer words.
L
X
X
X
Asynchronous Reset;
Q –Q = LOW
0
7
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the
recommended setup and hold times, relative to the rising
edge of CP, are observed.
H
H
H
L
H
H
Parallel Load; I/O → Q
n
n
Shift Right;
DS → Q , Q → Q , etc.
0
0
0
1
H
H
H
L
L
L
Shift Left,
DS → Q , Q → Q , etc.
7
7
7
6
A HIGH signal on either OE or OE disables the
1
2
X
Hold
3-STATE buffers and puts the I/O pins in the high imped-
ance state. In this condition the shift, hold, load and reset
operations can still occur. The 3-STATE buffers are also
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
disabled by HIGH signals on both S and S in prepara-
0
1
tion for a parallel load operation.
= LOW-to-HIGH Transition
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
−0.5V to +7.0V
CC
IK
DC Input Diode Current
V = −0.5V
−20mA
+20mA
I
V = V + 0.5
I
CC
V
DC Input Voltage
−0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= −0.5V
−20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
−0.5V to V + 0.5V
O
CC
I
±50mA
±50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
−65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage (unless otherwise specified)
CC
AC
2.0V to 6.0V
4.5V to 5.5V
ACT
V
Input Voltage
0V to V
0V to V
I
CC
CC
V
Output Voltage
O
T
Operating Temperature
Minimum Input Edge Rate, AC Devices:
−40°C to +85°C
A
∆V / ∆t
125mV/ns
V
from 30% to 70% of V , V @ 3.3V, 4.5V, 5.5V
CC CC
IN
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
4
DC Electrical Characteristics for AC
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
3.0
V
= 0.1V or
OUT
1.5
2.1
2.1
V
IH
V
– 0.1V
CC
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
– 0.1V
V
V
IL
OUT
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
5.5
V
= V or V ,
0.36
0.36
±0.1
0.44
0.44
±1.0
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(2)
I
Maximum Input
Leakage Current
V = V , GND
µA
IN
I
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65V Max.
= 3.85V Min.
75
mA
mA
µA
OLD
OLD
(3)
I
−75
40.0
OHD
(2)
OHD
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
I
Maximum I/O
5.5
V (OE) = V , V ;
±0.3
±3.0
µA
OZT
I
IL IH
Leakage Current
V = V , GND;
I CC
V
= V , GND
CC
O
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
3. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
5
DC Electrical Characteristics for ACT
T = +25°C T = −40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
4.5
V
= 0.1V or
OUT
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
3.76
V
IH
V
− 0.1V
CC
5.5
4.5
5.5
4.5
5.5
4.5
V
Maximum LOW
Level Input Voltage
V
V
= 0.1V or
− 0.1V
1.5
V
V
IL
OUT
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= −50µA
4.49
5.49
OH
OUT
V
= V or V ,
0.0001 3.86
IN
IL
IH
I
= −24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(4)
I
I
= −24mA
OH
V
Maximum LOW
4.5
5.5
4.5
= 50µA
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
Level Output Voltage
V
= V or V ,
0.36
0.36
±0.1
0.44
0.44
±1.0
IN
IL
IH
I
= 24mA
OL
5.5
5.5
V
= V or V ,
IN
IL
IH
(4)
I
= 24mA
OL
I
Maximum Input
Leakage Current
V = V , GND
µA
IN
I
CC
I
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V − 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OHD
(5)
Output Current
I
= 3.85V Min.
−75
40.0
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
I
Maximum I/O
5.5
V (OE) = V , V ;
±0.3
±3.0
µA
OZT
I
IL IH
Leakage Current
V = V , GND;
I CC
V
= V , GND
CC
O
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
6
AC Electrical Characteristics for AC
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(6)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
f
Maximum Input Frequency
3.3
90
130
8.5
5.5
8.5
5.5
9.0
6.0
10.0
6.5
9.0
5.5
9.0
5.5
7.0
4.5
7.0
5.0
6.5
3.5
5.5
3.5
124
173
14.0
9.5
80
105
7.0
4.5
7.0
5.0
7.5
5.0
8.5
6.0
7.5
5.0
7.5
5.0
6.0
4.0
6.0
4.0
5.5
3.0
4.5
2.0
MHz
MAX
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
t
Propagation Delay, CP to Q or Q
(Shift Left or Right)
20.5
14.0
21.5
14.5
20.5
14.5
23.0
16.0
22.5
15.5
21.5
15.0
18.0
12.5
18.0
12.5
18.5
14.0
17.0
12.5
22.0
15.0
23.0
16.0
22.5
16.0
24.5
17.5
25.0
17.0
24.0
16.5
19.5
13.5
20.5
14.0
19.5
15.0
19.0
13.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
PHL
PHL
PZH
0
7
t
Propagation Delay, CP to Q or Q
(Shift Left or Right)
14.5
10.0
14.5
10.0
16.0
11.0
15.5
10.5
15.0
10.0
12.0
8.5
0
7
t
t
t
t
Propagation Delay, CP to I/O
n
n
Propagation Delay, CP to I/O
Propagation Delay, MR to Q or Q
0
7
Propagation Delay, MR to I/O
n
t
Output Enable Time, OE to I/O
Output Enable Time, OE to I/O
n
t
12.5
8.0
PZL
n
t
Output Disable Time, OE to I/O
Output Disable Time, OE to I/O
13.0
9.5
PHZ
n
t
11.5
8.0
PLZ
n
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
7
AC Operating Requirements for AC
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(7)
Symbol
Parameter
Setup Time, HIGH or LOW,
S or S to CP
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
3.3
3.0
8.0
8.5
5.5
0.5
1.0
6.0
4.0
0
ns
S
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.0
−3.0
−1.5
2.0
5.0
0.5
1.0
5.5
3.5
0
0
1
t
Hold Time, HIGH or LOW,
S or S to CP
ns
ns
ns
ns
ns
ns
ns
ns
H
0
1
t
Setup Time, HIGH or LOW,
S
I/O to CP
n
1.0
t
Hold Time, HIGH or LOW,
−2.0
−1.0
2.5
H
I/O to CP
n
1.0
6.5
4.0
0
1.0
7.0
4.5
0.5
1.0
5.0
3.5
5.0
3.5
1.5
1.5
t
Setup Time, HIGH or LOW,
S
DS or DS to CP
0
7
1.5
t
Hold Time, HIGH or LOW,
DS or DS to CP
−2.0
−1.0
3.5
H
0
7
1.0
4.5
3.5
4.5
3.5
1.5
1.5
t
t
CP Pulse Width, LOW
MR Pulse Width, LOW
Recovery Time, MR to CP
W
2.0
4.0
W
2.0
t
0
REC
0.5
Note:
7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
8
AC Electrical Characteristics for ACT
T = +25°C,
T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(8)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
MHz
ns
CC
f
Maximum Input Frequency
5.0
120
4.0
170
8.5
110
3.0
MAX
t
Propagation Delay, CP to Q or Q
(Shift Left or Right)
5.0
12.5
13.5
14.0
15.0
PLH
0
7
t
Propagation Delay, CP to Q or Q
5.0
4.0
9.0
3.5
ns
PHL
0
7
(Shift Left or Right)
t
t
t
t
Propagation Delay, CP to I/O
Propagation Delay, CP to I/O
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.5
5.0
4.0
4.0
2.5
2.0
2.0
2.5
8.5
9.5
12.5
15.0
15.0
14.5
12.0
12.0
12.5
11.5
4.5
4.5
4.0
3.5
1.5
1.5
2.0
2.0
13.5
16.5
18.0
17.5
13.0
13.5
13.5
12.5
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PHL
PHL
PZH
n
n
Propagation Delay, MR to Q or Q
14.0
13.0
8.0
0
7
Propagation Delay, MR to I/O
n
t
Output Enable Time, OE to I/O
Output Enable Time, OE to I/O
n
t
8.0
PZL
PHZ
n
t
Output Disable Time, OE to I/O
Output Disable Time, OE to I/O
8.5
n
t
8.0
PLZ
n
Note
8. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for ACT
T = +25°C, T = −40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(9)
Symbol
Parameter
V
(V)
Typ.
2.0
Guaranteed Minimum
Units
ns
CC
t
Setup Time, HIGH or LOW, S or S to CP
5.0
5.0
5.5
1.0
4.5
1.0
5.0
S
H
0
1
t
Hold Time, HIGH or LOW, S or S to CP
5.0
5.0
5.0
5.0
−2.0
1.5
1.0
4.0
1.0
4.5
ns
0
1
t
Setup Time, HIGH or LOW, I/O to CP
ns
S
H
n
t
Hold Time, HIGH or LOW, I/O to CP
−1.0
1.5
ns
n
t
Setup Time, HIGH or LOW,
ns
S
DS or DS to CP
0
7
t
Hold Time, HIGH or LOW,
DS or DS to CP
5.0
−1.0
1.0
1.0
ns
H
0
7
t
t
CP Pulse Width, HIGH or LOW
MR Pulse Width, LOW
5.0
5.0
5.0
2.0
2.0
0
4.0
3.5
1.5
4.5
3.5
1.5
ns
ns
ns
W
W
t
Recovery Time, MR to CP
REC
Note
9. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Conditions
Typ.
4.5
Units
C
Input Capacitance
V
V
= 5.0V
pF
pF
IN
CC
C
Power Dissipation Capacitance
= 5.5V
170
PD
CC
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
9
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
10
0.65
0.51
0.35
1.27
PIN ONE
INDICATOR
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
11
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
12
Physical Dimensions (Continued)
26.92
24.89
PIN #1
7.11
6.09
3.43
3.17
5.33 MAX
(0.97)
1.78
7.87
7.62
7° TYP
1.14
7° TYP
3.55
2.54
0.36
3.17
0.38 MIN
10.92 MAX
0.56
0.20
0.35
.001[.025]
C
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
13
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SyncFET™
®
FPS™
Power220®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
Power247®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
Ultra FRFET™
UniFET™
VCX™
FAST®
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1988 Fairchild Semiconductor Corporation
74AC299, 74ACT299 Rev. 1.4.0
www.fairchildsemi.com
14
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