74ACT377SJX [ROCHESTER]
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20;
| 型号： | 74ACT377SJX |
| 厂家： | 
Rochester Electronics |
| 描述： | D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：1107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
74AC377, 74ACT377
Octal D-Type Flip-Flop with Clock Enable
Features
General Description
■ I reduced by 50%
The AC/ACT377 has eight edge-triggered, D-type flip-
flops with individual D inputs and Q outputs. The com-
mon buffered Clock (CP) input loads all flip-flops simulta-
neously, when the Clock Enable (CE) is LOW.
CC
■ Ideal for addressable register applications
■ Clock enable for address and data synchronization
applications
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's Q
output. The CE input must be stable only one setup time
prior to the LOW-to-HIGH clock transition for predictable
operation.
■ Eight edge-triggered D-type flip-flops
■ Buffered common clock
■ Outputs source/sink 24mA
■ See 273 for master reset version
■ See 373 for transparent latch version
■ See 374 for 3-STATE version
■ ACT377 has TTL-compatible inputs
Ordering Information
Package
Order Number
74AC377SC
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC377SJ
M20D
74AC377MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT377SC
74ACT377SJ
74ACT377MTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
74ACT377PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
Connection Diagram
Pin Descriptions
Pin Names
Description
D –D
Data Inputs
0
7
CE
Clock Enable (Active LOW)
Data Outputs
Q –Q
0
7
CP
Clock Pulse Input
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs
Outputs
Operating Mode
CP
CE
L
D
Q
n
n
Load ‘1'
H
H
Load ‘0'
L
L
X
X
L
Hold (Do Nothing)
H
No Change
No Change
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
–0.5V to +7.0V
CC
IK
DC Input Diode Current
V = –0.5V
–20mA
+20mA
I
V = V + 0.5V
I
CC
V
DC Input Voltage
–0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= –0.5V
–20mA
+20mA
O
V
= V + 0.5V
CC
O
V
DC Output Voltage
DC Output Source or Sink Current
–0.5V to V + 0.5V
O
CC
I
50mA
50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
Junction Temperature
–65°C to +150°C
140°C
T
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
AC
CC
2.0V to 6.0V
4.5V to 5.5V
ACT
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
–40°C to +85°C
125mV/ns
A
∆V / ∆t
Minimum Input Edge Rate, AC Devices:
from 30% to 70% of V , V @ 3.3V, 4.5V, 5.5V
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACT Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
4
DC Electrical Characteristics for AC
T = +25°C
T = –40°C to +85°C
A
A
V
CC
Symbol
Parameter
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
Conditions
Typ.
Guaranteed Limits
Units
V
Minimum HIGH
Level Input Voltage
V
= 0.1V
1.5
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
IH
OUT
or V – 0.1V
CC
2.25
2.75
1.5
V
Maximum LOW
Level Input Voltage
V
= 0.1V
V
V
IL
OUT
or V – 0.1V
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH
Level Output Voltage
I
= –50µA
OH
OUT
4.4
4.4
5.4
5.4
V
= V or V ,
2.56
2.46
IN
IL
IH
I
= –12mA
OH
4.5
5.5
V
= V or V ,
3.86
4.86
3.76
4.76
IN
IL
IH
I
= –24mA
OH
V
= V or V ,
IN
IL
IH
(1)
I
I
= –24mA
OH
V
Maximum LOW
3.0
4.5
5.5
3.0
= 50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
Level Output Voltage
0.1
0.1
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 12mA
OL
4.5
5.5
V
= V or V ,
0.36
0.36
0.1
0.44
0.44
1.0
IN
IL
IH
I
= 24mA
OL
V
= V or V ,
IN
IL
IH
(1)
I
= 24mA
OL
(3)
I
Maximum Input
Leakage Current
5.5
5.5
V = V , GND
µA
IN
I
CC
I
Minimum Dynamic
Output Current
V
V
V
= 1.65V Max.
= 3.85V Min.
75
mA
mA
µA
OLD
OLD
(2)
I
–75
40.0
OHD
(3)
OHD
I
Maximum Quiescent
Supply Current
5.5
= V or GND
4.0
CC
IN
CC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
5
DC Electrical Characteristics for ACT
T = +25°C T = –40°C to +85°C
A
A
V
CC
Symbol
Parameter
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
Conditions
Typ.
Guaranteed Limits
Units
V
Minimum HIGH
Level Input Voltage
V
V
= 0.1V or
OUT
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
IH
– 0.1V
CC
V
Maximum LOW
Level Input Voltage
V
V
= 0.1V or
1.5
V
V
IL
OUT
– 0.1V
CC
1.5
V
Minimum HIGH
Level Output
Voltage
I
= –50µA
4.49
5.49
OH
OUT
V
= V or V ,
3.86
3.76
IN
IL
IH
I
= –24mA
OH
5.5
V
= V or V ,
4.86
4.76
IN
IL
IH
(4)
I
I
= –24mA
OH
V
Maximum LOW
Level Output
Voltage
4.5
5.5
4.5
= 50µA
0.001
0.001
0.1
0.1
0.1
0.1
V
OL
OUT
V
= V or V ,
0.36
0.44
IN
IL
IH
I
= 24mA
OL
5.5
5.5
V
= V or V ,
0.36
0.1
0.44
1.0
IN
IL
IH
(4)
I
= 24mA
OL
I
Maximum Input
Leakage Current
V = V , GND
µA
IN
I
CC
I
I
Maximum I /Input
5.5
5.5
V = V – 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
OLD
OHD
CC
I
CC
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OHD
(5)
Output Current
I
= 3.85V Min.
–75
40.0
I
Maximum
5.5
= V or GND
4.0
CC
IN
CC
Quiescent Supply
Current
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
6
AC Electrical Characteristics for AC
T = +25°C
T = –40°C to +85°C
A
A
(6)
Symbol
Parameter
V
(V)
Min.
90
Typ. Max.
Min.
75
Max.
Units
CC
f
Maximum Clock
Frequency
3.3
125
175
8.0
6.0
8.5
6.5
MHz
MAX
5.0
3.3
5.0
3.3
5.0
140
3.0
2.0
3.5
2.5
125
1.5
1.5
2.0
1.5
t
Propagation Delay,
13.0
9.0
14.0
10.0
14.5
11.0
ns
ns
PLH
PHL
CP to Q
n
t
Propagation Delay,
13.0
10.0
CP to Q
n
Note:
6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V
AC Operating Requirements for AC
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(7)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Setup Time, HIGH or LOW,
3.3
3.5
2.5
5.5
6.0
4.5
0
ns
S
D to CP
n
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
4.0
0
t
Hold Time, HIGH or LOW,
–2.0
–1.0
4.0
ns
ns
ns
ns
H
D to CP
n
1.0
6.0
4.0
0
1.0
7.5
4.5
0
t
Setup Time, HIGH or LOW,
CE to CP
S
2.5
t
Hold Time, HIGH or LOW,
CE to CP
–3.5
–2.0
3.5
H
1.0
5.5
4.0
1.0
6.0
4.5
t
CP Pulse Width,
HIGH or LOW
W
2.5
Note:
7. Voltage range 3.3 is 3.0V 0.3V. Voltage range 5.0 is 5.0V 0.5V
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
7
AC Electrical Characteristics for ACT
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(8)
Symbol
Parameter
V
(V)
Min. Typ. Max.
Min.
Max.
Units
CC
f
Maximum Clock
Frequency
5.0
140
3.0
3.5
175
6.5
7.0
125
2.5
2.5
MHz
MAX
t
Propagation Delay,
5.0
5.0
9.0
10.0
11.0
ns
ns
PLH
PHL
CP to Q
n
t
Propagation Delay,
CP to Q
10.0
n
Note:
8. Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements for ACT
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(9)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Setup Time, HIGH or LOW,
5.0
2.5
–1.0
2.5
4.5
1.0
4.5
1.0
4.0
5.5
ns
S
D to CP
n
t
Hold Time, HIGH or LOW,
5.0
5.0
5.0
5.0
1.0
5.5
1.0
4.5
ns
ns
ns
ns
H
D to CP
n
t
Setup Time, HIGH or LOW,
CE to CP
S
H
t
Hold Time, HIGH or LOW,
CE to CP
–1.0
2.0
t
CP Pulse Width,
HIGH or LOW
W
Note:
9. Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Conditions
Typ.
4.5
Units
C
Input Capacitance
Power Dissipation Capacitance
V
= OPEN
pF
pF
IN
CC
C
V
= 5.0V
90.0
PD
CC
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
8
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.65
0.51
0.35
1.27
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
11
Physical Dimensions (Continued)
26.92
24.89
PIN #1
7.11
6.09
3.43
3.17
5.33 MAX
(0.97)
1.78
7.87
7.62
7° TYP
1.14
7° TYP
3.55
2.54
0.36
3.17
0.38 MIN
10.92 MAX
0.56
0.20
0.35
.001[.025]
C
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
12
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SyncFET™
®
FPS™
Power220®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
Power247®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
Ultra FRFET™
UniFET™
VCX™
FAST®
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
13
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FAIRCHILD
74ACT378LC
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT378LCQR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT378LCT
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT378LCTR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT378LCX
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT378LCXR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74ACT378PC
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDIP16, PLASTIC, DIP-16
FAIRCHILD
74ACT378PCQR
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDIP16, PLASTIC, DIP-16
FAIRCHILD
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