AD5203AR10-REEL [ROCHESTER]
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, SOIC-24;
| 型号： | AD5203AR10-REEL |
| 厂家： | 
Rochester Electronics |
| 描述： | 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, SOIC-24 光电二极管 转换器 电阻器 |
| 文件： | 总13页 (文件大小：942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, 64-Position
Digital Potentiometer
a
AD5203
FEATURES
FUNCTIONAL BLOCK DIAGRAM
64 Position
Replaces Four Potentiometers
10 k⍀, 100 k⍀
DAC 1
A1
W1
B1
AGND1
6-BIT
AD5203
6
Power Shutdown—Less than 5 A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
LATCH
V
DD
RS
CK
SHDN
DGND
1
2
3
4
DAC 2
DAC
SELECT
A2
W2
B2
AGND2
6-BIT
LATCH
6
APPLICATIONS
CK RS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
SHDN
A1, A0
2
DAC 3
8-BIT
SERIAL
LATCH
A3
W3
B3
AGND3
6-BIT
LATCH
6
6
6
D
SDI
RS
CK
SHDN
CK
Q
RS
GENERAL DESCRIPTION
CLK
DAC 4
CS
A4
W4
B4
AGND4
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari-
able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack-
ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi-
tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 kΩ, or 100 kΩ has a ±1% channel-to-
channel matching tolerance with a nominal temperature coeffi-
cient of 700 ppm/°C.
6-BIT
LATCH
CK RS
SHDN
SHDN
SDO
RS
The reset RS pin forces the wiper to the midscale position by
loading 20H into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set-
ting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +85°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy-
chaining in multiple VR applications without additional external
decoding logic.
For pin compatible higher resolution applications, see the 256-
position AD8403 product.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD5203–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = +3 V ؎ 10% or +5 V ؎ 10%, V = +V , V = 0 V, –40؇C < T < +85؇C unless
otherwise noted)
DD
A
DD
B
A
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity Error2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
∆RAB/∆T
RW
RWB, VA = No Connect
RWB, VA = No Connect
–0.25
–0.5
–30
±0.1
±0.1
+0.25
+0.5
+30
LSB
LSB
%
ppm/°C
Ω
VAB = VDD, Wiper = No Connect
IW = 1 V/RAB
CH 1 to CH 2, VAB = VDD , TA = +25°C
700
45
0.2
100
1
Nominal Resistance Match
∆R/RO
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
DNL
INL
6
Bits
LSB
LSB
ppm/°C
LSB
Differential Nonlinearity Error4
–0.25
–0.75
±0.1
±0.1
20
–0.2
+0.1
+0.25
+0.75
Integral Nonlinearity Error4
Voltage Divider Temperature Coefficient ∆VW/∆T
Full-Scale Error
Zero-Scale Error
Code = 20H
Code = 3FH
Code = 00H
VWFSE
VWZSE
–0.75
0
0
+0.75
LSB
RESISTOR TERMINALS
Voltage Range5
VA, VB, VW
CA, CB
CW
IA_SD
RW_SD
0
VDD
V
Capacitance6 Ax, Bx
Capacitance6 Wx
f = 1 MHz, Measured to GND, Code = 20H
f = 1 MHz, Measured to GND, Code = 20H
VA = VDD, VB = 0 V, SHDN = 0
75
pF
pF
µA
Ω
120
0.01
45
Shutdown Supply Current7
Shutdown Wiper Resistance
5
100
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VOH
VOL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
RL = 2.2 kΩ to VDD
IOL = 1.6 mA, VDD = +5 V
VIN = 0 V or +5 V, VDD = +5 V
2.4
V
V
V
V
V
V
µA
pF
0.8
0.6
2.1
Output Logic High
Output Logic Low
Input Current
VDD–0.1
0.4
±1
Input Capacitance6
CIL
5
POWER SUPPLIES
Power Supply Range
VDD Range
IDD
IDD
PDISS
PSS
PSS
2.7
5.5
5
4
V
µA
mA
µW
%/%
%/%
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
VIH = VDD or VIL = 0 V
0.01
0.9
VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V
VIH = VDD or VIL = 0 V, VDD = +5.5 V
∆VDD = +5 V ± 10%
27.5
0.0002 0.001
∆VDD = +3 V ± 10%
0.006
0.03
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
BW_10K
BW_100K RAB = 100 kΩ
THDW
tS_10K
tS_100K
eNWB
RAB = 10 kΩ
600
71
0.003
2
18
9
kHz
kHz
%
µs
µs
nV/√Hz
nV/√Hz
dB
Total Harmonic Distortion
VW Settling Time
VA =1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1 LSB Error Band
VA = VDD, VB = 0 V, ±1 LSB Error Band
RWB = 5 kΩ, f = 1 kHz, RS = 0
RWB = 50 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
Resistor Noise Voltage
Crosstalk11
29
–65
CT
INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 12
Input Clock Pulsewidth
Data Setup Time
tCH, tCL
tDS
tDH
Clock Level High or Low
10
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold Time
CLK to SDO Propagation Delay13
CS Setup Time
tPD
RL = 2.2 kΩ, CL < 20 pF
1
25
tCSS
tCSW
tRS
tCSH
tCS1
10
10
50
0
CS High Pulsewidth
Reset Pulsewidth
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
10
–2–
REV. 0
AD5203
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R
for both VDD = +3 V or VDD = +5 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
8Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage
inputs result in minimum power dissipation.
9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10All dynamic characteristics use VDD = +5 V.
11Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
12See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V. Input logic should have a 1 V/µs minimum slew rate.
13Propagation delay depends on value of VDD, RL and CL. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
1
SDI
A1 A0 D5 D4 D3 D2 D1 D0
0
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
IAB, IAW, IBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance θJA
CLK
0
1
DAC REGISTER LOAD
CS
0
V
DD
V
OUT
0V
Figure 1a. Timing Diagram
1
0
SDI
(DATA IN)
Ax OR Dx
Ax OR Dx
tDS
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
tDH
1
0
SDO
(DATA OUT)
A'x OR D'x
A'x OR D'x
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
tPD
tPD
MIN
MAX
tCH
tCS1
1
0
CLK
tCL
tCSH
tCSS
1
0
tCSW
CS
Table I. Serial-Data Word Format
tS
؎1 LSB
V
DD
ADDR
B7
DATA
B5
V
OUT
؎ 1 LSB ERROR BAND
0V
B6
B4
B3
B2
B1
B0
Figure 1b. Detail Timing Diagram
A1
A0
D5
D4
D3
D2
D1
D0
LSB
20
MSB LSB
MSB
27 26
25
tRS
1
RS
0
tS
؎1 LSB
V
DD
V
OUT
؎1 LSB ERROR BAND
0V
Figure 1c. Reset Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD5203
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Description
Pin
No. Name
24 B1
AGND2
B2
1
2
23
22
21
20
19
18
A1
1
2
3
4
5
6
7
8
9
AGND2
Analog Ground #2*
3
A2
W1
B2
A2
W2
B Terminal RDAC #2
A Terminal RDAC #2
Wiper RDAC #2, addr = 012
Analog Ground #4*
B Terminal RDAC #4
A Terminal RDAC #4
Wiper RDAC #4, addr = 112
Digital Ground*
4
W2
AGND1
B3
5
AGND4
B4
AD5203
(Not to Scale)
6
A3
AGND4
B4
7
A4
W3
8
17 AGND3
W4
16
15
14
DGND
9
V
DD
A4
W4
10
11
SHDN
CS
RS
CLK
DGND
SHDN
13 SDO
SDI 12
10
Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors #1
through #4.
11
CS
Chip Select Input, Active Low. When CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
12
13
SDI
SDO
Serial Data Input
Serial Data Output. Open drain transistor
requires pull-up resistor.
14
15
CLK
RS
Serial Clock Input, positive edge triggered.
Active low reset to midscale; sets RDAC
registers to 20H.
16
VDD
Positive power supply, specified for opera-
tion at both +3 V and +5 V.
17
18
19
20
21
22
23
24
AGND3
W3
A3
B3
AGND1
W1
Analog Ground #3*
Wiper RDAC #3, addr =102
A Terminal RDAC #3
B Terminal RDAC #3
Analog Ground #1*
Wiper RDAC #1, addr = 002
A Terminal RDAC #1
B Terminal RDAC #1
A1
B1
*All AGNDs must be connected to DGND voltage potential.
ORDERING GUIDE
Model
k⍀
Temperature Range
Package Descriptions
Package Options
AD5203AN10
AD5203AR10
AD5203ARU10
AD5203AN100
AD5203AR100
AD5203ARU100
10
10
10
100
100
100
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Narrow Body Plastic DIP
24-Lead Wide Body (SOIC)
24-Lead Thin Surface Mount Package (TSSOP)
24-Lead Narrow Body Plastic DIP
24-Lead Wide Body (SOIC)
N-24
SOL-24
RU-24
N-24
SOL-24
RU-24
24-Lead Thin Surface Mount Package (TSSOP)
–4–
REV. 0
Typical Performance Characteristics–
AD5203
0.25
10
9
8
7
6
5
4
3
2
1
0
5
4.5
4
3F
H
V
R
= +3V, OR +5V
= 10k⍀
DD
V
= +3.0V
0.2
DD
AB
20
H
0.15
10
H
0.1
3.5
3
08
H
T
= +85؇C
0.05
0
A
05
H
2.5
2
02
–0.05
–0.1
–0.15
–0.2
–0.25
H
1.5
1
T
= –55؇C
R
R
A
WB
WA
R
= 10k⍀
AB
T
= +25؇C
A
V
T
= +5V
DD
= +25؇C
0.5
0
A
0
0
8
16
24 32
40 48
56
64
1
2
I
3
4
5
6
7
48
0
8
16
24
32
40
56 64
DIGITAL INPUT CODE – Decimal
CURRENT – mA
CODE – Decimal
WA
Figure 2. Wiper to End Terminal
Resistance vs. Code
Figure 4. Resistance Step Position
Nonlinearity Error vs. Code
Figure 3. Resistance Linearity vs.
Conduction Current
0.25
80
12
AD5203-10K VERSION
SS = 544 UNITS
V
= +3.0V
0.2
0.15
0.1
DD
V
= +4.5V
DD
10
T
= +25؇C
A
R
(END-TO-END)
AB
60
40
20
0
8
6
4
2
0
0.05
0
+25؇C
–0.05
–0.1
–0.15
–0.2
–0.25
R
(WIPER-TO-END)
WB
–55؇C
CODE = 20
H
+85؇C
0
8
16
24
32
40
48
56 64
30 31 32 33 34 35 36 37 38 39
–75 –50 –25
0
25
50 75 100 125
WIPER RESISTANCE – ⍀
DIGITAL INPUT CODE – Decimal
TEMPERATURE – ؇C
Figure 5. Wiper-Contact-Resistance
Histogram
Figure 6. Nominal Resistance vs.
Temperature
Figure 7. Potentiometer Divider
Nonlinearity Error vs. Code
0.25
120
50
V
= +3.0V
= –40؇C/+85؇C
= +2.0V
V
T
= +3.0V
= +25؇C, +85؇C, –40؇C
DD
V
= +3.0V
= –40؇C/+85؇C
= NO CONNECT
MEASURED
DD
DD
0.2
0.15
0.1
T
A
T
A
A
100
80
60
40
20
0
V
V
A
B
V
40
30
20
10
0
A
= 0V
R
WB
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
0
8
16
24
32
40
48
56 64
0
8
16 24
32 40
48
56 64
0
8
16
24
32 40
48
56 64
DIGITAL INPUT CODE – Decimal
CODE – Decimal
CODE – Decimal
Figure 8. Potentiometer Divider
Differential Nonlinearity Error vs.
Code
Figure 9. ∆VWB/∆T Potentiometer
Mode Tempco
Figure 10. ∆RWB/∆T Rheostat Mode
Tempco
REV. 0
–5–
–Typical Performance Characteristics
AD5203
0
0.75
0.5
CODE = 3F
H
V
= +5V
DD
CODE = 3F
SS = 77 UNITS
H
20
H
–10
10
08
H
H
AVG +2 ⌺
0.25
0
R
W
(20mV/DIV)
–20
–30
AVG
04
02
H
H
H
AVG –2 ⌺
–0.25
–0.5
–0.75
CS
(5V/DIV)
01
–40
–50
T
= +25؇C
A
TIME 500ns/DIV
SEE TEST CIRCUIT FIGURE 32
0
100
200
300
400
500
600
10
100
1k
10k
100k
1M
10M
HOURS OF OPERATION @ 150؇C
FREQUENCY – Hz
Figure 13. Long-Term Drift
Accelerated by Burn-In
Figure 11. One Position Step Change
at Half-Scale (Code 1FH to 20H)
Figure 12. Gain vs. Frequency for
R = 10 kΩ
10
FILTER = 22kHz
V
= +5V
DD
T
= +25؇C
= 10k⍀
A
1
0.1
R
AB
OUTPUT
V
OUT
(20mV/DIV)
SEE TEST CIRCUIT FIGURE 31
SEE TEST CIRCUIT FIGURE 30
CS
0.01
0.001
TIME 100ns/DIV
TIME 5s/DIV
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 14. Large Signal Settling Time
Figure 16. Digital Feedthrough vs.
Time
Figure 15. Total Harmonic Distortion
Plus Noise vs. Frequency
0
10
0
CODE = 3F
H
R
= 10k⍀
AB
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
20
10
H
–10
–20
–30
–40
–50
V
= +5.0V
DD
H
1
R
= 100k⍀
AB
08
04
H
H
V
= +3.0V
DD
02
H
H
0.1
V
= +5V
DD
01
CODE = 3F
H
V
= +5V
= +25؇C
DD
T
= +25؇C
A
T
A
SEE TEST CIRCUIT FIGURE 32
5dB/DIV
0.01
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
INPUT LOGIC VOLTAGE – Volts
FREQUENCY – Hz
FREQUENCY – Hz
Figure 17. 100 kΩ Gain vs. Frequency
vs. Code
Figure 19. Supply Current vs. Logic
Input Voltage
Figure 18. Normalized Gain Flat-
ness vs. Frequency
–6–
REV. 0
AD5203
1200
1000
800
600
400
200
0
80
60
40
20
0
0
A – V = +5.5V
DD
T
= +25؇C
–5
A
CODE = 15
H
B – V = +3.3V
DD
–10
–15
CODE = 15
H
f
= 65kHz,
R = 100k⍀
–3dB
C – V = +5.5V
DD
CODE = 3F
–20
–25
H
D – V = +3.3V
DD
f
= 625kHz,
–3dB
CODE = 3F
H
R = 10k⍀
–30
–35
V
T
= +5V DC ؎1V p-p AC
= +25؇C
V
= +5V
DD
DD
B
A
V
= 100mV rms
A
IN
CODE = 80
–40
H
CODE = 20
H
C
V
= 10pF
L
C
T
= +25؇C
A
= 4V, V = 0V
–45
–50
A
B
D
1k
10k
100k
1M
1k
10k
100k
FREQUENCY – Hz
1M
10M
10
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 20. Power Supply Rejection
vs. Frequency
Figure 21. –3 dB Frequency at
Half-Scale
Figure 22. Supply Current vs. Clock
Frequency
100
100
1
V
= +5V
T
= +25؇C
DD
A
LOGIC INPUT
VOLTAGE = 0, V
DD
80
60
40
20
0
V
= +2.7V
DD
0.1
10
V
= +5.5V
DD
0.01
V
V
= +5.5V
= +3.3V
DD
DD
1
–55 –35 –15
0.001
–55 –35 –15
5
25 45 65 85 105 125
0
1
2
3
– Volts
4
5
6
5
25 45 65 85 105 125
V
TEMPERATURE – ؇C
DD
TEMPERATURE – ؇C
Figure 24. Shutdown Current vs.
Temperature
Figure 23. Incremental Wiper ON
Resistance vs. VDD
Figure 25. Supply Current vs.
Temperature
REV. 0
–7–
–Parametric Test Circuits
AD5203
A
B
DUT
+5V
V+ = V
W
DUT
A
DD
V
~
IN
1LSB = V+/64
V
W
OP279
OUT
V+
OFFSET
GND
B
V
2.5V DC
MS
Figure 26. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 30. Inverting Programmable Gain Test Circuit
+5V
NO CONNECT
DUT
V
OP279
OUT
W
I
V
W
~
IN
A
W
OFFSET
GND
B
DUT
A
B
2.5V
V
MS
Figure 27. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 31. Noninverting Programmable Gain Test Circuit
I
MS
V+ Ϸ V
A
B
+15V
OP42
–15V
DD
DUT
W
I
= 1V/R
V – [V
+ I (R II R )]
W1 W AW BW
V
W
NOMINAL
W2
~
IN
A
R
= ––––––––––––––––––––––––––
DUT
V
W
W
W
I
W
V
V+
OUT
OFFSET
GND
WHERE V = V WHEN I = 0
B
W1
MS
W
AND V = V WHEN I = 1/R
2.5V
V
W2
MS
W
MS
Figure 32. Gain vs. Frequency Test Circuit
Figure 28. Wiper Resistance Test Circuit
0.1V
V
A
R
=
SW
I
DUT
SW
V+ = V ± 10%
DD
CODE = ØØ
H
⌬V
W
MS
A
B
V
DD
PSRR (dB) = 20 LOG ( ––––– )
W
⌬V
V+
~
B
DD
0.1V
I
⌬V
%
SW
MS
PSS (%/%) = –––––––
⌬V
V
MS
%
DD
0 TO V
DD
Figure 29. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
Figure 33. Incremental ON Resistance Test Circuit
–8–
REV. 0
AD5203
tap point located at 201 Ω [= RBA(nominal resistance)/64 + RW
= 156 Ω + 45 Ω)] for data 01H. The third connection is the next
tap point representing 312 + 45 = 357 Ω for data 02H. Each
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9889 Ω. The wiper does not
directly connect to the B Terminal. See Figure 34 for a simpli-
fied diagram of the equivalent RDAC circuit.
OPERATION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. Changing the pro-
grammed VR settings is accomplished by clocking in an 8-bit
serial data word into the SDI (Serial Data Input) pin. The for-
mat of this data word is two address bits, MSB first, followed by
six data bits, MSB first. Table I provides the serial register data
word format. The AD5203 has the following address assign-
ments for the ADDR decode, which determines the location of
VR latch receiving the serial register data in Bits B5 through B0:
The general transfer equation that determines the digitally pro-
grammed output resistance between Wx and Bx is:
R
WB(Dx) = (Dx)/64 × RBA + RW
(1)
VR# = A1 × 2 + A0 + 1
where Dx is the data contained in the 6-bit RDACx latch and
RBA is the nominal end-to-end resistance.
VR outputs can be changed one at a time in random sequence.
The serial clock running at 10 MHz makes it possible to load all
four VRs in under 3.2 µs (8 × 4 × 100 ns) for the AD5203. The
exact timing requirements are shown in Figure 1.
For example, when VB = 0 V and A–terminal is open circuit the
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
The AD5203 resets to a midscale by asserting the RS pin, sim-
plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin that places the RDAC in a zero power
consumption state where terminals Ax are open-circuited and
the wiper Wx is connected to Bx, resulting in only leakage cur-
rents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that, returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values.
D (DEC) RWB (⍀)
Output State
63
32
1
9889
5045
201
45
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
0
Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Ax
R
S
SHDN
R
S
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
D5
D4
D3
D2
D1
D0
terminal A also produces a digitally controlled resistance RWA
.
R
S
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
Wx
RDAC
LATCH
&
DECODER
R
WA(Dx) = (64-Dx)/64 × RBA + RW
(2)
where Dx is the data contained in the 6-bit RDACx latch and
RBA is the nominal end-to-end resistance. For example, when
VA = 0 V and B–terminal is tied to the wiper W, the following
output resistance values will be set for the following RDAC
latch codes:
R
S
Bx
R
= R /64
AB
S
Figure 34. Equivalent RDAC Circuit
D (DEC)
RWA (⍀)
Output State
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
63
32
1
201
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
5045
9889
10045
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ, and 100 kΩ. The final
digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance
(RAB) of the VR has 64 contact points accessed by the wiper
terminal, plus the B terminal contact. The 6-bit data word in
the RDAC latch is decoded to select one of the 64 possible
settings. The wiper’s first connection starts at the B terminal for
data 00H. This B–terminal connection has a wiper contact resis-
tance of 45 Ω. The second connection (10 kΩ part) is the first
0
Zero-Scale
The typical distribution of RBA from channel to channel matches
within ±1%. However, device-to-device matching is process-lot-
dependent, having a ±30% variation. The change in RBA with
temperature has a 700 ppm/°C temperature coefficient.
REV. 0
–9–
AD5203
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the VDD supply
of the AD5203 SDO output device, e.g., the AD5203 could
operate at VDD = 3.3 V and the pull-up for interface to the next
device could be set at +5 V. This allows for daisy chaining sev-
eral RDACs from a single processor serial data line. Clock pe-
riod needs to be increased when using a pull-up resistor to the
SDI pin of the following device in the series. Capacitive loading
at the daisy chain node SDO-SDI between devices must be
accounted for to successfully transfer data. When daisy chaining
is used, the CS should be kept low until all the bits of every
package are clocked into their respective serial registers insuring
that the address bits and data bits are in the proper decoding
location. This would require 16 bits of address and data comply-
ing to the word format provided in Table I if two AD5203 four-
channel RDACs are daisy chained. During shutdown, SHDN
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 37
for equivalent SDO output circuit schematic.
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V.
Each LSB of voltage is equal to the voltage applied across ter-
minal AB divided by the 64 position resolution of the potenti-
ometer divider. The general equation defining the output
voltage with respect to ground for any given input voltage ap-
plied to terminals AB is:
VW(Dx) = Dx/64 × VAB + VB
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors
not the absolute value, therefore the drift improves to 20 ppm/°C.
DIGITAL INTERFACING
The AD5203 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), CS and serial data
input (SDI). The positive-edge sensitive CLK input requires
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be de-
bounced by a flip-flop or other suitable means. The Figure 35
block diagram shows more detail of the internal digital cir-
cuitry. When CS is taken active low the clock loads data into
the serial register on each positive clock edge, see Table III.
Table II. Input Logic Control Truth Table
CLK CS
RS SHDN Register Activity
L
P
L
L
H
H
H
H
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin.
The eighth previously entered bit
is shifted out of the SDO pin.
Load SR data into RDAC latch
based on A1, A0 decode (Table III).
No Operation.
Sets all RDAC latches to midscale,
wiper centered and SDO latch
cleared.
X
P
H
H
X
X
H
X
H
L
H
H
AD5203
V
CS
DD
A1
W1
B1
CLK
D5
D0
R
EN
DAC
LAT
#1
ADDR
DEC
X
X
H
H
P
H
H
L
Latches all RDAC latches to 20H.
Open circuits all Resistor A–termi-
nals, connects W to B, turns off
SDO output transistor.
A1
A0
DO
SDO
R
D5
SER
REG
NOTE: P = positive edge, X = don’t care, SR = shift register.
A4
W4
B4
D5
D0
R
Table III. Address Decode Table
DAC
LAT
#4
DI
SDI
D0
A1
A0
Latch Decoded
6
R
0
0
1
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3
RDAC#4
SHDN
AGND
DGND
RS
Figure 35. Block Diagram
–10–
REV. 0
AD5203
The data setup and data hold times in the specification table
determine the data valid time requirements. The last eight bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it gates the
address decoder which enables one of four positive edge trig-
gered RDAC latches, see Figure 36 detail.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 38. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK.
1k⍀
LOGIC
AD5203
RDAC 1
RDAC 2
CS
Figure 38. Equivalent ESD Protection Circuit
ADDR
DECODE
RDAC 4
DYNAMIC CHARACTERISTICS
CLK
SDI
The total harmonic distortion plus noise (THD+N) measures
0.003% using an offset ground with a rail-to-rail OP279 invert-
ing op amp test circuit, see Figure 30. Figure 15 plots THD
versus frequency for both inverting and noninverting amplifier
topologies. Thermal noise is primarily Johnson noise, typically
9 nV/√Hz for the 10 kΩ version measured at 1 kHz. For the
100 kΩ device, thermal noise measures 29 nV/√Hz. Channel-to-
channel crosstalk measures less than –65 dB at f = 100 kHz. To
achieve this isolation, the extra ground pins (AGND) located
between the potentiometer terminals (A, B, W) must be con-
nected to circuit ground. The AGND and DGND pins should
be at the same voltage potential. Any unused potentiometers in
a package should be connected to ground. Power supply rejec-
tion is typically –50 dB at 10 kHz (care is needed to minimize
power supply ripple injection in high accuracy applications).
SERIAL
REGISTER
Figure 36. Equivalent Input Control Logic
The target RDAC latch is loaded with the last six bits of the
serial data word completing one RDAC update. Four separate
8-bit data words must be clocked in to change all four VR
settings.
SHDN
CS
SDO
SERIAL
REGISTER
Q
D
SDI
CK
RS
CLK
RS
Figure 37. Detail, SDO Output Schematic of the AD5203
REV. 0
–11–
AD5203
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Narrow Body Plastic DIP
(N-24)
1.275 (32.30)
1.125 (28.60)
24
1
13
0.280 (7.11)
0.240 (6.10)
12
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.150
(3.81)
MIN
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.100 (2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77) SEATING
PLANE
0.045 (1.15)
24-Lead SOIC
(SOL-24)
0.6141 (15.60)
0.5985 (15.20)
24
13
12
1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0138 (0.35)
0.0091 (0.23)
24-Lead Thin Surface Mount TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
12
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–12–
REV. 0
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