AD5282BRU50
更新时间:2024-09-18 18:40:05
品牌:ROCHESTER
描述:DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16, MO-153AB, TSSOP-16
AD5282BRU50 概述
DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16, MO-153AB, TSSOP-16 数字电位计
AD5282BRU50 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Active | 零件包装代码: | TSSOP |
包装说明: | TSSOP, | 针数: | 16 |
Reach Compliance Code: | unknown | 风险等级: | 5.84 |
其他特性: | CAN ALSO OPERATE FROM A SINGLE +5V TO +15V SUPPLY; ALSO REQUIRES A +2.7V TO +5.5V LOGIC SUPPLY | 标称带宽: | 0.15 kHz |
控制接口: | 2-WIRE SERIAL | 转换器类型: | DIGITAL POTENTIOMETER |
JESD-30 代码: | R-PDSO-G16 | JESD-609代码: | e0 |
长度: | 5 mm | 湿度敏感等级: | 1 |
标称负供电电压: | -5 V | 功能数量: | 2 |
位置数: | 256 | 端子数量: | 16 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | TSSOP |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
峰值回流温度(摄氏度): | 240 | 认证状态: | COMMERCIAL |
电阻定律: | LINEAR | 最大电阻容差: | 30% |
最大电阻器端电压: | 5 V | 最小电阻器端电压: | -5 V |
座面最大高度: | 1.2 mm | 标称供电电压: | 5 V |
表面贴装: | YES | 标称温度系数: | 30 ppm/°C |
温度等级: | INDUSTRIAL | 端子面层: | TIN LEAD |
端子形式: | GULL WING | 端子节距: | 0.65 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 30 |
标称总电阻: | 50000 Ω | 宽度: | 4.4 mm |
Base Number Matches: | 1 |
AD5282BRU50 数据手册
通过下载AD5282BRU50数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Single/Dual, +15 V/ 5 V, ꢀ5ꢁ6-PoiꢂiPn,
IꢀC6CPmpaꢂible Digiꢂal -PꢂenꢂiPmeꢂer
AD5ꢀ80/AD5ꢀ8ꢀ
logic outputs that enable users to drive digital loads, logic gates,
LED drivers, and analog switches in their system.
FEATURES
AD5280: 1 channel
The AD5280/AD5282 are available in thin, surface-mounted
14-lead TSSOP and 16-lead TSSOP. All parts are guaranteed to
operate over the extended industrial temperature range of
−40°C to +85°C. For 3-wire SPI-compatible interface applica-
tions, see the AD5260/AD5262 product information on
www.analog.com.
AD5282: 2 channels
256 positions
5 V to 15 V single supply; 5.5 V dual-supply operation
Fixed terminal resistance: 20 kΩ, 50 kΩ, 200 kΩ
Low temperature coefficient: 30 ppm/°C
Power-on midscale preset1
Programmable reset
Operating temperature: −40oC to +85oC
I2C-compatible interface
FUNCTIONAL BLOCK DIAGRAMS
A
W
B
O
O
2
1
APPLICATIONS
SHDN
Multimedia, video, and audio
Communications
V
DD
V
L
RDAC REGISTER
OUTPUT REGISTER
PWR ON
V
SS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage source
Programmable current source
Line impedance matching
ADDRESS
CODE
RESET
8
SCL
SDA
GND
SERIAL INPUT REGISTER
GENERAL DESCRIPTION
AD5280
The AD5280/AD5282 are single-channel and dual-channel,
256-position, digitally controlled variable resistors (VRs)2.
The devices perform the same electronic adjustment function
as a potentiometer, trimmer, or variable resistor. Each VR offers
a completely programmable value of resistance between the
A terminal and the wiper or the B terminal and the wiper. The
fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has
a 1% channel-to-channel matching tolerance. The nominal
temperature coefficient of both parts is 30 parts per million/
degrees centigrade (ppm/°C). Another key feature is that the
parts can operate up to +15 V or 5 V.
AD0
AD1
Figure 1. AD5280
A
W
B
A
W
B
O
1
1
1
1
2
2
2
OUTPUT
REGISTER
SHDN
V
DD
V
L
RDAC1 REGISTER
RDAC2 REGISTER
PWR ON
V
SS
ADDRESS
CODE
RESET
8
Wiper position programming defaults to midscale at system
power-on. When powered, the VR wiper position is programmed
by an I2C-compatible, 2-wire serial data interface. The AD5280/
AD5282 feature sleep mode programmability. This allows any
level of preset in power-up and is an alternative to a costly
EEPROM solution. Both parts have additional programmable
SCL
SDA
GND
SERIAL INPUT REGISTER
AD5282
AD0
AD1
Figure 2. AD5282
1 Assert shutdown and program the device during power-up, then deassert
the shutdown to achieve the desired preset level.
2 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
AD5ꢀ80/AD5ꢀ8ꢀ
TABLE OF CONTENTS
Features .............................................................................................. 1
Multiple Devices on One Bus ................................................... 17
Level Shift for Bidirectional Interface...................................... 18
Level Shift for Negative Voltage Operation ............................ 18
ESD Protection ........................................................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
Layout and Power Supply Bypassing ....................................... 19
Applications Information.............................................................. 20
Bipolar DC or AC Operation from Dual Supplies................. 20
Gain Control Compensation .................................................... 20
15 V, 8-Bit I2C DAC.................................................................... 20
8-Bit Bipolar DAC...................................................................... 21
Bipolar Programmable Gain Amplifier................................... 21
Programmable Voltage Source with Boosted Output ........... 21
Programmable Current Source ................................................ 22
Programmable Bidirectional Current Source......................... 22
Programmable Low-Pass Filter ................................................ 23
Programmable Oscillator .......................................................... 23
RDAC Circuit Simulation Model............................................. 24
Macro Model Net List for RDAC ............................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 12
Theory of Operation ...................................................................... 14
Rheostat Operation .................................................................... 14
Potentiometer Operation........................................................... 14
Digital Interface .............................................................................. 16
2-Wire Serial Bus........................................................................ 16
Readback RDAC Value .............................................................. 17
Additional Programmable Logic Output ................................ 17
Self-Contained Shutdown Function and Programmable
Preset............................................................................................ 17
REVISION HISTORY
8/07—Rev. A to Rev. B
Updated Operating Temperature Range Throughout...................1
Changes to the Features Section.......................................................1
Changes to the General Description Section..................................1
Changes to Table 2..............................................................................3
Added the Thermal Resistance Section...........................................5
Changes to the Ordering Guide......................................................26
11/05—Rev. 0 to Rev. A
Updated Format...................................................................Universal
Updated Outline Dimensions.........................................................26
Changes to Ordering Guide ............................................................27
10/02—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
S-ECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = −5 V; VLOGIC = 5 V, VA = +VDD, VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS–RHEOSTAT MODE
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistor Tolerance3
R-DNL
R-INL
ΔRAB
RWB, VA = NC
RWB, VA = NC
TA = 25°C
−1
−1
−30
1ꢀ/
1ꢀ/
+1
+1
+30
LSB
LSB
%
Resistance Temperature
Coefficient
(∆RABꢀRAB)ꢀ∆T x 106
VAB = VDD, wiper = no connect
30
60
ppmꢀ°C
Wiper Resistance
RW
IW = VDDꢀR, VDD = 3 V or 5 V
150
Ω
DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE (specifications apply to all VRs)
Resolution
N
8
Bits
Integral Nonlinearity/
Differential Nonlinearity/
INL
−1
−1
1ꢀ/
1ꢀ/
5
+1
+1
LSB
DNL
LSB
Voltage Divider Temperature
Coefficient
(∆VWꢀVW)ꢀ∆T x 106
Code = 0x80
ppmꢀ°C
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−2
0
−1
+1
0
+2
LSB
LSB
VA, VB, VW
CA, CB
VSS
VDD
V
Capacitance A, B6
f = 5 MHz, measured to GND,
Code = 0x80
f = 1 MHz, measured to GND,
Code = 0x80
25
55
1
pF
Capacitance W6
CW
pF
Common-Mode Leakage
Shutdown Current
ICM
VA = VB = VW
nA
μA
ISHDN
5
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VIL
VIH
VIL
IIL
0.7 × VL
VL + 0.5
0.3 × VL
V
Input Logic Low
0
V
Output Logic High (O1, O2)
Output Logic Low (O1, O2)
Input Current
/.9
V
0./
1
V
VIN = 0 V or 5 V
μA
pF
Input Capacitance6
CIL
5
POWER SUPPLIES
Logic Supply
VLOGIC
VDD RANGE
VDDꢀSS RANGE
ILOGIC
2.7
/.5
/.5
VDD
16.5
5.5
60
1
V
Power Single-Supply Range
Power Dual-Supply Range
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation7
VSS = 0 V
V
V
VLOGIC = 5 V
μA
μA
μA
mW
IDD
VIH = 5 V or VIL = 0 V
0.1
0.1
0.2
ISS
1
PDISS
VIH = 5 V or VIL = 0 V, VDD = +5 V, VSS = −5
V
0.3
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth −3 dB
PSS
0.002
0.01
%ꢀ%
BW_20K
BW_50K
BW_200K
RAB = 20 kΩ, Code = 0x80
RAB = 50 kΩ, Code = 0x80
RAB = 200 kΩ, Code = 0x80
310
150
35
kHz
kHz
kHz
Rev. B | Page 3 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Total Harmonic Distortion
THDW
VA = 1 V rms, RAB = 20 kΩ
VB = 0 V dc, f = 1 kHz
0.01/
%
VW Settling Time
Crosstalk
tS
VA = 5 V, VB = 5 V, 1 LSB error band
5
μs
CT
VA = VDD, VB = 0 V, measure VW1 with
adjacent RDAC making full-scale
code change
15
nV-s
Analog Crosstalk
CTA
Measure VW1 with VW2 = 5 V p-p @ f =
10 kHz
RWB = 20 kΩ, f = 1 kHz
−62
18
dB
Resistor Noise Voltage
eN_WB
nVꢀ√Hz
INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11
SCL Clock Frequency
fSCL
t1
/00
kHz
μs
0
1.3
tBUF Bus Free Time Between
Stop and Start
tHD:STA Hold Time (Repeated
Start)
t2
After this period, the first clock pulse 0.6
is generated
μs
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
t3
t/
t5
1.3
0.6
0.6
μs
μs
μs
tSU:STA Setup Time for Start
Condition
tHD:DAT Data Hold Time
tSU:DAT Data Setup Time
t6
t7
t8
0.9
μs
ns
ns
0
100
tF Fall Time of Both SDA and
SCL Signals
tR Rise Time of Both SDA and
SCL Signals
tSU:STO Setup Time for STOP
Condition
300
300
t9
ns
μs
t10
0.6
1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
/ INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram (Figure 3) for location of measured values.
11 Standard I2C mode operation is guaranteed by design.
t2
t8
t6
t9
SCL
SDA
t10
t4
t7
t5
t2
t3
t9
t8
t1
P
S
S
P
Figure 3. Detailed Timing Diagram
Rev. B | Page / of 28
AD5ꢀ80/AD5ꢀ8ꢀ
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
VDD to GND
VSS to GND
VDD to VSS
−0.3 V to +16.5 V
0 V to −7 V
16.5 V
VA, VB, VW to GND
VSS to VDD
THERMAL RESISTANCE
AX to BX, AX to WX, BX to WX
Intermittent3
Continuous
20 mA
5 mA
0 V to 7 V
0 V to 7 V
−/0°C to +85°C
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. Package
power dissipation = (TJMAX − TA)/ θJA .
VLOGIC to GND
Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature Range
Reflow Soldering
Table 3. Thermal Resistance
Package Type
θJA
Unit
°CꢀW
°CꢀW
)
TSSOP-1/
TSSOP-16
206
150
−65°C to +150°C
Peak Temperature
Time at Peak Temperature
260°C
20 sec to /0 sec
ESD CAUTION
3 Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
Rev. B | Page 5 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
-IN CONFIGURATIONS AND FUNCTION DESCRI-TIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
O
A
A
2
A
W
B
O
1
1
1
1
1
W
B
V
2
L
W
B
O
AD5280
TOP VIEW
2
2
AD5282
V
V
V
V
SS
L
DD
TOP VIEW
V
SHDN
SCL
GND
AD1
AD0
DD
SS
SHDN
GND
AD1
AD0
8
SCL
SDA
SDA
Figure 4. AD5280 Pin Configuration
Figure 5. AD5282 Pin Configuration
Table 5. AD5282 Pin Function Descriptions
Table 4. AD5280 Pin Function Descriptions
Pin No. Mnemonic Description
Pin No.
Mnemonic Description
1
2
3
/
5
O1
A1
W1
B1
Logic Output Terminal O1.
1
2
3
/
A
W
B
Resistor Terminal A.
Wiper Terminal W.
Resistor Terminal B.
Positive Power Supply. Specified for
operation from 5 V to 15 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Active Low, Asynchronous Connection
of Wiper W to Terminal B and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should tie
to VL if not used. Can also be used as a
programmable preset in power-up.
Resistor Terminal A1.
Wiper Terminal W1.
Resistor Terminal B1.
Positive Power Supply. Specified for
operation from 5 V to 15 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Active Low, Asynchronous Connection
of Wiper W to Terminal B and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should tie
to VL if not used. Can be also used as a
programmable preset in power-up.
VDD
VDD
5
SHDN
6
SHDN
6
7
8
SCL
SDA
AD0
Serial Clock Input.
Serial Data InputꢀOutput.
7
8
9
SCL
SDA
AD0
Serial Clock Input.
Serial Data InputꢀOutput.
Programmable Address Bit 0 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Programmable Address Bit 1 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Programmable Address Bit 0 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Programmable Address Bit 1 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
9
AD1
10
AD1
10
11
GND
VSS
Common Ground.
11
12
GND
VSS
Common Ground.
Negative Power Supply. Specified for
operation from 0 V to −5 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Negative Power Supply. Specified for
operation from 0 V to −5 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Logic Supply Voltage. Needs to be less
than or equal to VDD and at the same
voltage as the digital logic controlling
the AD5282.
12
13
O2
VL
Logic Output Terminal O2.
13
VL
Logic Supply Voltage. Needs to be less
than or equal to VDD and at the same
voltage as the digital logic controlling
the AD5280.
1/
15
16
B2
W2
A2
Resistor Terminal B2.
Wiper Terminal W2.
Resistor Terminal A2.
1/
O1
Logic Output Terminal O1.
Rev. B | Page 6 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
TY-ICAL -ERFORMANCE CHARACTERISTICS
1.0
0.5
0.4
R
= 20kꢀ
AB
R
= 20kΩ
AB
0.8
T
= 25°C
A
0.6
0.3
+5V
0.4
0.2
T
= –40°C
T
= +85°C
A
A
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
±5V
+15V
T
= +25°C
224
A
0
0
0
32
64
96
128
160
192
224
256
256
256
0
0
0
32
64
96
128
160
192
256
256
256
CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL vs. Code vs. Supply Voltages
Figure 9. DNL vs. Code, VDD/VSS = 5 V
0.5
0.4
1.0
0.8
R
= 20kꢀ
AB
= 25°C
R
= 20kꢀ
= 25°C
AB
T
A
T
A
0.3
0.6
±5V
+15V
±5V
0.2
0.4
+5V
0.1
0.2
+15V
0
0
–0.1
–0.2
–0.3
–0.8
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
+5V
32
64
96
128
160
192
224
32
64
96
128
160
192
224
CODE (Decimal)
CODE (Decimal)
Figure 7. R-DNL vs. Code vs. Supply Voltages
Figure 10. INL vs. Code vs. Supply Voltages
1.0
0.8
0.5
0.4
R
= 20kꢀ
R
= 20kꢀ
AB
AB
= 25°C
T
A
0.6
0.3
T
= +85°C
+5V
A
0.4
0.2
±5V
+15V
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
T
= –40°C
A
T
= +25°C
A
32
64
96
128
160
192
224
32
64
96
128
160
192
224
CODE (Decimal)
CODE (Decimal)
Figure 8. INL vs. Code, VDD/VSS
=
5 V
Figure 11. DNL vs. Code vs. Supply Voltages
Rev. B | Page 7 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
1.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
R
= 20kꢀ
AB
R
= 20kꢀ
AB
= 25°C
T
A
AVG +3σ
0.5
0
V
/V = +5V/0V
DD SS
AVG
AVG –3σ
V
/V = ±5V
DD SS
V
/V = +15V/0V
DD SS
–0.5
–1.0
0
5
10
15
20
–40
–20
0
20
40
60
80
100
|V – V | (V)
TEMPERATURE (°C)
DD SS
Figure 12. INL Over Supply Voltage
Figure 15. Zero-Scale Error
2.0
1.5
1000
100
10
R
= 20kꢀ
= 25°C
AB
R
= 20kꢀ
V
V
V
= +5V
= +5V
= 0V
AB
LOGIC
T
A
IH
IL
AVG +3σ
1.0
AVG
0.5
AVG –3σ
|
@V /V = +15V/0V
DD SS
0
SS
–0.5
–1.0
–1.5
–2.0
|
@V /V = ±5V
DD SS
SS
|
@V /V = ±5V
DD SS
DD
1
–40
0
5
10
15
20
–7
26
59
85
|V – V | (V)
TEMPERATURE (°C)
DD SS
Figure 16. Supply Current vs. Temperature
Figure 13. R-INL Over Supply Voltage
26.0
25.5
25.0
24.5
24.0
23.5
23.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
R
= 20kꢀ
R
= 20kꢀ
AB
AB
V
/V = +15V/0V
DD SS
V
/V = +15V/0V
DD SS
V
/V = ±5V
DD SS
V
/V = +5V/0V
DD SS
V
/V = ±5V
DD SS
–40
–7
26
TEMPERATURE (°C)
59
85
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. VLOGIC Supply Current vs. Temperature
Figure 14. Full-Scale Error
Rev. B | Page 8 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
1000
100
10
0
–6
80H
40H
R
= 20kꢀ
AB
= 25°C
T
A
–12
–18
–24
–30
–36
–42
–48
–54
–60
20H
V
V
/V = 5V/0V
DD SS
10H
08H
04H
= 5V
LOGIC
02H
01H
T
V
V
= 25°C
= 50mV rms
/V = ±5V
DD SS
V
V
/V = 5V/0V
DD SS
A
= 3V
A
LOGIC
0
1
2
3
4
5
0
10k
100k
1M
V
(V)
FREQUENCY (Hz)
IH
Figure 18. VLOGIC Supply Current vs. Digital Input Voltage
Figure 21. Gain vs. Frequency vs. Code, RAB = 20 kΩ
700
600
500
400
300
200
100
0
0
–6
T
= 25°C
80H
40H
A
–12
–18
–24
–30
–36
–42
–48
–54
–60
20H
10H
08H
04H
20kꢀ
50kꢀ
200kꢀ
02H
01H
T
= 25°C
A
–100
–200
V
V
= 50mV rms
/V = ±5
DD SS
A
0
32
64
96
128
192
224
256
0
10k
100k
1M
CODE (Decimal)
FREQUENCY (Hz)
Figure 19. Rheostat Mode Tempco ΔRWB/ΔT vs. Code, VDD/VSS
=
5 V
Figure 22. Gain vs. Frequency vs. Code, RAB = 50 kΩ
120
0
–6
T
= 25°C
80H
A
100
80
40H
20H
10H
08H
04H
–12
–18
–24
–30
–36
–42
–48
–54
–60
20kꢀ
50kꢀ
200kꢀ
60
40
20
02H
01H
0
T
= 25°C
A
–20
–40
V
V
= 50mV rms
/V = ±5V
DD SS
A
0
32
64
96
128
192
224
256
0
10k
100k
1M
CODE (Decimal)
FREQUENCY (Hz)
Figure 20. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code,
VDD/VSS 5 V
Figure 23. Gain vs. Frequency vs. Code, RAB = 200 kΩ
=
Rev. B | Page 9 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
0
80
60
40
20
0
R = 20kꢀ
310kHz
CODE = 80 , V = V , V = 0V
DD
H
A
B
–6
–12
–18
–24
–30
–36
–42
–48
–54
–PSRR @ V /V = ±5V
DD SS
DC ±10% p-p AC
R = 50kꢀ
150kHz
R = 200kꢀ
35kHz
+PSRR @ V /V = ±5V
DD SS
DC ±10% p-p AC
T
V
V
= 25°C
/V = ±5V
DD SS
= 50mV rms
A
A
–60
0
10k
100k
1M
100
1000
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 27. PSRR vs. Frequency
Figure 24. −3 dB Bandwidth
T
V
= 25°C
A
A2
1.2V
852.0µs
/V = ±5V
DD SS
R = 20kꢀ
–6dB
R = 50kꢀ
R = 200kꢀ
2.04µs
100
1k
10k
100k
FREQUENCY (Hz)
Figure 25. Normalized Gain Flatness vs. Frequency
Figure 28. Midscale Glitch Energy Code 0x80 to 0x7F
500
400
300
200
100
0
T
T
V
= 25°C
A
/V = ±5V
DD SS
+5V
V
1
W
–5V
CODE = 55
H
CS
2
CODE = 55
H
10k
100k
FREQUENCY (Hz)
1M
10M
CH1 5.00V CH2 5.00V
M100ns
A
CH1
0V
Figure 26. VLOGIC Supply Current vs. Frequency
Figure 29. Large Signal Settling Time
Rev. B | Page 10 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
40
30
20
10
0
CODES SET TO
MIDSCALE
3 LOTS
A2
1.0V
33.41µs
SAMPLE SIZE = 135
1.50µs
LONG TERM CHANNEL-TO-CHANNEL RAB MATCH (%)
Figure 30. Digital Feedthrough vs. Time
Figure 32. Channel-to-Channel Resistance Matching (AD5282)
100
10
V
T
= V = OPEN
B
= 25°C
A
A
1.0
R
R
= 20kꢀ
= 50kꢀ
AB
AB
0.1
R
= 200kꢀ
AB
0.01
0
32
64
96
128
192
224
256
CODE (Decimal)
Figure 31. IWB_MAX vs. Code
Rev. B | Page 11 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
TEST CIRCUITS
Figure 33 to Figure 43 define the test conditions used in the product specification table.
A
DUT
B
DUT
A
V+ = V
DD
1LSB = V+/2
N
5V
W
V
IN
W
V+
B
V
OUT
OP279
V
MS
OFFSET
GND
OFFSET
BIAS
Figure 37. Inverting Gain
Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL)
5V
NO CONNECT
DUT
I
W
V
OUT
OP279
A
V
IN
W
W
B
OFFSET
GND
V
MS
A
DUT
B
OFFSET
BIAS
Figure 38. Noninverting Gain
Figure 34. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
I
= V /R
DD NOMINAL
A
W
+15V
DUT
A
V
W
W
W
V
DUT
IN
V
V
OUT
MS2
AD8610
–15V
B
OFFSET
GND
V
MS1
B
R
= [V
MS1
–V
]/I
MS2
W
W
2.5V
Figure 35. Wiper Resistance
Figure 39. Gain vs. Frequency
0.1V
V+ = V ±10%
DD
V
R
=
A
SW
I
ΔV
ΔV
SW
MS
DUT
B
PSRR (dB) = 20 LOG
(
)
DD
ΔV
ΔV
%
%
MS
W
PSS (%/%) =
V
DD
A
B
DD
W
V+
I
SW
0.1V
V
MS
V
TO V
SS
DD
Figure 36. Power Supply Sensitivity (PSS, PSSR)
Figure 40. Incremental On Resistance
Rev. B | Page 12 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
NC
V
A
DD
A
2
NC = NO CONNECT
1
RDAC
RDAC
2
1
V
I
A
DD
DUT
CM
W
W
1
2
W
V
V
OUT
IN
N/C
B
V
SS
GND
V
V
SS
B
B
2
CM
1
NC
C
= 20 LOG [V /V ]
OUT IN
TA
Figure 41. Common-Mode Leakage Current
Figure 43. Analog Crosstalk (AD5282 Only)
V
I
LOGIC
LOGIC
SCL
SCA
DIGITAL INPUT
VOLTAGE
Figure 42. VLOGIC Current vs. Digital Input Voltage
Rev. B | Page 13 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
THEORY OF O-ERATION
The AD5280/AD5282 are single-channel and dual-channel,
256-position, digitally controlled variable resistors (VRs). To
program the VR settings, see the Digital Interface section. Both
parts have an internal power-on preset that places the wiper at
midscale during power-on, which simplifies the fault condition
recovery at power-up. Operation of the power-on preset function
also depends on the state of the VL pin.
The general equation determining the digitally programmed
output resistance between W and B is
D
256
RWB
(
D
)
=
× RAB + RW
(1)
where:
D is the decimal equivalent of the binary code loaded in the 8-
bit RDAC register.
A
X
SW
A
R
R
AB is the nominal end-to-end resistance.
W is the wiper resistance contributed by the on resistance of
SHDN
R
S
the internal switch.
Note that in the zero-scale condition, a finite wiper resistance
of 60 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
R
R
0xFF
D7
D6
D5
D4
D3
D2
D1
D0
S
S
W
X
As in the mechanical potentiometer, the resistance of the RDAC
between Wiper W and Terminal A also produces a digitally
controlled complementary resistance, RWA. When these terminals
are used, the B terminal can be opened. Setting the resistance
value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value. The
general equation for this operation is
RDAC
LATCH
AND
0x01 SW
0x00
B
DECODER
R
S
B
X
Figure 44. AD5280/AD5282 Equivalent RDAC Circuit
RHEOSTAT OPERATION
256 − D
256
RWA
(
D
)
=
× RAB + RW
(2)
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final
two or three digits of the part number determine the nominal
resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, and
200 kΩ = 200. The nominal resistance (RAB) of the VR has
256 contact points accessed by the wiper terminal, plus the B
terminal contact. The eight-bit data in the RDAC latch is
decoded to select one of the 256 possible settings. Assuming
that a 20 kΩ part is used, the wiper’s first connection starts at
the B terminal for data 0x00. Because there is a 60 Ω wiper
contact resistance, such a connection yields a minimum of 60 Ω
resistance between Terminal W and Terminal B.
The typical distribution of the nominal resistance, RAB, from
channel to channel matches within 1%. Device-to-device
matching is process lot dependent, and it is possible to have a
30% variation. Because the resistance element is processed in
thin film technology, the change in RAB with temperature is very
small (30 ppm/°C).
POTENTIOMETER OPERATION
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A to be proportional to the input voltage
at A to B. Unlike the polarity of VDD – VSS, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity, provided that VSS is powered by a negative supply.
The second connection is the first tap point that corresponds to
138 Ω (RWB = RAB/256 + RW = 78 Ω + 60 Ω) for data 0x01. The
third connection is the next tap point representing 216 Ω (78 ×
2 + 60) for data 0x02, and so on. Each LSB data value increase
moves the wiper up the resistor ladder until the last tap point is
reached at 19,982 Ω (RAB – 1 LSB + RW). Figure 46 shows a
simplified diagram of the equivalent RDAC circuit where the
last resistor string is not accessed; therefore, there is 1 LSB less
of the nominal resistance at full scale in addition to the wiper
resistance.
If the effect of the wiper resistance for approximation is ignored,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across A to B divided by the 256 positions of the
potentiometer divider. Because the AD5280/AD5282 can be
supplied by dual supplies, the general equation defining the
output voltage at VW with respect to ground for any valid
Rev. B | Page 1/ of 28
AD5ꢀ80/AD5ꢀ8ꢀ
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors RWA and RWB and not on the absolute
values; therefore, the temperature drift reduces to 5 ppm/°C.
input voltage applied to Terminal A and Terminal B is
D
256
256 − D
256
VW
(
D
)
=
VA +
VB
(3)
For a more accurate calculation that includes the effect of wiper
resistance, VW can be found as
RWB
RAB
(
D
)
RWA (D)
RAB
(4)
VW
(
D
)
=
VA +
VB
1
9
1
9
1
9
SCL
SDA
AD1
0
1
0
1
1
AD0 R/W
A/B RS SD O1 O2
X
X
X
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
AD5280/5282
ACK. BY
AD5280/AD5282
ACK. BY
AD5280/5282
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
STOP BY
MASTER
Figure 45. Writing to the RDAC Register
1
9
1
9
SCL
0
1
0
1
1
AD1 AD0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
A
SDA
ACK. BY
AD5280/AD5282
NO ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED
STOP BY
MASTER
Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode
Table 6. Serial Format of Data Accepted from the I2C Bus
S
0
1
0
1
1
AD1
AD0
W
Rꢀ
A
A
RS
SD O1
O2
X
X
X
A
D7
D6
D5 D/ D3 D2 D1 D0
A
P
ꢀB
Slave Address Byte
Instruction Byte
Data Byte
where:
Abbreviation
Equals
S
P
A
X
Start condition
Stop condition
Acknowledge
Don’t care
AD1, AD0
RꢀW
Package pin programmable address bits
Read enable at high and write enable at low
RDAC subaddress select; 0 = RDAC1 and 1 = RDAC2
Midscale reset, active high (only affects selected channel)
AꢀB
RS
SD
Shutdown; same as SHDN pin operation except inverse logic (only affects selected channel)
O2, O1
Output logic pin latched values; default Logic 0
Data bits
D7, D6, D5, D/, D3, D2, D1, D0
Rev. B | Page 15 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
DIGITAL INTERFACE
2-WIRE SERIAL BUS
The AD5280/AD5282 are controlled via an I2C-compatible serial
bus. The RDACs are connected to this bus as slave devices. As
shown in Figure 45, Figure 46, and Table 6, the first byte of the
AD5280/AD5282 is a slave address byte. It has a 7-bit slave
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to
the RDAC.
The following two bits are O1 and O2. They are extra program-
mable logic outputs that can be used to drive other digital loads,
logic gates, LED drivers, analog switches, and so on. The three
LSBs are don’t care bits (see Figure 45).
W
address and an R/ bit.
The 5 MSBs are 01011, and the two bits that follow are deter-
mined by the state of the AD0 pin and the AD1 pin of the
device. AD0 and AD1 allow the user to place up to four of the
I2C-compatible devices on one bus. The 2-wire I2C serial bus
protocol operates as follows.
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 45).
The master initiates data transfer by establishing a start condi-
tion, which happens when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 45). The following
byte is the slave address byte, which consists of the 7-bit slave
address followed by an R/ bit (this bit determines whether
data is read from or written to the slave device).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, the transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46).
W
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits for
W
data to be written to or read from its serial register. If the R/ bit
When all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the tenth clock
pulse to establish a stop condition (see Figure 45). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master then
brings the SDA line low before the 10th clock pulse, which goes
high to establish a stop condition (see Figure 46).
is high, the master reads from the slave device. On the other
hand, if the R/ bit is low, the master writes to the slave device.
W
A write operation contains one instruction byte more than a
read operation. Such an instruction byte in write mode follows
the slave address byte. The most significant bit (MSB) of the
A
instruction byte labeled /B is the RDAC subaddress select. A
low selects RDAC1 and a high selects RDAC2 for the dual
A
channel AD5282. Set /B low for the AD5280.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte updates
the RDAC output. For example, after the RDAC has acknow-
ledged its slave address and instruction bytes, the RDAC output
updates after these two bytes. If another byte is written to the
RDAC while it is still addressed to a specific slave device with the
same instruction, this byte updates the output of the selected slave
device. If different instructions are needed, the write mode has to
start with a new slave address, instruction, and data byte again.
Similarly, a repeated read function of RDAC is also allowed.
RS, the second MSB, is the midscale reset. A logic high on this
bit moves the wiper of a selected channel to the center tap
where RWA = RWB. This feature effectively writes over the
contents of the register and thus, when taken out of reset mode,
the RDAC remains at midscale.
SD, the third MSB, is a shutdown bit. A logic high causes the
selected channel to open circuit at Terminal A while shorting
the wiper to Terminal B. This operation yields almost 0 Ω in
rheostat mode or 0 V in potentiometer mode. This SD bit serves
SHDN
SHDN
the same function as the
pin except that the
pin
SHDN
reacts to active low. Also, the
pin affects both channels
(AD5282) as opposed to the SD bit, which affects only the
channel that is being written to. Note that the shutdown
Rev. B | Page 16 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
READBACK RDAC VALUE
The AD5280/AD5282 allow the user to read back the RDAC
values in read mode. However, for the dual-channel AD5282,
the channel of interest is the one that is previously selected in
the write mode. When users need to read the RDAC values of
both channels in the AD5282, they can program the first
subaddress in write mode and then change to read mode to read
the first channel value. After that, they can change back to write
mode with the second subaddress and read the second channel
value in read mode again. It is not necessary for users to issue
the Frame 3 data byte in write mode for subsequent readback
operation. Users should refer to Figure 45 and Figure 46 for the
programming format.
In addition, shutdown can be implemented with the device
digital output as shown in Figure 47. In this configuration, the
device is shut down during power-up, but the user is allowed to
program the device at any preset levels. When it is done, the
user programs O1 high with the valid coding and the device
exits from shutdown and responds to the new setting. This self-
contained shutdown function allows absolute shutdown during
power-up, which is crucial in hazardous environments, without
adding extra components. Also, the sleep mode programming
feature during shutdown allows the AD5280/AD5282 to have a
programmable preset at any level, a solution that can be as
effective as using other high cost EEPROM devices. Because of
the extra power drawn on RPD, note that a high value should be
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
chosen for the RPD
.
The AD5280/AD5282 feature additional programmable logic
outputs, O1 and O2, which can be used to drive a digital load,
analog switches, and logic gates. O1 and O2 default to Logic 0. The
logic states of O1 and O2 can be programmed in Frame 2 under
write mode (see Figure 45). These logic outputs have adequate
current driving capability to sink/source milliamperes of load.
O
1
SHDN
R
PD
SDA
SCL
Users can also activate O1 and O2 in three ways without
affecting the wiper settings by programming as follows:
Figure 47. Shutdown by Internal Logic Output
MULTIPLE DEVICES ON ONE BUS
•
Perform start, slave address, acknowledge, and instruction
bytes with O1 and O2 specified, acknowledge, stop.
Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, stop.
Not complete the write cycle by not issuing the stop, then
start, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, stop.
Figure 48 shows four AD5282 devices on the same serial bus.
Each has a different slave address because the states of their Pin
AD0 and Pin AD1 are different. This allows each RDAC within
each device to be written to or read from independently. The
master device output bus line drivers are open-drain pull-
downs in a fully I2C-compatible interface.
•
•
5V
R
R
P
P
SELF-CONTAINED SHUTDOWN FUNCTION AND
PROGRAMMABLE PRESET
SDA
SCL
MASTER
5V
5V
5V
SDA SCL
SDA SCL
AD1
SDA SCL
AD1
SDA SCL
AD1
SHDN
Shutdown can be activated by strobing the
pin or
AD1
programming the SD bit in the write mode instruction byte.
As shown in Figure 44, when shutdown is asserted, the
AD5280/AD5282 open SWA to let the A terminal float and
short the W terminal to the B terminal. The AD5280/AD5282
consume negligible power during shutdown mode, resuming
AD0
AD0
AD0
AD0
AD5282
AD5282
AD5282
AD5282
Figure 48. Multiple AD5282 Devices on One Bus
SHDN
the previous setting once the
pin is released.
Rev. B | Page 17 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE
While most old systems can be operated at one voltage, a new
component can be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, a 3.3 V EEPROM can interface
with a 5 V digital potentiometer. A level-shift scheme is needed
to enable a bidirectional communication so that the setting of
the digital potentiometer can be stored to and retrieved from
the EEPROM. Figure 49 shows one of the implementations.
M1 and M2 can be any N-channel signal FETs or low threshold
FDV301N if VDD falls below 2.5 V.
V
DD
+5V
0
V
Q3
Q1
IN
0
Q2
0
V
OUT
R2
10kꢀ
R3
10kꢀ
0
–5V
V
= –5V
SS
Figure 51. Level Shift for Bipolar Potential Operation
V
= 3.3V
V
= 5V
DD1
DD2
R
R
R
R
P
G
P
P
P
ESD PROTECTION
S
D
SDA1
SCL1
SDA2
SCL2
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures, as shown in Figure 52. The
M1
G
S
D
SHDN
protection applies to digital inputs SDA, SCL, and
.
M2
3.3V
EEPROM
5V
AD5282
340ꢀ
LOGIC
Figure 49. Level Shift for Different Potential Operation
LEVEL SHIFT FOR NEGATIVE VOLTAGE
OPERATION
V
SS
Figure 52. ESD Protection of Digital Pins
The digital potentiometer is popular in laser diode driver
applications and certain telecommunications equipment level-
setting applications. These applications are sometimes
operated between ground and a negative supply voltage such
that the systems can be biased at ground to avoid large bypass
capacitors that may significantly impede the ac performance.
Like most digital potentiometers, the AD5280/AD5282 can be
configured with a negative supply (see Figure 50).
TERMINAL VOLTAGE OPERATING RANGE
The AD5280/AD5282 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on
Resistor Terminal A, Resistor Terminal B, and Wiper Terminal
W that exceed VDD or VSS are clamped by the internal forward-
biased diodes (see Figure 53).
V
DD
V
DD
A
W
B
V
SS
V
–5V
LEVEL SHIFTED
LEVEL SHIFTED
GND
SDA
SCL
SS
Figure 53. Maximum Terminal Voltages Set by VDD and VSS
Figure 50. Biased at Negative Voltage
POWER-UP SEQUENCE
However, the digital inputs must also be level shifted to allow
proper operation because the ground is referenced to the
negative potential. Figure 51 shows one implementation with a
few transistors and a few resistors. When VIN is below the Q3
threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state,
Because there are ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W (see
Figure 53), it is important to power VDD/VSS before applying any
voltage to the A, B, and W terminals. Otherwise, the diode is
forward biased such that VDD/VSS is unintentionally powered,
which may affect the rest of the user’s circuit. The ideal power-
up sequence is the following: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA/VB/VW and digital inputs
is not important as long as they are powered after VDD/VSS.
VOUT approaches 0 V. When VIN is above 2 V, Q3 is on, Q1 is on,
and Q2 is turned off. In this state, VOUT is pulled down to VSS.
Be aware that proper time shifting is also needed for successful
communication with the device.
Rev. B | Page 18 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
LAYOUT AND POWER SUPPLY BYPASSING
V
V
V
DD
DD
+
+
C3
C1
It is a good practice to design a layout with compact, minimum
lead lengths. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
10µF
0.1µF
AD5280/
AD5282
C4
C2
0.1µF
10µF
V
SS
SS
GND
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple (see Figure 54). Notice that the digital ground should also
be joined remotely to the analog ground at one point to
minimize digital ground bounce.
Figure 54. Power Supply Bypassing
Rev. B | Page 19 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
A--LICATIONS INFORMATION
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option unless C2 is scaled as if R2 were at its maximum
value. Doing so may overcompensate and compromise the
performance slightly when R2 is set at low values. However, it
avoids the gain peaking, ringing, or oscillation at the worst case.
For critical applications, C2 should be found empirically to suit
the need. In general, C2 in the range of a few picofarads (pF) to
no more than a few tenths of a picofarad is usually adequate for
the compensation.
BIPOLAR DC OR AC OPERATION FROM DUAL
SUPPLIES
The AD5280/AD5282 can be operated from dual supplies
enabling control of ground-referenced ac signals or bipolar
operation. The ac signal, as high as VDD/VSS, can be applied
directly across Terminal A to Terminal B with the output taken
from Terminal W. See Figure 55 for a typical circuit connection.
+5.0V
V
DD
A
1
SCLK
SCL
SDA
MICROCONTROLLER
W
1
MOSI
GND
±2.5V p-p
D–80
±5V p-p
B
1
H
AD5282
Similarly, there are W and A terminal capacitances connected to
the output (not shown); fortunately, their effect at this node is less
significant and the compensation can be avoided in most cases.
GND
A
2
W
2
15 V, 8-BIT I2C DAC
B
2
V
SS
V
DD
–5.0V
V
DD
R
BIAS
Figure 55. Bipolar Operation from Dual Supplies
U2
U1A
GAIN CONTROL COMPENSATION
V+
AD8512
V–
AD5280
D1
The digital potentiometer is commonly used in gain control
applications such as the noninverting gain amplifier shown in
Figure 56.
U1B
200kꢀ
ADR512
V
O
B
AD8512
200kꢀ
A
R2
B
W
R1
C2
4.7pF
Figure 57. 8-Bit I2C DAC
47kꢀ
R
1
C
25pF
AD5280/AD5282 can be configured as a high voltage DAC, as
high as 15 V. The output is
1
V
U1
O
V
I
D
R
[1.2V× (1+ 2 )]
R1
(5)
Figure 56. Typical Noninverting Gain Amplifier
VO (D) =
256
Notice that the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node. It introduces a 0
for the 1/βO term with 20 dB/decade (dec), whereas a typical op
amp GBP has −20 dB/dec characteristics. A large R2 and finite
C1 can cause the 0 frequency to fall well below the crossover
frequency. Thus the rate of closure becomes 40 dB/dec, and the
system has a 0° phase margin at the crossover frequency. The
output may ring or oscillate if the input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values because this is equivalent to a step
change at the input.
Rev. B | Page 20 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
8-BIT BIPOLAR DAC
+15V
As in the previous example, in the simpler and more common
case where K = 1, a single digital AD5280 potentiometer is
used. U1 is replaced by a matched pair of resistors to apply
Vi and −Vi at the ends of the digital potentiometer. The
relationship becomes
+
U
2
V
1
OP2177
–
V
O
W
U
1
A
2
V
IN
B
A
–15V
R
R
R2 2D2
⎞⎛
⎛
⎞
V
OUT
(7)
VO = 1+
−1 ×V
⎜
⎟⎜
R1 256
⎟
–5V
+15V
i
+5V
REF
REF
TRIM
⎠⎝
⎠
⎝
GND
–
If R2 is large, a compensation capacitor having a few pF may be
needed to avoid any gain peaking.
ADR425
OP2177
+
AD5280
–
U
2
Table 7 shows the result of adjusting D, with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and a 256-step
resolution.
A
1
–15V
Figure 58. 8-Bit Bipolar DAC
Figure 58 shows a low cost, 8-bit, bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at
low value codes, are skewed by the effects of the digital potenti-
ometer wiper resistance. The output of this circuit is
Table 7. Result of Bipolar Gain Amplifier
D
R1 = R2
R2 = 9R1
R1 = ∞, R2 = 0
0
6/
128
192
255
−1
−0.5
0
0.5
0.968
−2
−1
0
−10
−5
0
2D
256
⎛
⎜
⎝
⎞
⎠
V =
−1 ×V
(6)
⎟
O
REF
1
5
1.937
9.680
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
V
DD
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
+
U
W
2
2
V
OP2177
O
For applications that require high current adjustments, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 60).
AD5282 A
B
2
2
–
C1
R2
R1
A
A
2
V
2
S8
A
B
1
1
–kVI
V
1
W
V
1
DD
V
V
O
I
+
5V
U
1
+
R
N
BIAS
1
AD5282
OP2177
I
C
L
C
–
SIGNAL
A
B
W
+
–
V+
V–
U
1
A
V
1
S8
A1
Figure 59. Bipolar Programmable Gain Amplifier
U
A
N
= AD5280
= AD8501, AD8605, AD8541
= FDV301N, 2N7002
1
1
1
For applications that require bipolar gain, Figure 59 shows one
implementation similar to the previous circuit. The digital
potentiometer, U1, sets the adjustment range. The wiper voltage
at W2 can therefore be programmed between Vi and –KVi at a
given U2 setting. Configuring A2 in noninverting mode allows
linear gain and attenuation. The transfer function is
Figure 60. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the
BIAS to be equal to the wiper voltage set by the digital potenti-
V
ometer. The load current is then delivered by the supply via the
N-channel FET N1. The N1 power handling must be adequate
to dissipate (Vi – VO) × IL power. This circuit can source a
maximum of 100 mA with a 5 V supply. A1 needs to be a rail-
to-rail input type. For precision applications, a voltage reference
such as ADR423, ADR292, or AD1584 can be applied at the
input of the digital potentiometer.
VO
Vi
R2
R1
D2
⎛
⎝
⎞
⎟
⎛
⎜
⎞
⎟
(7)
= 1+
×
×
(
1+ K − K
)
⎜
256
⎠
⎝
⎠
where K is the ratio of RWB1/RWA1 set by U1.
Rev. B | Page 21 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
PROGRAMMABLE CURRENT SOURCE
PROGRAMMABLE BIDIRECTIONAL CURRENT
SOURCE
+5V
I
I
R1
R2
U
150kꢀ
15kꢀ
1
2
V
0 TO (2.048 + V )
L
IN
3
6
V
SLEEP
OUT
B
C1
10pF
+15V
V+
REF191
GND
C1
1µF
W
R
102ꢀ
A
+5V
S
4
OP2177
V–
+5V
A
+15V
A
2
R2
B
AD5280
V+
50kꢀ
–15V
AD5280
V+
OP2177
V–
OP8510
W
U
2
V
L
–2.048V TO V
V
L
L
R1
150kꢀ
R2
R
L
A
V–
A
R
100ꢀ
14.95kꢀ
500kꢀ
–5V
1
L
I
L
5V
–15V
|
L
Figure 61. Programmable Current Source
Figure 62. Programmable Bidirectional Current Source
A programmable current source can be implemented with the
circuit shown in Figure 61. REF191 is a unique, low supply
headroom and high current handling precision reference that
can deliver 20 mA at 2.048 V. The load current is simply the
voltage across Terminal B to Terminal W of the digital
potentiometer divided by RS.
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (see Figure 62). If the resistors are matched, the load
current is
R2A + R2B
)
R1
(9)
VREF × D
IL
=
×VW
(8)
IL =
R2B
RS ×2N
In theory, R2B can be made as small as needed to achieve the
The circuit is simple, but attention must be paid to two things.
First, dual-supply op amps are ideal because the ground
potential of REF191 can swing from −2.048 V at zero scale to VL
at full scale of the potentiometer setting. Although the circuit
works under single supply, the programmable resolution of the
system is reduced.
current needed within the A2 output current driving capability.
In this circuit, the OP2177 can deliver 5 mA in either direction,
and the voltage compliance approaches 15 V. It can be shown
that the output impedance is
R1' ×R2B
R1×R2' − R1'
R1+ R2A
ZO
=
(10)
(
R2A + R2B
)
For applications that demand higher current capabilities, a
few changes to the circuit in Figure 61 produce an adjustable
current in the range of hundreds of milliamps. First, the voltage
reference needs to be replaced with a high current, low dropout
regulator, such as the ADP3333, and the op amp needs to be
swapped with a high current dual-supply model, such as the
AD8532. Depending on the desired range of current, an
appropriate value for RS must be calculated. Because of the high
current flowing to the load, the user must pay attention to the
load impedance so as not to drive the op amp beyond the
positive rail.
This output impedance can be infinite if Resistor R1' and
Resistor R2' match precisely with R1 and R2A + R2B,
respectively. On the other hand, it can be negative if the
resistors are not matched. As a result, C1 must be in the range
of 1 pF to 10 pF to prevent the oscillation.
Rev. B | Page 22 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
PROGRAMMABLE LOW-PASS FILTER
In analog-to-digital conversion applications, it is common to
include an antialiasing filter to band-limit the sampling signal.
Dual-channel digital potentiometers can be used to construct
a second-order Sallen key low-pass filter (see Figure 63). The
At resonance, setting the following balances the bridge:
R2
(16)
= 2
R1
In practice, R2/R1 should be set slightly larger than 2 to ensure
that oscillation can start. On the other hand, the alternate turn-
on of Diode D1 and Diode D2 ensures that R2/R1 are smaller
than 2 momentarily and, therefore, stabilizes the oscillation.
design equations are
2
VO
ωO
=
(11)
ω
S2 + O S + ωO
2
V
i
Q
Once the frequency is set, the oscillation amplitude can be
1
tuned by R2B because
ωO =
(12)
(13)
2
R1R2C1C2
(17)
VO = ID R2B +VD
3
1
1
Q =
+
R1C1 R2C2
VO, ID, and VD are interdependent variables. With proper
selection of R2B, an equilibrium is reached such that VO
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be
too large to prevent saturation of the output.
FREQUENCY
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, R1 and R2 can be
adjusted to the same settings to achieve the desirable bandwidth.
C1
I
I
ADJUSTMENT
C
R
2.2nF
10kꢀ
VP
C
B
A
B
+2.5V
C
2.2nF
R
10kꢀ
W
R1
R2
+2.5V
A
B
A
B
W
V
V+
AD8601
I
A
V+
V
O
U
W
W
1
V
V–
U
OP1177
V–
O
R
R
I
R1 = R1 = R2B = AD5282
D1 = D2 = 1N4148
1
C2
C
–2.5V
–2.5V
VN
ADJUSTED TO
SAME SETTING
R2
A
2.1kꢀ
D1
D2
R2
10kꢀ
B
Figure 63. Sallen Key Low-Pass Filter
B
A
R1
1kꢀ
PROGRAMMABLE OSCILLATOR
W
In a classic Wien-bridge oscillator (Figure 64), the Wien
network (R, R', C, C') provides positive feedback, while R1
and R2 provide negative feedback. At the resonant frequency, fO,
the overall phase shift is 0, and the positive feedback causes the
circuit to oscillate. With R = R', C = C', and R2 = R2A//(R2B +
Rdiode), the oscillation frequency is
AMPLITUDE
ADJUSTMENT
Figure 64. Programmable Oscillator with Amplitude Control
1
1
(14)
ωO
=
or fo =
RC
2πRC
where R is equal to RWA such that
256 − D
256
R =
RAB
(15)
Rev. B | Page 23 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
RDAC CIRCUIT SIMULATION MODEL
MACRO MODEL NET LIST FOR RDAC
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5280
(20 kΩ resistor) measures 310 kHz at half scale. Figure 24
provides the Bode plot characteristics of the three available
resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic
simulation model is shown in Figure 65. A macro model net list
for the 20 kΩ RDAC is provided.
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA
RWA
CW
RWB
A
A
W
W
B
0
W
0
B
0
25E-12
{(1-D/256)*RDAC+60}
55E-12
{D/256*RDAC+60}
25E-12
CB
RDAC
20kꢀ
*
A
B
.ENDS DPOT
C
C
A
A
25pF
25pF
C
W
85pF
Figure 65. RDAC Circuit Simulation Model for RDAC = 20 kΩ
Rev. B | Page 2/ of 28
AD5ꢀ80/AD5ꢀ8ꢀ
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 66. 14-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 67. 16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Dimensions shown in millimeters
Rev. B | Page 25 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
ORDERING GUIDE
No. of
Channels
Temperature
Range
Package
Option
Model1
RAB (kΩ)
20
20
50
50
200
200
20
20
50
Package Description
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
1/-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Ordering Quantity
AD5280BRU20
AD5280BRU20-REEL7
AD5280BRU50
AD5280BRU50-REEL7
AD5280BRU200
AD5280BRU200-REEL7
AD5280BRUZ202
AD5280BRUZ20-REEL72
AD5280BRUZ502
AD5280BRUZ50-REEL72
AD5280BRUZ2002
AD5280BRUZ200-R72
AD5282BRU20
AD5282BRU20-REEL7
AD5282BRU50
AD5282BRU50-REEL7
AD5282BRU200
AD5282BRU200-REEL7
AD5282BRUZ202
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
−/0°C to +85°C
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-1/
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
50
200
200
20
20
50
50
200
200
20
20
50
AD5282BRUZ20-REEL72
AD5282BRUZ502
AD5282BRUZ50-REEL72
AD5282BRUZ2002
AD5282BRUZ200-R72
AD5282-EVAL
50
200
200
20
1,000
1
Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and Line 3 contains date code YYWW.
Z = RoHS Compliant Part.
2
Rev. B | Page 26 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
NOTES
Rev. B | Page 27 of 28
AD5ꢀ80/AD5ꢀ8ꢀ
NOTES
©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02929-0-8/07(B)
Rev. B | Page 28 of 28
AD5282BRU50 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
AD5282BRU50-REEL7 | ADI | Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer | 获取价格 | |
AD5282BRU50-REEL7 | ROCHESTER | DUAL 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16, MO-153AB, TSSOP-16 | 获取价格 | |
AD5282BRUZ20 | ROCHESTER | DUAL 20K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16 | 获取价格 | |
AD5282BRUZ20-REEL72 | ADI | Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer | 获取价格 | |
AD5282BRUZ200 | ADI | Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer | 获取价格 | |
AD5282BRUZ200 | ROCHESTER | Digital Potentiometer, 1 Func, 200000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16 | 获取价格 | |
AD5282BRUZ200-R7 | ADI | Single/Dual, +15 V/±5 V, 256-Position, I2C-Compatible Digital Potentiometer | 获取价格 | |
AD5282BRUZ200-R72 | ADI | Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer | 获取价格 | |
AD5282BRUZ200-REEL7 | ADI | IC DUAL 200K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16, MO-153AB, TSSOP-16, Digital Potentiometer | 获取价格 | |
AD5282BRUZ2002 | ADI | Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer | 获取价格 |
AD5282BRU50 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6