AD74111YRU-REEL7 [ROCHESTER]
SPECIALTY CONSUMER CIRCUIT, PDSO16, TSSOP-16;
| 型号： | AD74111YRU-REEL7 |
| 厂家： | 
Rochester Electronics |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16, TSSOP-16 光电二极管 商用集成电路 |
| 文件： | 总21页 (文件大小：995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost, Low Power
Mono Audio Codec
AD74111
FEATURES
GENERAL DESCRIPTION
2.5 V Mono Audio Codec with 3.3 V Tolerant
Digital Interface
Supports 8 kHz to 48 kHz Sample Rates
Supports 16-/20-/24-Bit Word Lengths
Multibit ꢀ-ꢁ Modulators with
The AD74111 is a front-end processor for general-purpose audio
and voice applications. It features a multibit ⌺-⌬ A/D conversion
channel and a multibit ⌺-⌬ D/A conversion channel. The ADC
channel provides >67 dB THD+N and the DAC channel pro-
vides >88 dB THD+N, both over an audio signal bandwidth.
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DAC – Least Sensitive to Jitter
Performance (20 Hz to 20 kHz)
85 dB ADC Dynamic Range
The AD74111 is particularly suitable for a variety of applications
where mono input and output channels are required, including
audio sections of digital video camcorders, portable personal
audio devices, and telematic applications. Its high quality
performance also makes it suitable for speech and telephony
applications such as speech recognition and synthesis, and modern
feature phones.
93 dB DAC Dynamic Range
Programmable ADC Gain
On-Chip Volume Control for DAC Channel
Software Controllable Clickless Mute
Supports 256 ꢂ fS, 512 ꢂ fS, and 768 ꢂ fS Master Mode
Clocks
Master Clock Prescaler for Use with DSP Master Clocks
On-Chip Reference
An on-chip reference voltage is included but can be powered
down and bypassed by an external reference source if required.
The AD74111 offers sampling rates that, depending on MCLK
selection and MCLK divider ratio, range from 8 kHz in the
voiceband range to 48 kHz in the audio range.
16-Lead TSSOP Package
The AD74111 is available in a 16-lead TSSOP package option
and is specified for the automotive temperature range of –40°C
to +105°C.
APPLICATIONS
Digital Video Camcorders (DVC)
Portable Audio Devices (Walkman®, PDAs, and so on)
Audio Processing
Voice Processing
Telematic Systems
General-Purpose Analog I/O
FUNCTIONAL BLOCK DIAGRAM
RESET
MCLK
DVDD1
DVDD2
AVDD
ADC
CAPP
ꢀ-ꢁ
MODULATOR
DIGITAL
FILTER
GAIN
STAGE
VIN
DIN
SERIAL
DATA
PORT
DOUT
DFS
CAPN
DCLK
DAC CHANNEL
DIGITAL
FILTER
VOLUME
CONTROL
ꢀ-ꢁ DAC
MODULATOR
REFERENCE
VOUT
DGND
REFCAP
AGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(AVDD = 2.5 V 5%, DVDD2 = 2.5 V 5%, DVDD1 = 2.5 V 5%, fMCLK = 12.288 MHz,
AD74111–SPECIFICATIONS fS = 48 kHz, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Signal to Noise Ratio (SNR)
Dynamic Range
24
77
Bits
dB
fS = 16 kHz
70
(20 Hz to 20 kHz, –60 dB Input)
No Filter
fS = 48 kHz
fS = 16 kHz
fS = 48 kHz
fS = 48 kHz, PGA = 0 dB
fS = 16 kHz
85
85
87
–67
–75
12
3
+30
0.5
4
dB
dB
dB
dB
dB
dB
dB
mV
V rms
kΩ
pF
78
With A-Weighted Filter
Total Harmonic Distortion + Noise
Programmable Input Gain
Gain Step Size
Offset Error
Full-Scale Input Voltage
Input Resistance
Input Capacitance
Common-Mode Input Volts
Crosstalk
–55
+80
15
1.125
100
V
dB
ADC Input Signal = 1.0 kHz,
0 dB; DAC Output = DC
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Signal to Noise Ratio (SNR)
Dynamic Range
(20 Hz to 20 kHz, –60 dB Input)
No Filter
24
89
Bits
dB
fS = 16 kHz
80
84
fS = 48 kHz
fS = 16 kHz
fS = 48 kHz
fS = 48 kHz
fS = 16 kHz
93
93
95
–88
–88
dB
dB
dB
dB
dB
dB
With A-Weighted Filter
Total Harmonic Distortion + Noise
–81
DC Accuracy
Offset Error
Gain Error
–75
–0.9
–10
+0.175
+50
+0.8
mV
dB
Volume Control Step Size
(1024 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
De-emphasis Gain Error
Full-Scale Output Voltage
Output Resistance
0.098
–60
–100
0.1
%
dB
dB
dB
V rms
Ω
0.5
145
1.125
95
Common Mode Output Volts
Crosstalk
V
dB
Signal Input ADC = AGND;
DAC Output
Level = 1.0 kHz, 0 dB
REFERENCE (Internal)
Absolute Voltage, VREF
VREF TC
1.125
50
V
ppm/°C
–2–
REV. 0
AD74111
Parameter
Conditions
Min
Typ
Max
Unit
ADC DECIMATION FILTER*
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
fS = 48 kHz
21.5
0.2
kHz
mdB
kHz
kHz
dB
µs
µs
5
26.5
120
910
87
Low Group Delay Mode
DAC INTERPOLATION FILTER*
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
fS = 48 kHz
21.5
10
kHz
mdB
kHz
kHz
dB
µs
µs
5
26.5
75
505
55
Low Group Delay Mode
LOGIC INPUT
VINH, Input High Voltage
DVDD1 – 0.8
0
DVDD1
0.8
V
V
V
INL, Input Low Voltage
Input Current
Input Capacitance
–10
+10
10
µA
pF
LOGIC OUTPUT
VOH, Output High Voltage
DVDD1 – 0.4
0
DVDD1
0.4
V
V
V
OL, Output Low Voltage
Three-State Leakage Current
–10
+10
µA
POWER SUPPLIES
AVDD
DVDD2
2.375
2.375
2.375
2.625
2.625
3.6
V
V
V
DVDD1
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog
Supply Pins
50/60 Hz, 300 mV p-p Signal at Analog
Supply Pins
72
73
dB
dB
*Guaranteed by design.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = 2.5 V, DVDD1 = 2.5 V, DVDD2 = 2.5 V)1, 2, 3
AVDD
DVDD1
DVDD2
Current (mA) (Max)(mA)
Total Current
Conditions
Current (mA) Current (mA)
ADC, Reference, Ref-Amp On 6.11 (6.11)
DAC, Reference, Ref-Amp On 3.80 (4.0)
0.15 (0.43)
0.15 (0.43)
0.15 (0.43)
0.15 (0.43)
0.15 (0.43)
0.72 (2.10)
0.85 (2.23)
0.27 (0.50)
1.72 (4.80)
0.49 (0.49)
Reference, Ref-Amp On
All Sections On
0.60 (0.60)
8.60
15.35
2.6
Power-Down Mode
0.035
NOTES
1All values are typical, unless otherwise noted.
2Max values are quoted with DVDD1 = 3.6 V.
3Sample rates quoted are for 16 kHz and (48 kHz).
REV. 0
–3–
AD74111
5%, DVDD2 = 2.5 V 5%, DVDD1 = 3.3 V 10%, fMCLK = 12.288 MHz, fS = 48 kHz,
TIMING CHARACTERISTICS (TAAV=DDTM=IN2t.o5 TVMAX, unless otherwise noted.)
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
tML
tRES
tRS
MCLK High
MCLK Low
RESET Low
DIN Setup Time
DIN Setup Time
25
25
10
5
ns
ns
ns
MCLKS
MCLKS
To RESET Rising Edge1
To RESET Rising Edge1
tRH
5
SERIAL PORT
tCH
tCL
tFD
tFS
tFH
tDD
tDS
tDH
tDT
DCLK High2
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
DCLK Low2
DFS Delay
5
From DCLK Rising Edge3
To DCLK Falling Edge
From DCLK Falling Edge
From DCLK Rising Edge
To DCLK Falling Edge
From DCLK Falling Edge
From DCLK Rising Edge4
DFS Setup Time
DFS Hold Time
DOUT Delay
DIN Setup Time
DIN Hold Time
DOUT Three-State
5
15
30
40
5
15
NOTES
1Determines Master/Slave mode operation.
2Applies in Slave mode only.
3Applies in Master mode only.
4Applies in Multiframe-Sync mode only.
tMH
MCLK
tML
RESET
tRES
DIN
tRS
tRH
Figure 1. MCLK and RESET Timing
tFS
DFS
tFH
tCH
DCLK
tCL
tFD
MSB
MSB–1
MSB–2
DIN
tDS
tDH
MSB–1
MSB
MSB–2
DOUT
tDD
Figure 2. Serial Port Timing
100ꢃA
I
OL
DVDD1
2
TO OUTPUT
PIN
C
L
50pF
100ꢃA
I
OH
Figure 3. Load Circuit for Digital Output Timing Specifications
–4–
REV. 0
AD74111
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
16-Lead TSSOP, θJA Thermal Impedance . . . . . . . .150.4°C/W
Lead Temperature, Soldering
AVDD, DVDD2 to AGND, DGND . . . . . . . –0.3 V to +3.0 V
DVDD1 to AGND, DGND . . . . . . . . . . . . . –0.3 V to +4.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . . –0.3 V to DVDD1 + 0.3 V
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TEMPERATURE RANGE
ORDERING GUIDE
Parameter
Min
Max
Unit
Model
Range
Package
Specifications Guaranteed
Storage
–40
–65
+105
+150
ºC
ºC
AD74111YRU
–40ºC to +105ºC
RU-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD74111 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD74111
PIN CONFIGURATION
16
15
14
13
12
11
10
9
MCLK
DVDD1
DVDD2
DGND
AGND
REFCAP
CAPP
VIN
DCLK
DIN
1
2
3
4
5
6
7
8
DFS
AD74111
DOUT
RESET
AVDD
CAPN
VOUT
TOP VIEW
(NOT TO SCALE)
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
I/O
1
2
DCLK
DIN
I/O
I
Serial Clock
Serial Data Input. The state of DIN on the rising edge of RESET determines the operating mode
of the interface. See the Selecting Master or Slave Mode section for more information.
3
4
5
6
7
DFS
I/O
O
I
Frame Synchronization Signal
Serial Data Output
Power-Down/Reset Input
Analog 2.5 V Power Supply Connection
ADC Filter Capacitor (Negative)
DAC Analog Output
DOUT
RESET
AVDD
CAPN
VOUT
VIN
8
9
O
I
ADC Analog Input
10
11
12
13
14
15
16
CAPP
ADC Filter Capacitor (Positive)
Internal Reference Decoupling Capacitor. Can also be used for connection of an external reference.
Analog Ground Connection
REFCAP
AGND
DGND
DVDD2
DVDD1
MCLK
I/O
Digital Ground Connection
Digital 2.5 V Power Supply Connection (Core)
Digital Power Supply Connection (Interface)
External Master Clock Input
I
–6–
REV. 0
Typical Performance Characteristics–AD74111
0
0
–50
–40
–100
–150
–80
–120
0
0.25
0.5
0.75
1.0
0
0.25
0.5
0.75
1.0
FREQUENCY – NORMALIZED TO fS
FREQUENCY – NORMALIZED TO
f
s
TPC 1. ADC Composite Filter Response
TPC 4. DAC Composite Filter Response
0
0
–50
–40
–100
–150
–80
–120
0
0.25
0.5
0.75
1.0
0
0.25
0.5
0.75
1.0
FREQUENCY – NORMALIZED TO fS
FREQUENCY – NORMALIZED TO
f
s
TPC 2. ADC Composite Filter Response
Low Group Delay Enabled
TPC 5. DAC Composite Filter Response
Low Group Delay Enabled
1.0
0.5
10
5
0
0
–0.5
–1.0
–5
–10
0
0.1
0.2
0.3
0.4
0.5
0
0.1
0.2
0.3
0.4
0.5
FREQUENCY – NORMALIZED TO
f
FREQUENCY – NORMALIZED TO fS
s
TPC 3. ADC Composite Filter Response
(Pass-Band Section)
TPC 6. DAC Composite Filter Response
(Pass-Band Section)
REV. 0
–7–
AD74111
90
88
78
74
86
84
82
70
66
62
80
78
58
54
84
32
24
SAMPLE RATE – kHz
8
16
40
48
32
24
SAMPLE RATE – kHz
16
40
48
TPC 7. ADC THD+N vs. Sample Rate
TPC 8. DAC THD+N vs. Sample Rate
FUNCTIONAL DESCRIPTION
General Description
ADC Section
The AD74111 contains a multibit sigma-delta ADC. The ADC
has a single input pin with additional pins for decoupling/filter
capacitors. The ADC channel has an independent input amplifier
gain stage that can be programmed in steps of 3 dB, from 0 dB
to 12 dB. The input amplifier gain settings are set by program-
ming the appropriate bits in Control Register E. The ADC can
also be muted under software control. The AD74111 input
channel employs a multibit sigma-delta conversion technique that
provides a high resolution output with system filtering imple-
mented on-chip. Sigma-delta converters employ a technique
known as oversampling, where the sampling rate is many times
the highest frequency of interest. In the case of the AD74111,
the oversampling ratio is 64 and a decimation filter is used to
reduce the output to standard sample rates. The maximum sample
rate is 48 kHz.
The AD74111 is a 2.5 V mono codec. It comprises an ADC and
DAC channel with single-ended input and output. The ADC
has a programmable gain stage and the DAC has programmable
volume control. Each of these sections is described in further
detail below. The AD74111 is controlled by means of a flexible
serial port (SPORT) that can be programmed to accommodate
many industry standard DSPs and microcontrollers. The AD74111
can be set to operate as a master or slave device. The AD74111
can be set to operate with sample rates of 8 kHz to 48 kHz,
depending on the values of MCLK and the MCLK prescalers.
On-chip digital filtering is provided as part of the DAC and
ADC channels with a low group delay option to reduce the delays
through the filters when operating at lower sample rates. Figure 4
shows a block diagram of the DAC and ADC channel in the
AD74111. Figures 5a and 5b show block diagrams of the filter
arrangements of the ADC and DAC filters.
MCLK
ADC
INPUT
ꢀ-ꢁ ADC
MODULATOR
DECIMATOR
(/8)
ADC
DATA
PRESCALERS
(/1 to /12)
SINC FILTER
(/8)
/4
16-/20-/24-
BITS
ADC MODULATOR
CLOCK
ꢀ-ꢁ DAC
MODULATOR
/2
DAC O/P
DAC MODULATOR
CLOCK
5 BITS
DAC
INTERPOLATOR
INTERPOLATOR
(ꢂ 8)
DATA
(ꢂ 16)
16-/20-/24-
BITS
Figure 4. ADC and DAC Engine
–8–
REV. 0
AD74111
4 ꢂ fS
2 ꢂ fS
fS
ADC
MODULATOR
64 ꢂ fS
8 ꢂ fS
5th ORDER
COMB FILTER
COMB
COMPENSATION
ADC
RESULT
HALF-BAND
HALF-BAND
LOW GROUP
DELAY OUTPUT
Figure 5a. ADC Filter Section
DAC
MODULATOR
128 ꢂ fS
4 ꢂ fS
2 ꢂ fS
fS
8 ꢂ fS
ZERO ORDER HOLD
SINC COMPENSATION
FILTER
DAC
INPUT
16 ꢂ ZERO
ORDER HOLD
HALF-BAND–
FILTER
HALF-BAND
FILTER
LOW GROUP
DELAY INPUT
Figure 5b. DAC Filter Section
ADC, CAPP, and CAPN Pins
Output Signal Swing
The ADC channel requires two external capacitors to act as
charge reservoirs for the switched capacitor inputs of the sigma-
delta modulator. These capacitors isolate the outputs of the PGA
stage from glitches generated by the sigma-delta modulator. The
capacitor also forms a low-pass filter with the output impedance
of the PGA (approximately 124 Ω), which helps to isolate noise
from the modulator engine. The capacitors should be of good
quality, such as NPO or polypropylene film, with values from
100 pF to 1 nF and should be connected to AGND.
The DAC has an output range of 0.5 V rms/1.414 V p-p about
a bias point equal to VREFCAP (see Figure 7).
V
REFCAP
VOUT
1.414V p-p
820ꢃ
2n2F
NPO
Figure 7. Typical Output Circuit
Low Group Delay
Peak Readback
The AD74111 can store the highest ADC value to facilitate level
adjustment of the input signal. Programming the Peak Enable
bit in Control Register E with a 1 will enable ADC Peak Level
Reading. The peak value is stored as a 6-bit number from 0 dB
to –63 dB in 1 dB steps. Reading Control Register F will give the
highest ADC value since the bit was set. The ADC peak register
is automatically cleared after reading.
It is possible to bypass much of the digital filtering by enabling
the Low Group Delay function in Control Register C. By reduc-
ing the amount of filtering the AD74111 applies to input and
output samples, the time delay between the sampling interval
and when the sample is available is greatly reduced. This can be
of benefit in applications such as telematics, where minimal
time delays are important. When the Low Group Delay function
is enabled, the sample rate becomes IMCLK/128.
Decimator Section
The digital decimation filter has a pass-band ripple of 0.2 mdB
and a stop-band attenuation of 120 dB. The filter is an FIR type
with a linear phase response. The group delay at 48 kHz is
910 µs. Output sample rates up to 48 kHz are supported.
Reference
The AD74111 features an on-chip reference whose nominal
value is 1.125 V. A 100 nF ceramic and 10 µF tantalum capacitor
applied at the REFCAP pin are necessary to stabilize the reference.
(See Figure 8.)
Input Signal Swing
The ADC input has an input range of 0.5 V rms/1.414 V p-p
about a bias point equal to VREFCAP. Figure 6 shows a typical
input filter circuit for use with the AD74111.
REFCAP
10ꢄF
0.1ꢄF
ꢅ
V
51ꢃ
10nF
AGND
VIN
1.414V p-p
47ꢄF
NPO
Figure 8. Reference Decoupling
If required, an external reference can be used as the reference
source of the ADC and DAC sections. This may be desirable in
situations where multiple devices are required to use the same
value of reference or because of a better temperature coefficient
specification. The internal reference can be disabled via Control
Register A and the external reference applied at the REFCAP
pin (see Figure 9). External references should be of a suitable
value such that the voltage swing of the inputs or outputs is not
affected by being too close to the power supply rails and should
be adequately decoupled.
Figure 6. Typical Input Circuit
DAC Section
The AD74111 DAC channel has a single-ended, analog output.
The DAC has independent software controllable Mute and Volume
Control functions. Control Register G controls the attenuation
factor for the DAC. This register is 10 bits wide, giving 1024
steps of attenuation. The AD74111 output channel employs a
multibit sigma-delta conversion technique that provides a high
quality output with system filtering implemented on-chip.
REV. 0
–9–
AD74111
Example 2: fSAMP = 44.1 kHz and 11.025 kHz Required
MCLK = 44.1 kHz ϫ 256 = 11.2896 MHz to provide 44.1 kHz fSAMP
.
1.125V
REFCAP
For fSAMP = 11.025 kHz, it is necessary to use the Ϭ1 setting in
Prescaler 1 and the Ϭ4 setting in Prescaler 2, and pass through
in Prescaler 3. This results in an IMCLK = 11.025 kHz ϫ 256
= 2.8224 MHz (= 11.2896 MHz/4).
EXTERNAL
REFERENCE
Figure 9. External Reference
Resetting the AD74111
Master Clocking Scheme
The AD74111 can be reset by bringing the RESET pin low.
Following a reset, the internal circuitry of the AD74111 ensures
that the internal registers are reset to their default settings and
the on-chip RAM is purged of previous data samples. The DIN
pin is sampled to determine if the AD74111 is required to
operate in Master or Slave mode. The reset process takes 3072
MCLK periods, and the user should not attempt to program the
AD74111 during this time.
The update rate of the AD74111’s ADC and DAC channels
requires an internal master clock (IMCLK) that is 256 times the
sample update rate (IMCLK = 256 ϫ fS). To provide some flex-
ibility in selecting sample rates, the device has a series of three
master clock prescalers that are programmable and allow the
user to choose a range of convenient sample rates from a single
external master clock. The master clock signal to the AD74111 is
applied at the MCLK pin. The MCLK signal is passed through
a series of three programmable MCLK prescaler (divider) circuits
that can be selected to reduce the resulting Internal MCLK
(IMCLK) frequency if required. The first and second MCLK
prescalers provide divider ratios of Ϭ1 (pass through), Ϭ2, Ϭ3;
while the third prescaler provides divider ratios of Ϭ1 (pass
through), Ϭ2, Ϭ4.
Power Supplies and Grounds
The AD74111 features three separate supplies: AVDD, DVDD1,
and DVDD2.
AVDD is the supply to the analog section of the device and must
be of sufficient quality to preserve the AD74111’s performance
characteristics. It is nominally a 2.5 V supply.
DVDD1 is the supply for the digital interface section of the device.
It is fed from the digital supply voltage of the DSP or controller
to which the device is interfaced and allows the AD74111
to interface with devices operating at supplies of between
2.5 V – 5% to 3.3 V + 10%.
PROGRAMMABLE MCLK DIVIDER
PRESCALER 1
PRESCALER 2
PRESCALER 3
/1
/2
/3
/1
/2
/4
/1
/2
/3
MCLK
IMCLK
DVDD2 is the supply for the digital core of the AD74111. It is
nominally a 2.5 V supply.
CONTROL REGISTER
Accessing the Internal Registers
The AD74111 has seven registers that can be programmed to
control the functions of the AD74111. Each register is 10 bits
wide and is written to or read from using a 16-bit write or read
operation, with the exception of Control Register F, which is
read-only. Table V shows the format of the data transfer operation.
The Control Word is made up of a Read/Write bit, the register
address, and the data to be written to the device. Note that in a
read operation the data field is ignored by the device. Access to
the control registers is via the serial port through one of the
operating modes described below.
Figure 10. MCLK Divider
The divider ratios allow a more convenient sample rate selection
from a common MCLK, which may be required in many voice
related applications. Control Register B should be programmed
to achieve the desired divider ratios.
Selecting Sample Rates
The sample rate at which the converter runs is always 256 times
the IMCLK rate. IMCLK is the Internal Master Clock and is the
output from the Master Clock Prescaler. The default sample rate
is 48 kHz (based on an external MCLK of 12.288 MHz). In this
mode, the ADC modulator is clocked at 3.072 MHz and the DAC
modulator is clocked at 6.144 MHz. Sample rates that are lower
than MCLK/256 can be achieved by using the MCLK prescaler.
Serial Port
The AD74111 contains a flexible serial interface port that is
used to program and read the control registers and to send and
receive DAC and ADC audio data. The serial port is compatible
with many popular DSPs and can be programmed to operate in
a variety of modes, depending on which one best suits the DSP
being used. The serial port can be set to operate as a Master or
Slave device, as discussed below. Figure 11 shows a timing
diagram of the serial port.
Example 1: fSAMP = 48 kHz and 8 kHz Required
MCLK = 48 kHz ϫ 256 = 12.288 MHz to provide 48 kHz fSAMP
.
For fSAMP = 8 kHz, it is necessary to use the Ϭ3 setting in
Prescaler 1, the Ϭ2 setting in Prescaler 2, and pass through
in Prescaler 3. This results in an IMCLK = 8 kHz ϫ 256 =
2.048 MHz (= 12.288 MHz/6).
–10–
REV. 0
AD74111
tFS
DFS
tFH
tCH
DCLK
tCL
tFD
MSB
MSB–1
MSB–2
DIN
tDS
tDH
MSB–1
MSB
MSB–2
DOUT
tDD
Figure 11. Serial Port (SPORT) Timing
Serial Port Operating Modes
Master Mode Operation
The serial port of the AD74111 can be programmed to operate
in a variety of modes depending on the requirements and flex-
ibility of the DSP to which it is connected. The two principal
modes of operation are Mixed mode and Data mode.
In Master mode, the DFS and DCLK pins are outputs from the
AD74111. This is the easiest mode in which to use the AD74111
because the correct timing relationship between sample rate,
DCLK, and DFS is controlled by the AD74111.
Mixed Mode
Slave Mode Operation
Mixed mode allows the control registers of the AD74111 to be
programmed and read back. It also allows data to be sent to the
DACs and data to be read from the ADCs. In Mixed mode,
there are separate data slots, each with its own frame synchroni-
zation signal (DFS) for control and DAC or ADC information.
The AD74111 powers up in Mixed mode by default to allow
the control registers to be programmed. Figure 13 shows the
default setting for Mixed mode.
In Slave mode, the DFS and DCLK pins are inputs to the
AD74111. Care needs to be exercised when designing a system
to operate the AD74111 in this mode as the relationship between
the sample rate, DCLK, and DFS needs to be controlled by the
DSP or other controller and must be compatible with the inter-
nal DAC/ADC engine of the AD74111. Figure 12 shows a block
diagram of the DAC engine and the AD74111’s serial port. The
sample rate for the DAC engine is determined by the MCLK
and MCLK prescalers. The DAC engine will read data from the
DAC Data register at this rate. It is therefore important that the
serial port is updated at the same rate, as any error between the
two will accumulate and eventually cause the DAC engine to have
to resynchronize with the serial port, which will cause erroneous
values on the DAC output pins.
Data Mode
Data mode can be used when programming or reading the
control registers is no longer required. Data mode provides a
frame synchronization (DFS) pulse for each sample of data.
Once the part has been programmed into Data mode, the only
way to change the control registers is to perform a hardware reset
to put the AD74111 back into Mixed mode. Figure 15 shows
the default setting for Data mode.
RESYNC*
DAC ENGINE
VOUT
Data-Word Length
LOAD DAT
The AD74111 can be programmed to send DAC audio data
and receive ADC audio data in different word length formats of
16, 20, or 24 bits. The default mode is 16 bits, but this can be
changed by programming Control Register C for the appropriate
word length.
DAC DATA REGISTER
SERIAL PORT
DFS
DIN
Selecting Master or Slave Mode
The initial operating mode of the AD74111 is determined by
the state of the DIN pin following a reset. If the DIN pin is high
during this time, Slave mode is selected. In Slave mode, the
DFS and DCLK pins are inputs and the control signals for
these pins must be provided by the DSP or other controller. If
the DIN pin is low immediately following a reset, the AD74111
will operate in Master mode.
*RESYNC IS ONLY USED WHEN THE DAC BECOMES
UNSYNCHRONIZED WITH THE SERIAL PORT
Figure 12. DAC Engine
In most cases, it is easy to keep a DSP in synchronization with
the AD74111 if they are both run from the same clock or the
DSP clock is a multiple of the AD74111’s MCLK. In this case,
REV. 0
–11–
AD74111
there will be a fixed relationship between the instruction cycle
time of the DSP program and the AD74111, so a timer could be
used to accurately control the DAC updates. If a timer is not
available, the Multiframe-Sync (MFS) mode could be used to
generate a DFS pulse every 16 or 32 DCLKs, allowing the DSP
to accurately control the number of DCLKs between updates
using an autobuffering or DMA type technique. In all cases for
Slave mode operation, there should be 128 DCLKs (Normal
mode) or 256 DCLKs (Fast mode) between DAC updates. The
ADC operates in a similar manner; however, if the DSP does not
read an ADC result, this will appear only as a missed sample and
will not be audible. Slave mode is most suited to state-machine
type applications where the number of DCLKs and their
relationships to the other interface signals can be controlled.
Table II. Serial Mode Selection
CRD:2 CRC:5, 4
CRD:3
DSP
Word
Operating
Mode
DM/MM Mode Width
Figure
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
16
16
16
>16
>16
>16
>16
16-Bit Data Mode
32-Bit Data Mode
16-Bit Mixed Mode 13
32-Bit Mixed Mode 17
16-Bit Data Mode
32-Bit Data Mode
15
19
16
20
16-Bit Mixed Mode 14
32-Bit Mixed Mode 18
1/fS
CONTROL
(16 BITS)
CONTROL
DAC
(16 BITS)
(16 BITS)
DAC
(16 BITS)
DIN
STATUS
STATUS
(16 BITS)
ADC
(16 BITS)
ADC
(16 BITS)
DOUT
(16 BITS)
DFS
(MM16)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 13. 16-Bit Mixed Mode, Word Length = 16 Bits
1/fS
DAC DATA
(24 BITS)
CONTROL
(16 BITS)
CONTROL
(16 BITS)
DIN
ADC DATA
(24 BITS)
STATUS
(16 BITS)
STATUS
(16 BITS)
DOUT
DFS
(MM16)
16 DCLKS
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 14. 16-Bit Mixed Mode, Word Length = 24 Bits
1/fS
DAC
(16 BITS)
DAC
(16 BITS)
DIN
ADC
(16 BITS)
ADC
(16 BITS)
DOUT
DFS
(MM16)
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 15. 16-Bit Data Mode, Word Length = 16 Bits
–12–
REV. 0
AD74111
1/fS
DAC DATA
(24 BITS)
DAC DATA
(24 BITS)
DIN
ADC DATA
(24 BITS)
ADC DATA
(24 BITS)
DOUT
DFS
(MM16)
16 DCLKs
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 16. 16-Bit Data Mode, Word Length = 24 Bits
1/fS
CONTROL
(16 BITS)
CONTROL
(16 BITS)
DAC DATA
(16 BITS)
DIN
STATUS
(16 BITS)
STATUS
(16 BITS)
ADC DATA
(16 BITS)
DOUT
DFS
32 DCLKs
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 17. 32-Bit Mixed Mode, Word Length = 16 Bits
1/fS
DAC DATA
(24 BITS)
CONTROL
(16 BITS)
CONTROL
(16 BITS)
DIN
ADC DATA
(24 BITS)
STATUS
(16 BITS)
STATUS
(16 BITS)
DOUT
DFS
32 DCLKS
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 18. 32-Bit Mixed Mode, Word Length = 24 Bits
1/fS
DAC DATA
(24 BITS)
DAC DATA
(16 BITS)
DIN
ADC DATA
(24 BITS)
ADC DATA
(16 BITS)
DOUT
DFS
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 19. 32-Bit Data Mode, Word Length = 16 Bits
–13–
REV. 0
AD74111
1/fS
DAC DATA
(24 BITS)
DAC DATA
(24 BITS)
DIN
ADC DATA
(24 BITS)
ADC DATA
(24 BITS)
DOUT
DFS
128 DCLKs (NORMAL MODE)
256 DCLKs (FAST MODE)
Figure 20. 32-Bit Data Mode, Word Length = 24 Bits
1/fS
32 DCLKs
DFS
DIN
C
S
DAC
C
S
DAC
ADC
ADC
DOUT
Figure 21. Multiframe Sync 32-Bit Mixed Mode
1/fS
32 DCLKs
DFS
DIN
DAC
ADC
DAC
ADC
DOUT
Figure 22. Multiframe Sync 32-Bit Data Mode
1/fS
16 DCLKS
DFS
DIN
C
S
DAC
ADC
C
S
DAC
DOUT
ADC
Figure 23. Multiframe Sync 16-Bit Mixed Mode
–14–
REV. 0
AD74111
1/fS
16 DCLKs
DFS
DIN
DAC
ADC
DAC
ADC
DOUT
Figure 24. Multiframe Sync 16-Bit Data Mode
Table III. Multiframe Sync Selection
CRD:9
MFS
CRD:3
DM/MM
CRC:2
DSP Mode
Operating Mode
Figure
1
1
1
1
0
0
1
1
0
1
0
1
16-Bit Data Mode
32-Bit Data Mode
16-Bit Mixed Mode
32-Bit Mixed Mode
24
22
23
21
Table IV. Control Register Map
Address (Binary)
Name
Description
Type
Width
Reset Setting
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
CRA
CRB
CRC
CRD
CRE
CRF
CRG
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Control Register F
Control Register G
R/W
R/W
R/W
R/W
R/W
R
10
10
10
10
10
10
10
00h
00h
00h
08h or 09h*
00h
00h
00h
R/W
*09h if DIN is low and 08h if DIN is high.
Table V. Control Word Descriptions
Bit
Field
Description
15
R/W
When this bit is high, the contents of the data field will be written to the register specified by the Address
Field. When this bit is low, a read of the register specified by the Address Field will occur at the next
sample interval; the contents of the Data Field are ignored.
14–11 Register Address This 4-bit field is used to select one of the seven control registers of the AD74111.
10
Reserved
This bit is reserved and should always be programmed with zero.
9–0
Data Field
This 10-bit field holds the data that is to be written to or read from the register specified in the Address Field.
REV. 0
–15–
AD74111
Table VI. Control Register A
Function
ADC Input
Amplifier
Reference
Amplifier Reserved
R/W
ADDRESS
RES
Reserved
ADC
DAC
Reference
15
14, 13, 12, 11
0000
10
9, 8, 7
6
5
4
3
2
1, 0
0
1
0
0
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
Table VII. Control Register B
Function
Second MCLK
Third MCLK
Divider
First MCLK
Divider
R/W
ADDRESS
RES
Reserved
Divider
15
14, 13, 12, 11
0001
10
9, 8, 7, 6
0
5, 4
3, 2
1, 0
1
0
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 1
00 = Divide by 1
01 = Divide by 2
10 = Divide by 3
11 = Divide by 1
00 = Divide by 1
01 = Divide by 2
10 = Divide by 3
11 = Divide by 1
Table VIII. Control Register C
Function
Low Group
DAC and ADC
Word Width
DAC
De-emphasis
ADC High-
Pass Filter
R/W
ADDRESS
14, 13, 12, 11
RES
Reserved
Delay
15
1
10
0
9, 8, 7, 6
0
5, 4
3
2, 1
0
0010
00 = 16 Bits
01 = 20 Bits
10 = 24 Bits
11 = 24 Bits
0 = Disabled
1 = Enabled
00 = None
0 = Disabled
1 = Enabled
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
Table IX. Control Register D
Function
Master/
R/W
ADDRESS
RES
Multiframe Sync
Reserved
DM/MM
DSP Mode Fast DCLK Slave
15
14, 13, 12, 11 10
0011
9
8, 7, 6, 5, 4
3
2
1
0
1
0
0 = Normal Mode
1 = MFS Mode
0
0 = Data Mode
1 = Mixed Mode 1 = 32 Bits
0 = 16 Bits
0 = 128 ϫ fS 0 = Slave
1 = 256 ϫ fS 1 = Master
–16–
REV. 0
AD74111
Table X. Control Register E
ADCL Peak
Function
ADC
Mute
DAC
Mute
R/W
ADDRESS
RES
Reserved
Enable
ADC Gain
15
14, 13, 12, 11
10
9, 8, 7, 6
0
5
4, 3, 2
1
0
1
0100
0
0 = Disabled
1 = Peak Enable
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
1XX = 12 dB
0 = Normal
1 = Mute
0 = Normal
1 = Mute
Table XI. Control Register F
Function
R/W
ADDRESS
RES
Reserved
ADC Input Peak Level
15
14, 13, 12, 11
10
9, 8, 7, 6
5, 4, 3, 2, 1, 0
000000 = 0 dBFS
000001 = –1 dBFS
000010 = –2 dBFS
111110 = –62 dBFS
111111 = –63 dBFS
0
0101
0
0
Table XII. Control Register G
Function
R/W
ADDRESS
RES
DAC Volume
15
14, 13, 12, 11
10
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
0000000000 = 0 dBFS
0000000001 = (1023/1024) dBFS
0000000010 = (1022/1024) dBFS
1111111110 = (2/1024) dBFS
1111111111 = Mute
1
0110
0
REV. 0
–17–
AD74111
OUTLINE DIMENSIONS
16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8ꢆ
0ꢆ
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
–18–
REV. 0
–19–
–20–
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