AD745JR-16-REEL [ROCHESTER]
OP-AMP, 1500 uV OFFSET-MAX, 20 MHz BAND WIDTH, PDSO16, SOIC-16;
| 型号： | AD745JR-16-REEL |
| 厂家： | 
Rochester Electronics |
| 描述： | OP-AMP, 1500 uV OFFSET-MAX, 20 MHz BAND WIDTH, PDSO16, SOIC-16 光电二极管 |
| 文件： | 总14页 (文件大小：1026K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise,
High Speed, BiFET Op Amp
a
AD745
FEATURES
CO NNECTIO N D IAGRAMS
ULTRALOW NOISE PERFORMANCE
2.9 nV/ ͙Hz at 10 kHz
0.38 V p-p, 0.1 Hz to 10 Hz
6.9 fA/ ͙Hz Current Noise at 1 kHz
8-P in P lastic Mini-D IP (N) &
8-P in Cerdip (Q) P ackages
16-P in SO IC (R) P ackage
NC
1
16 NC
15 NC
14 NC
OFFSET
NULL
OFFSET
NULL
1
8
NC
+V
2
AD745
EXCELLENT AC PERFORMANCE
12.5 V/ s Slew Rate
20 MHz Gain Bandw idth Product
THD = 0.0002% @ 1 kHz
Internally Com pensated for Gains of +5 (or –4) or
Greater
– IN
2
3
4
7
6
5
S
– IN
3
4
5
6
7
8
AD745
TOP VIEW
+IN
OUTPUT
NC
13
+V
S
OFFSET
NULL
–V
S
+IN
12 OUTPUT
OFFSET
11
–V
S
NULL
NC
NC
TOP VIEW
10 NC
NC = NO CONNECT
EXCELLENT DC PERFORMANCE
0.5 m V m ax Offset Voltage
9
NC
250 pA m ax Input Bias Current
2000 V/ m V m in Open Loop Gain
Available in Tape and Reel in Accordance w ith
EIA-481A Standard
T he AD745’s guaranteed, tested maximum input voltage noise
of 4 nV/√Hz at 10 kHz is unsurpassed for a FET -input mono-
lithic op amp, as is its maximum 1.0 µV p-p noise in a 0.1 Hz to
10 Hz bandwidth. T he AD745 also has excellent dc perfor-
mance with 250 pA maximum input bias current and 0.5 mV
maximum offset voltage.
APPLICATIONS
Sonar
Photodiode and IR Detector Am plifiers
Accelerom eters
T he internal compensation of the AD745 is optimized for
higher gains, providing a much higher bandwidth and a faster
slew rate. T his makes the AD745 especially useful as a
preamplifier where low level signals require an amplifier that
provides both high amplification and wide bandwidth at these
higher gains. T he AD745 is available in five performance
grades. T he AD745J and AD745K are rated over the
commercial temperature range of 0°C to +70°C. T he AD745A
and AD745B are rated over the industrial temperature range of
–40°C to +85°C. T he AD745S is rated over the military
temperature range of –55°C to +125°C and is available
processed to MIL-ST D-883B, Rev. C.
Low Noise Pream plifiers
High Perform ance Audio
P RO D UCT D ESCRIP TIO N
T he AD745 is an ultralow noise, high speed, FET input
operational amplifier. It offers both the ultralow voltage noise
and high speed generally associated with bipolar input op amps
and the very low input currents of FET input devices. Its 20
MHz bandwidth and 12.5 V/µs slew rate makes the AD745 an
ideal amplifier for high speed applications demanding low noise
and high dc precision. Furthermore, the AD745 does not
exhibit an output phase reversal.
T he AD745 is available in 8-pin plastic mini-DIP, 8-pin cerdip,
16-pin SOIC, or in chip form.
1000
R
SOURCE
OP37 &
RESISTOR
( — )
120
100
80
120
100
80
E
O
R
SOURCE
100
10
1
PHASE
AD745 & RESISTOR
OR
AD745 + RESISTOR
60
60
(
)
OP37 & RESISTOR
GAIN
40
40
20
20
0
RESISTOR NOISE ONLY
(– – –)
0
1k
10k
100k
1M
10M
100
SOURCE RESISTANCE – Ω
–20
–20
10M 100M
REV. C
100
1k
10k
100k
FREQUENCY – Hz
1M
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD745–SPECIFICATIONS
(@ +25؇C and ؎15 V dc, unless otherwise noted)
Model
AD 745J/A
Conditions
Min
Typ
Max
Units
INPUT OFFSET VOLT AGE1
Initial Offset
Initial Offset
vs. T emp.
vs. Supply (PSRR)
vs. Supply (PSRR)
0.25
1.0/0.8
1.5
mV
mV
µV/°C
dB
T MIN to T MAX
T MIN to T MAX
12 V to 18 V2
T MIN to T MAX
2
96
90
88
dB
INPUT BIAS CURRENT 3
Either Input
VCM = 0 V
150
400
pA
Either Input
@ T MAX
Either Input
Either Input, VS = ±5 V
VCM = 0 V
VCM = +10 V
VCM = 0 V
8.8/25.6
600
200
nA
pA
pA
250
30
INPUT OFFSET CURRENT
Offset Current
VCM = 0 V
VCM = 0 V
40
150
pA
nA
@ T MAX
2.2/6.4
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate
G = –4
VO = 20 V p-p
G = –4
20
MHz
kHz
V/µs
µs
120
12.5
5
Settling T ime to 0.01%
T otal Harmonic
f = 1 kHz
G = –4
Distortion4
0.0002
%
INPUT IMPEDANCE
Differential
Common Mode
1 × 1010ʈ20
3 × 1011ʈ18
ΩʈpF
ΩʈpF
INPUT VOLT AGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode
±20
+13.3, –10.7
V
V
V
–10
+12
Rejection Ratio
VCM = ±10 V
T MIN to T MAX
80
78
95
dB
dB
INPUT VOLT AGE NOISE
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
0.38
5.5
3.6
3.2
2.9
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
5.0
4.0
f = 10 kHz
INPUT CURRENT NOISE
OPEN LOOP GAIN
f = 1 kHz
6.9
fA/√Hz
VO = ±10 V
RLOAD ≥ 2 kΩ
T MIN to T MAX
RLOAD = 600 Ω
1000
800
4000
1200
V/mV
V/mV
V/mV
OUT PUT CHARACT ERIST ICS
Voltage
RLOAD ≥ 600 Ω
RLOAD ≥ 600 Ω
T MIN to T MAX
RLOAD ≥ 2 kΩ
Short Circuit
+13, –12
V
+13.6, –12.6
V
V
+12, –10
±12
20
V
+13.8, –13.1
40
Current
mA
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
±15
8
V
V
mA
±4.8
±18
10.0
T RANSIST OR COUNT
NOT ES
# of T ransistors
50
1Input offset voltage specifications are guaranteed after 5 minutes of operations at T A = +25°C.
2T est conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to +18 V, –VS = 15 V.
3Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperature, the current doubles every 10°C.
4Gain = –4, RL = 2 kΩ, CL = 10 pF.
5Defined as voltagc between inputs, such that neither exceeds ±10 V from common.
6T he AD745 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. C
AD745
ESD SUSCEP TIBILITY
ABSO LUTE MAXIMUM RATINGS1
An ESD classification per method 3015.6 of MIL-ST D-883C
has been performed on the AD745, which is a class 1 device.
Using an IMCS 5000 automated ESD tester, the two null pins
will pass at voltages up to 1000 volts, while all other pins will
pass at voltages exceeding 2500 volts.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Cerdip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage T emperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage T emperature Range (N, R) . . . . . . . –65°C to +125°C
Operating T emperature Range
AD745J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD745A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD745S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . . +300°C
NOT ES
O RD ERING GUID E
P ackage
Model
Tem perature Range
O ption*
AD745JN
AD745AN
AD745JR-16
0°C to +70°C
–40°C to +85°C
0°C to +70°C
N-8
N-8
R-16
*N = Plastic DIP; R = Small Outline IC.
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
28-Pin Plastic Package: θJA = 100°C/W, θJC = 50°C/W
8-Pin Cerdip Package: θJA = 110°C/W, θJC = 30°C/W
8-Pin Plastic SOIC Package: θJA = 100°C/W, θJC = 30°C/W
METALIZATIO N P H O TO GRAP H
D imensions shown in inches and (mm).
REV. C
–3–
(@ + 25؇C, V = ؎15 V unless otherwise noted)
AD745
–Typical Characteristics
S
20
20
15
10
5
35
R
= 10kΩ
R
= 10kΩ
LOAD
LOAD
30
25
20
15
15
10
5
POSITIVE
SUPPLY
+V
IN
NEGATIVE
SUPPLY
–V
IN
10
5
0
0
0
0
5
10
15
20
0
100
LOAD RESISTANCE – Ω
10k
10
1k
10
15
20
5
+
SUPPLY VOLTAGE VOLTS
+
–
SUPPLY VOLTAGE VOLTS
–
Figure 2. Output Voltage Swing vs.
Supply Voltage
Figure 3. Output Voltage Swing vs.
Load Resistance
Figure 1. Input Voltage Swing vs.
Supply Voltage
10 –6
12
9
200
100
10–7
10–8
10
10–9
6
3
0
1
10–10
CLOSED-LOOP GAIN = –5
0.1
10–11
10–12
0.01
80 100 120 140
–60 –40 –20
20 40 60
0
10k
100k
1M
10M
100M
5
10
0
15
20
TEMPERATURE – °C
FREQUENCY – Hz
SUPPLY VOLTAGE ± VOLTS
Figure 5. Input Bias Current vs.
Tem perature
Figure 6. Output Im pedance vs.
Frequency
Figure 4. Quiescent Current vs.
Supply Voltage
80
70
300
200
100
0
28
26
24
60
+ OUTPUT
CURRENT
50
22
20
18
16
14
40
30
– OUTPUT
CURRENT
20
10
0
– 60 – 40
0
20 40 60 80 100 120 140
– 20
–60 –40 –20
20
0
40 60 80 100 120 140
–9
–6
–3
3
6
9
12
–12
0
TEMPERATURE – °C
TEMPERATURE –
C
COMMON-MODE VOLTAGE – Volts
Figure 8. Short Circuit Current Lim it
vs. Tem perature
Figure 9. Gain Bandwidth Product
vs. Tem perature
Figure 7. Input Bias Current vs.
Com m on-Mode Voltage
–4–
REV. C
AD745
Typical Characteristics–
120
14
12
120
100
150
RL = 2kΩ
100
80
140
PHASE
80
60
40
20
0
130
120
100
60
GAIN
CLOSED-LOOP GAIN = +5
40
10
8
20
0
–20
100
–20
10M 100M
80
10
15
20
1k
10k
100k
1M
0
5
–60 –40 –20
0
20 40 60 80 100 120 140
SUPPLY VOLTAGE ± VOLTS
FREQUENCY – Hz
TEMPERATURE – °C
Figure 10. Open-Loop Gain and
Phase vs. Frequency
Figure 11. Slew Rate vs.
Tem perature
Figure 12. Open-Loop Gain vs.
Supply Voltage
120
110
100
90
120
100
80
35
30
25
20
15
10
+ SUPPLY
R
= 2kΩ
L
60
40
20
0
– SUPPLY
80
Vcm = ±10V
70
60
50
5
0
1k
100
10k
100k
1M
10M
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14. Power Supply Rejection
vs. Frequency
Figure 13. Com m on-Mode Rejection
vs. Frequency
Figure 15. Large Signal Frequency
Response
1.0
–40
–60
–80
1k
100
0.1
CLOSED-LOOP GAIN = +5
10
100
0.01
GAIN = +10
–100
0.001
10
GAIN = +100
1.0
0.1
0.0001
0.00001
–120
–140
GAIN = –4
1k
1.0
10
100
10k
100k
1
100
1k
10k
100k
10
10
100
1k
10k 100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Total Harm onic Distortion
vs. Frequency
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Input Noise Current
Spectral Density
REV. C
–5–
AD745
–Typical Characteristics
72
648
594
+V
S
1µF
0.1µF
TOTAL UNITS = 760
66
60
54
48
42
36
30
24
18
12
6
+
540
486
432
378
TOTAL UNITS = 4100
2
7
6
324
270
216
162
108
54
AD745
5
1
3
2MΩ
V
4
OS
ADJUST
1µF
0.1µF
1MΩ
+
0
–15
0
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
INPUT VOLTAGE NOISE @ 10kHz – nV/√ Hz
–10
–5
0
5
10
15
–V
S
INPUT OFFSET VOLTAGE DRIFT – µV/ oC
Figure 21. Offset Null Configuration,
8-Pin Package Pinout
Figure 19. Distribution of Offset
Voltage Drift. TA = +25°C to +125°C
Figure 20. Typical Input Noise
Voltage Distribution @ 10 kHz
+V
S
0.1µF
V
IN
3
2
7
2µs
500nS
V
OUT
100
90
100
90
AD745
6
SQUARE
WAVE
C
L
INPUT
4
10pF
0.1µF
–V
S
10
10
2kΩ
20pF
0%
0%
50mV
5V
499Ω
Figure 22a. Gain of 5 Follower,
8-Pin Package Pinout
Figure 22b. Gain of 5 Follower
Large Signal Pulse Response
Figure 22c. Gain of 5 Follower Sm all
Signal Pulse Response
20pF
2kΩ
500nS
2µs
100
90
100
90
+V
S
0.1
µF
499Ω
7
2
3
V
V
OUT
IN
AD745
6
10
10
C
SQUARE
WAVE
INPUT
L
0%
0%
4
0.1µF
10pF
50mV
5V
–V
S
Figure 23a. Gain of 4 Inverter,
8-Pin Package Pinout
Figure 23b. Gain of 4 Inverter Large
Signal Pulse Response
Figure 23c. Gain of 4 Inverter Sm all
Signal Pulse Response
–6–
REV. C
AD745
O P AMP P ERFO RMANCE JFET VS. BIP O LAR
D ESIGNING CIRCUITS FO R LO W NO ISE
T he AD745 offers the low input voltage noise of an industry
standard bipolar op amp without its inherent input current
errors. T his is demonstrated in Figure 24, which compares
input voltage noise vs. input source resistance of the OP37 and
the AD745 op amps. From this figure, it is clear that at high
source impedance the low current noise of the AD745 also
provides lower total noise. It is also important to note that with
the AD745 this noise reduction extends all the way down to low
source impedances. T he lower dc current errors of the AD745
also reduce errors due to offset and drift at high source
impedances (Figure 25).
An op amp’s input voltage noise performance is typically
divided into two regions: flatband and low frequency noise. T he
AD745 offers excellent performance with respect to both. T he
figure of 2.9 nV/͙Hz @ 10 kHz is excellent for a JFET input
amplifier. T he 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p.
T he user should pay careful attention to several design details in
order to optimize low frequency noise performance. Random air
currents can generate varying thermocouple voltages that appear
as low frequency noise: therefore sensitive circuitry should be
well shielded from air flow. Keeping absolute chip temperature
low also reduces low frequency noise in two ways: first, the low
frequency noise is strongly dependent on the ambient temperature
and increases above +25°C. Secondly, since the gradient of
temperature from the IC package to ambient is greater, the
noise generated by random air currents, as previously mentioned,
will be larger in magnitude. Chip temperature can be reduced
both by operation at reduced supply voltages and by the use of a
suitable clip-on heat sink, if possible.
T he internal compensation of the AD745 is optimized for
higher gains, providing a much higher bandwidth and a faster
slew rate. T his makes the AD745 especially useful as a
preamplifier, where low level signals require an amplifier that
provides both high amplification and wide bandwidth at these
higher gains.
1000
Low frequency current noise can be computed from the
OP37 &
RESISTOR
( — )
~
R
SOURCE
=
2qIB∆f
and increases
In
magnitude of the dc bias current
below approximately 100 Hz with a 1/f power spectral density.
E
O
For the AD745 the typical value of current noise is 6.9 fA/√Hz
~
R
100
SOURCE
at 1 kHz. Using the formula,
, to compute the
4kT/R∆f
I n
=
Johnson noise of a resistor, expressed as a current, one can see
that the current noise of the AD745 is equivalent to that of a
3.45 × 108 Ω source resistance.
AD745 & RESISTOR
AD745 + RESISTOR
OR
)
(
OP37 & RESISTOR
At high frequencies, the current noise of a FET increases
proportionately to frequency. T his noise is due to the “real” part
of the gate input impedance, which decreases with frequency.
T his noise component usually is not important, since the voltage
noise of the amplifier impressed upon its input capacitance is an
apparent current noise of approximately the same magnitude.
10
RESISTOR NOISE ONLY
(– – –)
1
100
10M
1M
10k
SOURCE RESISTANCE – Ω
1k
100k
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. T his noise is
totally correlated at the inputs, so source impedance matching
will tend to cancel out its effect. Both input resistance and input
capacitance should be balanced whenever dealing with source
capacitances of less than 300 pF in value.
Figure 24. Total Input Noise Spectral Density @ 1 kHz
vs. Source Resistance
100
ADOP37G
LO W NO ISE CH ARGE AMP LIFIERS
As stated, the AD745 provides both low voltage and low current
noise. T his combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
10
1.0
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships:
AD745 KN
dQ
Q = CV and I =
dt
0.1
As shown, voltage, current and charge noise can all be directly
related. T he change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built-in charge (Q/∆C).
100
1M
SOURCE RESISTANCE – Ω
10M
1k
10k
100k
Figure 25. Input Offset Voltage vs. Source Resistance
REV. C
–7–
AD745
Figures 26 and 27 show two ways to buffer and amplify the
output of a charge output transducer. Both require using an
amplifier which has a very high input impedance, such as the
AD745. Figure 26 shows a model of a charge amplifier circuit.
Here, amplification depends on the principle of conservation of
charge at the input of amplifier A1, which requires that the
charge on capacitor CS be transferred to capacitor CF, thus
yielding an output voltage of ∆Q/CF. T he amplifiers input
voltage noise will appear at the output amplified by the noise
gain (1 + (CS/CF)) of the circuit.
Figure 28 shows that these two circuits have an identical
frequency response and the same noise performance (provided
that CS/CF = R1/ R2). One feature of the first circuit is that a
“T ” network is used to increase the effective resistance of RB
and improve the low frequency cutoff point by the same factor.
–100
–110
–120
–130
–140
TOTAL OUTPUT
–150
C
F
NOISE
–160
–170
–180
R
R 1
B
R 2
–190
NOISE DUE TO
–200
R
ALONE
B
NOISE DUE TO
ALONE
–210
–220
I
B
0.01
1k
0.1
1
10
100
10k
100k
C
FREQUENCY – Hz
S
A1
Figure 28. Noise at the Outputs of the Circuits of Figures
26 and 27. Gain = 10, CS = 3000 pF, RB = 22 MΩ
R1
C
S
R
C
*
*
B
B
=
R2
C
F
However, this does not change the noise contribution of RB
which, in this example, dominates at low frequencies. T he
graph of Figure 29 shows how to select an RB large enough to
minimize this resistor’s contribution to overall circuit noise.
When the equivalent current noise of RB ((͙4 kT)/R) equals
Figure 26. A Charge Am plifier Circuit
R1
C *
B
IB 2qIB
the noise of
RB larger.
, there is diminishing return in making
(
)
10
5.2 x 10
*
R
B
R2
A2
9
8
C
S
5.2 x 10
R
B
*OPTIONAL, SEE TEXT
5.2 x 10
Figure 27. Model for A High Z Follower with Gain
T he second circuit, Figure 27, is simply a high impedance
follower with gain. Here the noise gain (1 + (R1/R2)) is the
same as the gain from the transducer to the output. Resistor RB,
in both circuits, is required as a dc bias current return.
7
5.2 x 10
5.2 x 10
6
T here are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current
noise, while resistor RB contributes a current noise of:
1pA
10pA
INPUT BIAS CURRENT
10nA
100pA
1nA
Figure 29. Graph of Resistance vs. Input Bias Current
Where the Equivalent Noise ͙4 kT/R, Equals the Noise
T
RB
~
=
4 k
∆f
N
IB 2qIB
of the Bias Current
(
)
where:
T o maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
T his is represented by the optional resistor RB in Figures 26 and
27. As previously mentioned, for best noise performance care
should be taken to also balance the source capacitance
designated by CB T he value for CB in Figure 26 would be equal
to CS in Figure 27. At values of CB over 300 pF, there is a
diminishing impact on noise; capacitor CB can then be simply a
large mylar bypass capacitor of 0.01 µF or greater.
k = Boltzman’s Constant = 1.381 × 10–23 Joules/Kelvin
T = Absolute T emperature, Kelvin (0°C = +273.2 Kelvin)
∆f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall”
Filter)
T his must be root-sum-squared with the amplifier’s own
current noise.
–8–
REV. C
AD745
H O W CH IP P ACKAGE TYP E AND P O WER D ISSIP ATIO N
AFFECT INP UT BIAS CURRENT
300
200
As with all JFET input amplifiers, the input bias current of the
AD745 is a direct function of device junction temperature, IB
approximately doubling every 10°C. Figure 30 shows the
relationship between bias current and junction temperature for
the AD745. T his graph shows that lowering the junction
temperature will dramatically improve IB.
T = +25°C
A
θ
= 165°C/W
JA
–6
10
= 115°C/W
θ
JA
100
–7
10
+
= 15V
-
= +25°C
V
S
T
A
= 0°C/W
θ
JA
–8
10
10
10
0
10
SUPPLY VOLTAGE – ±Volts
5
15
–9
Figure 32. Input Bias Current vs. Supply Voltage for
–10
Various Values of θJ A
T
J
–11
10
–12
θ
A
10
20
40 60
80 100 120 140
–60
–20
0
–40
(J TO
JUNCTION TEMPERATURE – °C
DIE MOUNT)
θ
B
Figure 30. Input Bias Current vs. J unction Tem perature
(DIE MOUNT
TO CASE)
T
A
T he dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 31 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (θ in °C/watt).
+
θ
=
θ
θ
A
B
JC
CASE
θ
T
θ
JC
J
CA
Figure 33. Breakdown of Various Package Therm al
Resistance
θ
JA
T
P
A
IN
RED UCED P O WER SUP P LY O P ERATIO N FO R
LO WER IB
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and, second, by
reducing the basic gate-to-junction leakage (Figure 32). Figure
34 shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40°C to
+85°C temperature range. If the optional coupling capacitor,
C1, is used, this circuit will operate over the entire –55°C to
+125°C temperature range.
WHERE:
P
= DEVICE DISSIPATION
= AMBIENT TEMPERATURE
= JUNCTION TEMPERATURE
= THERMAL RESISTANCE – JUNCTION TO CASE
= THERMAL RESISTANCE – CASE TO AMBIENT
IN
T
A
T
θ
J
JC
θ
CA
Figure 31. Device Therm al Model
From this model TJ = T A+θJA PIN. T herefore, IB can be
determined in a particular application by using Figure 30
together with the published data for θJA and power dissipation.
T he user can modify θJA by use of an appropriate clip-on heat
sink such as the Aavid # 5801. θJA is also a variable when using
the AD745 in chip form. Figure 32 shows bias current vs.
supply voltage with θJA as the third variable. T his graph can be
used to predict bias current after θJA has been computed. Again
bias current will double for every 10°C. T he designer using the
AD745 in chip form (Figure 33) must also be concerned with
both θJC and θCA, since θJC can be affected by the type of die
mount technology used.
100Ω
10kΩ
C1*
CT**
+5V
108
**
Ω
AD745
TRANSDUCER
C
T
–5V
108
Ω
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEE TEXT
T ypically, θJC’s will be in the 3°C to 5°C/watt range; therefore,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate, θJC will dominate
proportionately more of the total θJA.
Figure 34. A Piezoelectric Transducer
REV. C
–9–
AD745
A dc servo loop (Figure 35b) can be used to assure a dc output
<10 mV, without the need for a large compensating resistor
when dealing with bias currents as large as 100 nA. For optimal
low frequency performance, the time constant of the servo loop
(R4C2 = R5C3) should be:
TWO H IGH P ERFO RMANCE ACCELERO METER
AMP LIFIERS
T wo of the most popular charge-out transducers are hydro-
phones and accelerometers. Precision accelerometers are typi-
cally calibrated for a charge output (pC/g).* Figures 35a and
35b show two ways in which to configure the AD745 as a low
noise charge amplifier for use with a wide variety of piezoelectric
accelerometers. T he input sensitivity of these circuits will be de-
termined by the value of capacitor C1 and is equal to:
R2
R3
Time Constant ≥10 R1 1+
C1
A LO W NO ISE H YD RO P H O NE AMP LIFIER
∆QOUT
C1
Hydrophones are usually calibrated in the voltage-out mode.
T he circuit of Figures 36a can be used to amplify the output of
a typical hydrophone. If the optional ac coupling capacitor CC is
used, the circuit will have a low frequency cutoff determined by
an RC time constant equal to:
∆VOUT
=
T he ratio of capacitor C1 to the internal capacitance (CT ) of the
transducer determines the noise gain of this circuit (1 + CT /C1).
T he amplifiers voltage noise will appear at its output amplified
by this amount. T he low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a “T ” network
is used, the effective value is: R1 (1 + R2/R3).
1
Time Constant =
2π × CC × 100 Ω
where the dc gain is 1 and the gain above the low frequency
cutoff (1/(2π CC(100 Ω))) is equal to (1 + R2/R3). T he circuit
of Figure 36b uses a dc servo loop to keep the dc output at 0 V
and to maintain full dynamic range for IB’s up to 100 nA. T he
time constant of R7 and C1 should be larger than that of R1
and CT for a smooth low frequency response.
*pC = Picocoulombs
g = Earth’s Gravitational Constant
C1 1250pF
R2
R1
110MΩ
9kΩ
(5x22MΩ)
1900Ω
1kΩ
R3
R3
R2
100Ω
R4*
C1*
C
C
AD745
B&K MODEL
4370 OR
EQUIVALENT
B&K TYPE 8100 HYDROPHONE
OUTPUT
AD745
OUTPUT
0.8mV/pC
C
T
108
R1
Ω
INPUT SENSITIVITY = –179dB RE. 1V/µPa**
*OPTIONAL, SEE TEXT
** 1 VOLT PER MICROPASCAL
Figure 35a. A Basic Accelerom eter Circuit
Figure 36a. A Low Noise Hydrophone Am plifier
C1 1250pF
T he transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), lowest noise can be
achieved by adding a parallel RC network (R4 = R1, C1 = CT )
in series with the inverting input of the AD745.
R2
R1
110MΩ
9kΩ
(5x22MΩ)
1kΩ
R3
1900Ω
C2
2.2µF
R3
100Ω
R2
108
R4*
Ω
18MΩ
C1*
OUTPUT
R4
R5
AD711
16MΩ
18MΩ
2.2µF
AD745
R4
C3
0.27µF
C2
AD745
B&K MODEL
4370 OR
EQUIVALENT
108
Ω
R1
B&K TYPE
8100
HYDROPHONE
OUTPUT = 0.8mV/pC
R5
AD711K
100kΩ
R6
1MΩ
C
T
16MΩ
*pC = PICOCOULOMBS
g = EARTH'S GRAVITATIONAL CONSTANT
DC OUTPUT ≤ 1mV FOR I (AD745) ≤ 100nA
B
*OPTIONAL, SEE TEXT
Figure 35b. An Accelerom eter Circuit Em ploying a DC
Servo Am plifier
Figure 36b. A Hydrophone Am plifier Incorporating a DC
Servo Loop
–10–
REV. C
AD745
1µF
+
D esign Consider ations for I-to-V Conver ter s
T here are some simple rules of thumb when designing an I-V
converter where there is significant source capacitance (as with a
photodiode) and bandwidth needs to be optimized. Consider the
circuit of Figure 37. T he high frequency noise gain (1 + CS/CL)
is usually greater than five, so the AD745, with its higher slew
rate and bandwidth is ideally suited to this application.
+12V
0.01
µF
16
15
14
13
12
11
10
9
1
2
–12V
0.01µF
+12V
AD1862
20 BIT D/A
CONVERTER
0.1µF
OUTPUT
3
4
5
6
0.01
µF
ANALOG
COMMON
10µF
+
Here both the low current and low voltage noise of the AD745
can be taken advantage of, since it is desirable in some instances
to have a large RF (which increases sensitivity to input current
noise) and, at the same time, operate the amplifier at high noise
gain.
+12V
3 POLE
LOW
PASS
AD745
0.1µF
DIGITAL
INPUTS
3kΩ
FILTER
7
8
–12V
TOP VIEW
R
F
–12V
100pF
INPUT SOURCE: PHOTO DIODE,
ACCELEROMETER, ECT.
0.01µF
DIGITAL
COMMON
2000pF
C
L
AD745
R
B
I
C
S
S
Figure 38. A High Perform ance Audio DAC Circuit
An important feature of this circuit is that high frequency
energy, such as clock feedthrough, is shunted to common via a
high quality capacitor and not the output stage of the amplifier,
greatly reducing the error signal at the input of the amplifier and
subsequent opportunities for intermodulation distortions.
Figure 37. A Model for an l-to-V Converter
In this circuit, the RF CS time constant limits the practical
bandwidth over which flat response can be obtained, in fact:
40
fC
f B
≈
2π RF CS
30
where:
fB = signal bandwidth
UNBALANCED
20
fC = gain bandwidth product of the amplifier
With CL ≈ 1/(2 π RF CS) the net response can be adjusted to a
provide a two pole system with optimal flatness that has a corner
frequency of fB. Capacitor CL adjusts the damping of the
circuit’s response. Note that bandwidth and sensitivity are
directly traded off against each other via the selection of RF. For
example, a photodiode with CS = 300 pF and RF = 100 kΩ will
have a maximum bandwidth of 360 kHz when capacitor
CL ≈ 4.5 pF. Conversely, if only a 100 kHz bandwidth were
required, then the maximum value of RF would be 360 kΩ and
that of capacitor CL still ≈ 4.5 pF.
BALANCED
2.9nV/ Hz
10
0
√
10
100
INPUT CAPACITANCE – pF
1000
Figure 39. RTI Noise Voltage vs. Input Capacitance
BALANCING SO URCE IMP ED ANCES
In either case, the AD745 provides impedance transformation,
the effective transresistance, i.e., the I/V conversion gain, may be
augmented with further gain. A wideband low noise amplifier
such as the AD829 is recommended in this application.
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD745. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 39, noise
performance will be optimized. Figure 40 shows the required
external components for noninverting (A) and inverting (B)
configurations.
T his principle can also be used to apply the AD745 in a high
performance audio application. Figure 38 shows that an I-V
converter of a high performance DAC, here the AD1862, can be
designed to take advantage of the low voltage noise of the
AD745 (2.9 nV/͙Hz) as well as the high slew rate and
bandwidth provided by decompensation. T his circuit, with
component values shown, has a 12 dB/octave rolloff at 728 kHz,
with a passband ripple of less than 0.001 dB and a phase
deviation of less than 2 degrees @ 20 kHz.
REV. C
–11–
AD745
R
1
C
R
= C II C
S
C F
B
F
C
R
FOR
= C
= R
B
B
S
S
= R II R
C
B
1 S
B
R
1
R
>> R OR R
S
R
C
1
2
B
OUTPUT
OUTPUT
AD745
C
S
AD745
R
S
R
2
C
B
S
R
INVERTING
CONNECTION
B
R
NONINVERTING
CONNECTION
S
Figure 40. Optional External Com ponents for Balancing Source Im pedances
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic Mini-D IP (N) P ackage
8
5
4
0.31
0.25
(7.87)
(6.35)
1
0.39 (9.91)
MAX
0.30 (7.62)
REF
+
0.035 0.01
-
+
+
(0.89 0.25)
0.165 0.01
-
-
+
(4.19 0.25)
-
SEATING
PLANE
+
0.011 0.003
-
0.125 (3.18)
MIN
+
(0.28 0.08)
-
+
0.18 0.03
+
0.100
-
0
- 15
O.018 0.003
-
+
(4.57 0.76)
+
(2.54)
TYP
-
(0.46 0.08)
-
8-P in Cer dip (Q ) P ackage
16-P in SO IC (R) P ackage
0.005 (0.13) MIN
0.055 (1.35) MAX
16
1
9
8
8
5
0
- 8
0.419 (10.64)
0.394 (10.01)
0.292 (7.42)
0.300 (7.62)
0.320 (8.13)
0.290 (7.37)
0.0500 (1.27)
0.0157 (0.40)
4
1
0.070 (1.78)
0.030 (0.76)
0.0291 (0.74)
0.0098 (0.25)
x 45
SEE
0.413 (10.49)
0.396 (10.11)
0.310 (7.87)
0.220 (5.59)
0.011 (0.279)
0.004 (0.102)
0.405 (10.29) MAX
0.104 (2.64)
0.003 (2.36)
0.200
(5.08)
MAX
0.060 (1.52)
0.015 (0.38)
0.019 (0.483)
0.014 (0.356)
0.060
(1.27)
REF
0.0125 (0.32)
0.0091 (0.23)
DETAIL
ABOVE
SEATING
PLANE
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
0
- 15
SEATING PLANE
–12–
REV. C
Package/Price Information
Ultralow Noise, High Speed, BiFET Op Amp
Package
Description
Pin
Count
Temperature
Range
Price*
(100-499)
Model
AD745AN
Status
OBSOLETE
OBSOLETE
PLASTIC/EPOXY DIP
PLASTIC/EPOXY DIP
8
COMMERCIAL
COMMERCIAL
-
-
AD745JN
8
AD745JR-16
PRODUCTION STD S.O. PKG (SOIC)
PRODUCTION STD S.O. PKG (SOIC)
PRODUCTION STD S.O. PKG (SOIC)
PRODUCTION STD S.O. PKG (SOIC)
PRODUCTION PLASTIC QUAD FLATPACK
16
16
16
16
-
COMMERCIAL $4.79
AD745JR-16-REEL
AD745JR-16-REEL7
AD745KR-16
COMMERCIAL
COMMERCIAL
-
-
COMMERCIAL $6.51
AD745KR-16-REEL
COMMERCIAL
COMMERCIAL
COMMERCIAL
-
-
-
AD745KR-16-REEL7 PRODUCTION PLASTIC QUAD FLATPACK
AD745SCHIPS OBSOLETE SINGLE IN-LINE PACKAGE
-
-
* This price is provided for budgetary purposes as recommended list price in U.S. Dollars per unit in the stated volume. Pricing displayed for Evaluation
Boards and Kits is based on 1-piece pricing. View Pricing and Availability for further information.
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