AD7822BRZ [ROCHESTER]
1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20, LEAD FREE, MS-013AC, SOIC-20;
| 型号： | AD7822BRZ |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20, LEAD FREE, MS-013AC, SOIC-20 光电二极管 转换器 |
| 文件： | 总29页 (文件大小：1480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel
Sampling ADCs
AD7822/AD7825/AD7829
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
1
1
2
3
8-bit half-flash ADC with 420 ns conversion time
One, four, and eight single-ended analog input channels
Available with input offset adjust
On-chip track-and-hold
DD
CONVST EOC A0 A1 A2 PD
CONTROL
LOGIC
COMP
2.5V
REF
SNR performance given for input frequencies up to 10 MHz
On-chip reference (2.5 V)
V
IN1
4
V
BUF
V
REF IN/OUT
IN2
4
4
5
5
5
5
Automatic power-down at the end of conversion
Wide operating supply range
3 V 10% and 5 V 10%
Input ranges
0 V to 2 V p-p, VDD = 3 V 10%
V
V
V
V
V
V
IN3
IN4
IN5
IN6
IN7
IN8
8-BIT
INPUT
MUX
HALF
FLASH
ADC
T/H
DB7
DB0
PARALLEL
PORT
V
MID
0 V to 2.5 V p-p, VDD = 5 V 10%
AGND DGND
CS RD
EOC
Flexible parallel interface with
standalone operation
pulse to allow
1
2
3
4
5
A0, A1
A2
PD
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
V
V
TO V
TO V
IN2
IN5
IN4
IN8
APPLICATIONS
Data acquisition systems, DSP front ends
Disk drives
Figure 1.
Mobile communication systems, subsampling
applications
GENERAL DESCRIPTION
The AD7822 and AD7825 are available in 20-lead and 24-lead,
0.3" wide, plastic dual in-line packages (PDIP); 20-lead and
24-lead standard small outline packages (SOIC); and 20-lead
and 24-lead thin shrink small outline packages (TSSOP). The
AD7829 is available in a 28-lead, 0.6" wide PDIP; a 28-lead
SOIC; and a 28-lead TSSOP.
The AD7822/AD7825/AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822/
AD7825/AD7829 contain an on-chip reference of 2.5 V
(2% tolerance); a track-and-hold amplifier; a 420 ns, 8-bit half-
flash ADC; and a high speed parallel interface. The converters
can operate from a single 3 V 10% and 5 V 10% supply.
PRODUCT HIGHLIGHTS
1. Fast Conversion Time. The AD7822/AD7825/AD7829
have a conversion time of 420 ns. Faster conversion times
maximize the DSP processing time in a real-time system.
The AD7822/AD7825/AD7829 combine the convert start and
CONVST
power-down functions at one pin, that is, the
pin.
This allows a unique automatic power-down at the end of a
CONVST
conversion to be implemented. The logic level on the
pin is sampled after the end of a conversion when an
2. Analog Input Span Adjustment. The VMID pin allows the
user to offset the input span. This feature can reduce the
requirements of single-supply op amps and take into
account any system offsets.
EOC
(end
of conversion) signal goes high. If it is logic low at that point,
the ADC is powered down. The AD7822 and AD7825 also have
a separate power-down pin (see the Operating Modes section).
3. FPBW (Full Power Bandwidth) of Track-and-Hold.
The track-and-hold amplifier has an excellent high
frequency performance. The AD7822/AD7825/AD7829
are capable of converting full-scale input signals up to a
frequency of 10 MHz. This makes the parts ideally suited
to subsampling applications.
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
EOC
space. The
pulse allows the ADCs to be used in a stand-
alone manner (see the Parallel Interface section.)
4. Channel Selection. Channel selection is made without the
necessity of writing to the part.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7822/AD7825/AD7829
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagram ................................................... 10
ADC Transfer Function............................................................. 11
Analog Input ............................................................................... 11
Power-Up Times......................................................................... 14
Power vs. Throughput................................................................ 15
Operating Modes........................................................................ 15
Parallel Interface......................................................................... 17
Microprocessor Interfacing........................................................... 18
AD7822/AD7825/AD7829 to 8051 ......................................... 18
AD7822/AD7825/AD7829 to PIC16C6x/PIC16C7x................ 18
AD7822/AD7825/AD7829 to ADSP-21xx ............................. 18
Interfacing Multiplexer Address Inputs .................................. 18
AD7822 Standalone Operation ................................................ 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Circuit Information........................................................................ 10
Circuit Description..................................................................... 10
REVISION HISTORY
Changes to Typical Connection Diagram Section........................7
Changes to Analog Input Section....................................................8
Changes to Analog Input Selection Section...................................9
Changes to Power-Up Times Section .......................................... 10
Changes to Power vs. Throughput Section................................. 11
Added AD7822 Stand-Alone Operation section ....................... 15
8/06—Rev. B to Rev. C
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Typical Connection Diagram Section..................... 10
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide .......................................................... 25
12/99—Rev. 0 to Rev. A
10/01—Rev. A to Rev. B
Changes to Power Requirements.................................................... 3
Changes to Pin Function Description ........................................... 5
Changes to Circuit Description...................................................... 7
Rev. C | Page 2 of 28
AD7822/AD7825/AD7829
SPECIFICATIONS
VDD = 3 V 10%, VDD = 5 V 10%, GND = 0 V, VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Version B
Unit
Test Condition/Comment
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio1
Total Harmonic Distortion1
Peak Harmonic or Spurious Noise1
Intermodulation Distortion1
Second-Order Terms
Third-Order Terms
fIN = 30 kHz, fSAMPLE = 2 MHz
48
−55
−55
dB min
dB max
dB max
fa = 27.3 kHz, fb = 28.3 kHz
fIN = 20 kHz
−65
−65
−70
dB typ
dB typ
dB typ
Channel-to-Channel Isolation1
DC ACCURACY
Resolution
8
Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Gain Error1
8
Bits
0.75
0.75
2
0.1
1
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB typ
Gain Error Match1
Offset Error1
Offset Error Match1
0.1
ANALOG INPUTS2
VDD = 5 V 10ꢀ
See Analog Input section
Input voltage span = 2.5 V
VIN1 to VIN8 Input Voltage
VDD
0
VDD − 1.25
1.25
V max
V min
V max
V min
VMID Input Voltage
Default VMID = 1.25 V
VDD = 3 V 10ꢀ
Input voltage span = 2 V
VIN1 to VIN8 Input Voltage
VDD
0
V max
V min
VMID Input Voltage
VDD − 1
1
V max
V min
Default VMID = 1 V
VIN Input Leakage Current
VIN Input Capacitance
VMID Input Impedance
REFERENCE INPUT
1
15
6
μA max
pF max
kΩ typ
VREF IN/OUT Input Voltage Range
2.55
2.45
1
V max
V min
ꢁA typ
ꢁA max
2.5 V + 2ꢀ
2.5 V − 2ꢀ
Input Current
100
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
LOGIC INPUTS
Nominal 2.5 V
50
50
mV max
ppm/°C typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
2
0.4
1
V min
V max
V min
V max
ꢁA max
pF max
VDD = 5 V 10ꢀ
VDD = 5 V 10ꢀ
VDD = 3 V 10ꢀ
VDD = 3 V 10ꢀ
10 nA typical, VIN = 0 V to VDD
Input Capacitance, CIN
10
Rev. C | Page 3 of 28
AD7822/AD7825/AD7829
Parameter
Version B
Unit
Test Condition/Comment
LOGIC OUTPUTS
Output High Voltage, VOH
ISOURCE = 200 ꢁA
VDD = 5 V 10ꢀ
VDD = 3 V 10ꢀ
ISINK = 200 ꢁA
4
2.4
V min
V min
Output Low Voltage, VOL
0.4
0.2
1
V max
V max
ꢁA max
pF max
VDD = 5 V 10ꢀ
VDD = 3 V 10ꢀ
High Impedance Leakage Current
High Impedance Capacitance
CONVERSION RATE
10
Track-and-Hold Acquisition Time
Conversion Time
200
420
ns max
ns max
See Circuit Description section
POWER SUPPLY REJECTION
VDD 10ꢀ
1
LSB max
POWER REQUIREMENTS
VDD
4.5
5.5
2.7
3.3
V min
V max
V min
V max
5 V 10ꢀ% for specified performance
3 V 10ꢀ% for specified performance
VDD
IDD
Normal Operation
Power-Down
12
5
0.2
mA max
ꢁA max
ꢁA typ
8 mA typical
Logic inputs = 0 V or VDD
Power Dissipation
Normal Operation
Power-Down
200 kSPS
VDD = 3 V
24 mW typical
36
mW max
9.58
23.94
mW typ
mW typ
500 kSPS
1 See the Terminology section of this data sheet.
2 Refer to the Analog Input section for an explanation of the analog input(s).
Rev. C | Page 4 of 28
AD7822/AD7825/AD7829
TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter1,
2
5 V 10% 3 V 10% Unit
Conditions/Comments
ns max Conversion time
ns min Minimum CONVST pulse width
t1
t2
t3
t4
420
20
30
110
70
10
0
420
20
30
110
70
10
0
ns min Minimum time between the rising edge of RD and the next falling edge of convert star
ns max EOC pulse width
ns min
t5
t6
t7
t8
t9
ns max RD rising edge to EOC pulse high
ns min CS to RD setup time
0
0
ns min CS to RD hold time
30
10
5
30
20
5
ns min Minimum RD pulse width
3
ns max Data access time after RD low
ns min Bus relinquish time after RD high
ns max
ns min Address setup time before falling edge of RD
ns min Address hold time after falling edge of RD
ns min Minimum time between new channel selection and convert start
4
t10
20
10
15
200
25
1
20
10
15
200
25
1
t11
t12
t13
tPOWER UP
tPOWER UP
ꢁs typ
Power-up time from rising edge of CONVST using on-chip reference
ꢁs max Power-up time from rising edge of CONVST using external 2.5 V reference
1 Sample tested to ensure compliance.
2 See Figure 24, Figure 25, and Figure 26.
3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V 10ꢀ, and time required for an output
to cross 0.4 V or 2.0 V with VDD = 3 V 10ꢀ.
4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200µA
I
OL
TO OUTPUT
PIN
2.1V
C
L
50pF
200µA
I
OH
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. C | Page 5 of 28
AD7822/AD7825/AD7829
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND
VDD to DGND
−0.3 V to +7 V
−0.3 V to +7 V
Analog Input Voltage to AGND
VIN1 to VIN8
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Reference Input Voltage to AGND
VMID Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
PDIP Package, Power Dissipation
θJA Thermal Impedance
Lead Temperature, (Soldering, 10 sec)
SOIC Package, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
−40°C to +85°C
−65°C to +150°C
150°C
450 mW
105°C/W
260°C
450 mW
75°C/W
215°C
Infrared (15 sec)
220°C
TSSOP Package, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
450 mW
128°C/W
215°C
220°C
1 kV
Infrared (15 sec)
ESD
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 6 of 28
AD7822/AD7825/AD7829
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB2
DB1
DB3
DB4
DB5
DB6
DB7
AGND
DB2
DB1
1
2
3
4
5
6
7
8
9
24 DB3
23 DB4
DB0
CONVST
CS
DB2
DB1
1
2
3
4
5
6
7
8
9
20 DB3
19 DB4
18 DB5
17 DB6
16 DB7
15 AGND
DB0
22 DB5
CONVST
CS
21 DB6
RD
AD7829
TOP VIEW
(Not to Scale)
DB0
AD7825 20 DB7
DGND
EOC
A2
V
V
V
V
V
V
V
V
DD
CONVST
CS
TOP VIEW
(Not to Scale)
RD
19 AGND
REF IN/OUT
MID
AD7822
DGND
EOC
A1
18
17
16
15
14
13
V
V
V
V
V
V
DD
TOP VIEW
RD
(Not to Scale)
A1 10
REF IN/OUT
IN1
DGND
EOC
PD
14
13
12
11
V
V
V
V
DD
11
A0
MID
IN1
IN2
IN3
IN2
REF IN/OUT
MID
12
A0 10
PD 11
V
V
V
IN8
IN3
13
IN7
IN4
NC 10
IN1
14
V
12
IN4
IN6
IN5
NC = NO CONNECT
Figure 3. Pin Configuration
Figure 4. Pin Configuration
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic Description
VIN1 to VIN8
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight analog input
channels, respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (VDD). This span can
be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to
2 V (VDD = 3 V 10%) or AGND to 2.5 V (VDD = 5 V 10%). ꢀee the Analog Input section of the data sheet for more information.
VDD
Positive ꢀupply Voltage, 3 V 10% and 5 V 10%.
AGND
DGND
CONVꢀT
Analog Ground. Ground reference for track-and-hold, comparators, reference circuit, and multiplexer.
Digital Ground. Ground reference for digital circuitry.
Logic Input ꢀignal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The
falling edge of this signal places the track-and-hold in hold mode. The track-and-hold goes into track mode again 120 ns after
the start of a conversion. The state of the CONVꢀT signal is checked at the end of a conversion. If it is logic low, the AD7822/
AD7825/AD7829 powers down (see the Operating Modes section of the data sheet).
EOC
Cꢀ
Logic Output. The end-of-conversion signal indicates when a conversion has finished. The signal can be used to interrupt
a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section).
Logic Input ꢀignal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary
if the ADC is sharing a common data bus with another device.
PD
Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and
AD7825 in power-down mode. The ADCs power up when PD is brought logic high again.
RD
Logic Input ꢀignal. The read signal is used to take the output buffers out of their high impedance state and drive data onto
the data bus. The signal is internally gated with the Cꢀ signal. Both RD and Cꢀ must be logic low to enable the data bus.
A0 to A2
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal
goes low.
DB0 to DB7 Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD and Cꢀ
go active low.
VREF IN/OUT
Analog Input and Output. An external reference can be connected to the AD7822/AD7825/AD7829 at this pin. The on-chip
reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it
can be decoupled to AGND with a 0.1 μF capacitor.
VMID
The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog
Input section).
Rev. C | Page 7 of 28
AD7822/AD7825/AD7829
TERMINOLOGY
The AD7822/AD7825/AD7829 are tested using the CCIF
standard, where two input frequencies near the top end of the
input bandwidth are used. In this case, the second- and third-
order terms are of different significance. The second-order terms
are usually distanced in frequency from the original sine waves,
and the third-order terms are usually at a frequency close to the
input frequencies. As a result, the second- and third-order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in decibels (dB).
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal-to-(noise + distortion) at the
output of the analog-to-digital converter. The signal is the rms
amplitude of the fundamental. Noise is the rms sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent upon the number of
quantization levels in the digitization process: the more levels,
the smaller the quantization noise. The theoretical signal-to-(noise
+ distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Channel-to-Channel Isolation
Thus, for an 8-bit converter, this is 50 dB.
A measure of the level of crosstalk between channels. It is
measured by applying a full-scale 20 kHz sine wave signal to
one input channel and determining how much that signal is
attenuated in each of the other channels. The figure given is the
worst case across all four or eight channels of the AD7825 and
AD7829, respectively.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7822/AD7825/AD7829, it is defined as
2
2
2
2
2
V2 + V3 + V4 + V5 + V6
THD (dB) = 20 log
V1
Relative Accuracy or Endpoint Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Differential Nonlinearity
The difference between the measured and the ideal one LSB
change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specification
is determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it is a
noise peak.
Offset Error
The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, that is, VMID
.
Offset Error Match
The difference in offset error between any two channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb, where
m, n = 0, 1, 2, 3, … . Intermodulation terms are those for which
neither m nor n is equal to zero. For example, the second-order
terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Zero-Scale Error
The deviation of the first code transition (00000000) to
(00000001) from the ideal; that is, VMID − 1.25 V + 1 LSB (VDD
5 V 10%), or VMID − 1.0 V + 1 LSB (VDD = 3 V 10%).
=
Full-Scale Error
The deviation of the last code transition (11111110) to (11111111)
from the ideal; that is, VMID + 1.25 V − 1 LSB (VDD = 5 V 10%),
or VMID + 1.0 V − 1 LSB (VDD = 3 V 10%).
Rev. C | Page 8 of 28
AD7822/AD7825/AD7829
It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected VIN input of the AD7822/
AD7825/AD7829. It means that the user must wait for the
duration of the track-and-hold acquisition time after a channel
change/step input change to VIN before starting another
conversion, to ensure that the part operates to specification.
Gain Error
The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, that is, VREF − 1 LSB, after the
offset error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Track-and-Hold Acquisition Time
PSR (Power Supply Rejection)
The time required for the output of the track-and-hold amplifier to
reach its final value, within 1/2 LSB, after the point at which the
track-and-hold returns to track mode. This happens approximately
Variations in power supply affect the full-scale transition but
not the converter linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
CONVST
120 ns after the falling edge of
.
Rev. C | Page 9 of 28
AD7822/AD7825/AD7829
CIRCUIT INFORMATION
CIRCUIT DESCRIPTION
REFERENCE
The AD7822/AD7825/AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash
ADC contains a sampling capacitor followed by 15 comparators
that compare the unknown input to a reference ladder to
achieve a 4-bit result. This first flash (that is, coarse conversion)
provides the four MSBs. For a full 8-bit reading to be realized,
a second flash (that is, fine conversion) must be performed to
provide the four LSBs. The 8-bit word is then placed on the data
output bus.
R16
R15
15
14
13
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SW2
A
T/H 1
V
IN
SAMPLING
CAPACITOR
B
HOLD
R14
R13
1
Figure 6 and Figure 7 show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes
into hold mode and holds the analog input for 120 ns. This is
the acquisition phase, as shown in Figure 6, when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor,
as Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, that is, at 220 ns; and the end
of the second flash and, hence, the 8-bit conversion result is
available at 330 ns (minimum). The maximum conversion time
is 420 ns. As shown in Figure 8, the track-and-hold returns to
track mode after 120 ns and starts the next acquisition before
the end of the current conversion. Figure 10 shows the ADC
transfer function.
R1
TIMING AND
CONTROL
LOGIC
Figure 7. ADC Conversion Phase
120ns
HOLD
TRACK
TRACK
HOLD
CONVST
t2
t1
EOC
CS
t3
RD
VALID
DATA
DB0 TO DB7
Figure 8. Track-and-Hold Timing
REFERENCE
TYPICAL CONNECTION DIAGRAM
Figure 9 shows a typical connection diagram for the AD7822/
AD7825/AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
R16
15
DB7
DB6
R15
SW2
A
EOC
CONVST
conversion signal ( ) idles high, the falling edge of
DB5
14
13
T/H 1
V
IN
SAMPLING
CAPACITOR
initiates a conversion, and at the end of conversion the falling
EOC
B
DB4
DB3
DB2
DB1
DB0
HOLD
edge of
is used to initiate an interrupt service routine
R14
R13
(ISR) on a microprocessor (see the Parallel Interface section for
more details.) VREF and VMID are connected to a voltage source
such as the AD780, and VDD is connected to a voltage source
that can vary from 4.5 V to 5.5 V (see Table 5 in the Analog Input
section). When VDD is first connected, the AD7822/AD7825/
AD7829 power up in a low current mode, that is, power-down
1
R1
TIMING AND
CONTROL
LOGIC
EOC
mode, with the default logic level on the
pin on the
CONVST
AD7822 and AD7825 equal to a low. Ensure the
line is
Figure 6. ADC Acquisition Phase
not floating when VDD is applied, because this can put the
AD7822/AD7825/AD7829 into an unknown state.
Rev. C | Page 10 of 28
AD7822/AD7825/AD7829
ANALOG INPUT
CONVST
A suggestion is to tie
or pull-down resistor. A rising edge on the
the AD7829 to fully power up, while a rising edge on the
to VDD or DGND through a pull-up
The AD7822 has a single input channel, and the AD7825 and
AD7829 have four and eight input channels, respectively. Each
input channel has an input span of 2.5 V or 2.0 V, depending on
the supply voltage (VDD). This input span is automatically set up
by an on-chip VDD detector circuit. A 5 V operation of the ADCs
is detected when VDD exceeds 4.1 V, and a 3 V operation is
detected when VDD falls below 3.8 V. This circuit also possesses
a degree of glitch rejection; for example, a glitch from 5.5 V to
2.7 V up to 60 ns wide does not trip the VDD detector.
CONVST
pin causes
PD
pin
causes the AD7822 and AD7825 to fully power up. For applica-
tions where power consumption is of concern, the automatic
power-down at the end of a conversion should be used to improve
power performance (see the Power vs. Throughput section).
2.5V
AD780
SUPPLY
4.5V TO 5.5V
10µF
0.1µF
PARALLEL
INTERFACE
The VMID pin is used to center this input span anywhere in the
V
V
V
DD
REF
MID
range of AGND to VDD. If no input voltage is applied to VMID
,
DB0 TO DB7
EOC
the default input range is AGND to 2.0 V (VDD = 3 V 10%),
that is, centered about 1.0 V; or AGND to 2.5 V (VDD = 5 V
10%), that is, centered about 1.25 V. When using the default
input range, the VMID pin can be left unconnected, or in some
cases, it can be decoupled to AGND with a 0.1 μF capacitor.
V
IN1
1.25V TO
3.75V INPUT
AD7822/
AD7825/
AD7829
RD
CS
4
V
IN2
µC/µP
CONVST
5
(V )
IN4 IN8
V
1
A0
If, however, an external VMID is applied, the analog input range
is from VMID − 1.0 V to VMID + 1.0 V (VDD = 3 V 10%), or
from VMID − 1.25 V to VMID + 1.25 V (VDD = 5 V 10%).
AGND
DGND
1
A1
2
A2
3
PD
The range of values of VMID that can be applied depends on the
value of VDD. For VDD = 3 V 10%, the range of values that can
be applied to VMID is from 1.0 V to VDD − 1.0 V and from 1.25 V to
1
2
3
4
5
A0, A1
A2
PD
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
V
DD − 1.25 V when VDD = 5 V 10%. Table 5 shows the relevant
ranges of VMID and the input span for various values of VDD
Figure 11 illustrates the input signal range available with various
V
V
TO V
TO V
IN2
IN5
IN4
IN8
.
Figure 9. Typical Connection Diagram
values of VMID
.
ADC TRANSFER FUNCTION
Table 5.
The output coding of the AD7822/AD7825/AD7829 is straight
binary. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size =
VMID
VMID Ext
VMID Ext
VIN Span Min
VDD Internal Max
VIN Span Unit
5.5
5.0
4.5
3.3
3.0
2.7
1.25
1.25
1.25
1.00
1.00
1.00
4.25
3.75
3.25
2.3
2.0
1.7
3.0 to 5.5 1.25
2.5 to 5.0 1.25
2.0 to 4.5 1.25
1.3 to 3.3 1.00
1.0 to 3.0 1.00
0.7 to 2.7 1.00
0 to 2.5
0 to 2.5
0 to 2.5
0 to 2.0
0 to 2.0
0 to 2.0
V
V
V
V
V
V
VREF/256 (VDD = 5 V) or the LSB size = (0.8 VREF)/256 (VDD =
3 V). The ideal transfer characteristic for the AD7822/AD7825/
AD7829 is shown in Figure 10.
(V
= 5V)
DD
1LSB = V
11111111
111...110
/256
REF
111...000
10000000
000...111
(V
= 3V)
DD
1LSB = 0.8V
/256
REF
000...010
000...001
00000000
1LSB
V
MID
(V = 5V) V
DD
(V = 3V) V
DD
– 1.25V
– 1V
V
V
+ 1.25V – 1LSB
+ 1V – 1LSB
MID
MID
MID
MID
ANALOG INPUT VOLTAGE
Figure 10. Transfer Characteristic
Rev. C | Page 11 of 28
AD7822/AD7825/AD7829
2.5V
V
= 5V
DD
V
V
REF
MID
5V
4V
3V
2V
1V
AD7822/
AD7825/
AD7829
R4
R1
R3
R2
V
= 3.75V
MID
V
IN
V
V
V
= 2.5V
MID
0V
V
IN
V
= N/C (1.25V)
MID
2.5V
INPUT SIGNAL RANGE
FOR VARIOUS V
MID
0V
Figure 13. Accommodating Bipolar Signals Using External VMID
EXTERNAL
2.5V
V
= 3V
DD
3V
2V
V
REF
V
MID
R4
R1
AD7822/
AD7825/
AD7829
R3
R2
V
= 2V
MID
V
IN
V
= 1.5V
V
MID
V
V
= N/C (1V)
MID
1V
0V
V
INPUT SIGNAL RANGE
FOR VARIOUS V
IN
MID
V
MID
Figure 11. Analog Input Span Variation with VMID
0V
VMID can be used to remove offsets in a system by applying the
offset to the VMID pin as shown in Figure 12, or it can be used to
accommodate bipolar signals by applying VMID to a level-shifting
circuit before VIN, as shown in Figure 13. When VMID is being
driven by an external source, the source can be directly tied to
the level-shifting circuitry (see Figure 13). However, if the
internal VMID, that is, the default value, is being used as an
output, it must be buffered before applying it to the level-
shifting circuitry because the VMID pin has an impedance of
approximately 6 kΩ (see Figure 14).
Figure 14. Accommodating Bipolar Signals Using Internal VMID
NOTE: Although there is a VREF pin from which a voltage
reference of 2.5 V can be sourced, or to which an external
reference can be applied, this does not provide an option of
varying the value of the voltage reference. As stated in the
specifications for the AD7822/AD7825/AD7829, the input
voltage range at this pin is 2.5 V 2%.
Analog Input Structure
Figure 15 shows an equivalent circuit of the analog input
structure of the AD7822/AD7825/AD7829. The two diodes,
D1 and D2, provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never
exceeds the supply rails by more than 200 mV. Doing so causes
these diodes to become forward biased and start conducting
current into the substrate. A maximum current of 20 mA can be
conducted by these diodes without causing irreversible damage
to the part. However, it is worth noting that a small amount of
current (1 mA) being conducted into the substrate, due to an
overvoltage on an unselected channel, can cause inaccurate
conversions on a selected channel.
V
IN
V
IN
V
AD7822/
AD7825/
AD7829
MID
V
MID
V
MID
Figure 12. Removing Offsets Using VMID
Rev. C | Page 12 of 28
AD7822/AD7825/AD7829
120ns
Capacitor C2 in Figure 15 is typically about 4 pF and can be
primarily attributed to pin capacitance. The resistor, R1, is a
lumped component made up of the on resistance of several
components, including that of the multiplexer and the track-
and-hold. This resistor is typically about 310 Ω. Capacitor C1
is the track-and-hold capacitor and has a capacitance of 0.5 pF.
Switch 1 is the track-and-hold switch, and Switch 2 is that of the
sampling capacitor, as shown in Figure 6 and Figure 7.
HOLD CHx
TRACK CHx
TRACK CHx
CONVST
TRACK CHy
HOLD CHy
t2
t1
EOC
CS
t3
RD
V
DD
t13
VALID
DATA
DB0 TO DB7
C1
0.5pF
D1
R1
310Ω
SW2
B
A
V
IN
A0 TO A2
SW1
C2
4pF
D2
ADDRESS CHANNEL y
Figure 16. Channel Hopping Timing
Figure 15. Equivalent Analog Input Circuit
RD
There is a minimum time delay between the falling edge of
CONVST
and the next falling edge of the
signal, t13. This is the
When in track phase, Switch 1 is closed and Switch 2 is in
Position A. When in hold mode, Switch 1 opens and Switch 2
remains in Position A. The track-and-hold remains in hold
mode for 120 ns (see the Circuit Description section), after
which it returns to track mode and the ADC enters its conversion
phase. At this point, Switch 1 opens and Switch 2 moves to
Position B. At the end of the conversion, Switch 2 moves back
to Position A.
minimum acquisition time required of the track-and-hold to
maintain 8-bit performance. Figure 17 shows the typical perform-
ance of the AD7825 when channel hopping for various acquisition
times. These results are obtained using an external reference
and internal VMID while channel hopping between VIN1 and VIN4
with 0 V on Channel 4 and 0.5 V on Channel 1.
8.5
Analog Input Selection
8.0
On power-up, the default VIN selection is VIN1. When returning
to normal operation from power-down, the VIN selected is the
same one that was selected prior to initiation of power-down.
Table 6 shows the multiplexer address corresponding to each
analog input from VIN1 to VIN4(8) for the AD7825 or AD7829.
7.5
7.0
6.5
6.0
5.5
5.0
Table 6.
A2
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Analog Input Selected
0
0
0
0
1
1
1
1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
500
200
100
50
40
30
20
15
10
ACQUISITION TIME (ns)
Figure 17. Effective Number of Bits vs. Acquisition Time for the AD7825
The on-chip track-and-hold can accommodate input frequencies
to 10 MHz, making the AD7822/AD7825/AD7829 ideal for
subsampling applications. When the AD7825 is converting a
10 MHz input signal at a sampling rate of 2 MSPS, the effective
number of bits typically remains above seven, corresponding to
a signal-to-noise ratio of 42 dBs, as shown in Figure 18.
Channel selection on the AD7825 and AD7829 is made without
the necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read operation,
RD
CS
that is, on the falling edge of
while
is low, as shown in
Figure 16. This allows for improved throughput rates in “channel
hopping” applications.
Rev. C | Page 13 of 28
AD7822/AD7825/AD7829
50
48
46
44
42
EXTERNAL REFERENCE
fSAMPLE = 2MHz
V
DD
tPOWER-UP
1µs
CONVST
CONVERSION
INITIATED HERE
ON-CHIP REFERENCE
V
DD
tPOWER-UP
25µs
40
38
CONVST
CONVERSION
INITIATED HERE
0.2
1
3
4
5
6
8
10
INPUT FREQUENCY (MHz)
Figure 19. AD7829 Power-Up Time
Figure 18. SNR vs. Input Frequency on the AD7825
Figure 20 shows how to power up the AD7822 or AD7825 when
VDD is first connected or after the ADCs have been powered down,
POWER-UP TIMES
PD
CONVST
using the
pin or the
pin, with either the on-chip
The AD7822/AD7825/AD7829 have a 1 μs power-up time
when using an external reference and a 25 μs power-up time
when using the on-chip reference. When VDD is first connected,
the AD7822/AD7825/AD7829 are in a low current mode of
CONVST
reference or an external reference. When the supplies are first
connected or after the part has been powered down by the
pin, only a rising edge on the
up. When the part has been powered down using the
PD
pin causes the part to power
CONVST
PD
operation. Ensure that the
line is not floating when
PD
CONVST
pin powers
CONVST
pin, a rising edge on either the
the part up again.
pin or the
V
DD is applied. If there is a glitch on
while VDD is
rising, the part attempts to power up before VDD has fully settled
and can enter an unknown state. To carry out a conversion, the
AD7822/AD7825/AD7829 must first be powered up. The
AD7829 is powered up by a rising edge on the
and a conversion is initiated on the falling edge of
As with the AD7829, when using an external reference with the
CONVST
AD7822 or AD7825, the falling edge of
may occur
CONVST
pin,
CONVST
before the required power-up time has elapsed. If this is the
case, the conversion is not initiated on the falling edge of
but rather at the moment when the part has powered up
.
CONVST
,
Figure 19 shows how to power up the AD7829 when VDD is first
connected or after the AD7829 has been powered down using
CONVST
completely, that is, after 1 μs. If the falling edge of
CONVST
the
external reference. When using an external reference, the falling
CONVST
pin when using either the on-chip reference or an
occurs after the required power-up time has elapsed, it is upon
this falling edge that a conversion is initiated. When using the
on-chip reference, it is necessary to wait the required power-up
time of approximately 25 μs before initiating a conversion; that
edge of
has elapsed; however, the conversion is not initiated on the
CONVST
may occur before the required power-up time
falling edge of
part has completely powered up, that is, after 1 μs. If the falling
CONVST
but rather at the moment when the
CONVST
is, a falling edge on
must not occur before the
required power-up time has elapsed, when supplies are first
connected to the AD7822 or AD7825, or when the ADCs have
edge of
occurs after the required power-up time has
elapsed, then it is upon this falling edge that a conversion is
initiated. When using the on-chip reference, it is necessary to
wait the required power-up time of approximately 25 μs before
PD
CONVST
been powered down using the
shown in Figure 20.
pin or the
pin, as
CONVST
initiating a conversion; that is, a falling edge on
must
not occur before the required power-up time has elapsed, when
VDD is first connected or after the AD7829 has been powered
CONVST
down using the
pin, as shown in Figure 19.
Rev. C | Page 14 of 28
AD7822/AD7825/AD7829
EXTERNAL REFERENCE
Figure 22 shows the power vs. throughput rate for automatic
full power-down.
V
DD
PD
100
10
1
tPOWER-UP
1µs
tPOWER-UP
1µs
CONVST
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
ON-CHIP REFERENCE
V
DD
0.1
PD
tPOWER-UP
25µs
tPOWER-UP
25µs
CONVST
0
0
50 100 150 200 250 300 350 400 450 500
THROUGHPUT (kSPS)
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
Figure 22. AD7822/AD7825/AD7829 Power vs. Throughput
Figure 20. AD7822/AD7825 Power-Up Time
0
2048 POINT FFT
SAMPLING
2MSPS
POWER VS. THROUGHPUT
–10
–20
–30
–40
–50
–60
–70
–80
fIN = 200kHz
Superior power performance can be achieved by using the
automatic power-down (Mode 2) at the end of a conversion
(see the Operating Modes section).
Figure 21 shows how the automatic power-down is implemented
CONVST
using the
performance for the AD7822/AD7825/AD7829. The duration
CONVST
signal to achieve the optimum power
of the
pulse is set to be equal to or less than the power-up
time of the devices (see the Operating Modes section). As the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
FREQUENCY (kHz)
Figure 23. AD7822/AD7825/AD7829 SNR
tPOWER-UP tCONVERT
1µs
POWER-DOWN
OPERATING MODES
330ns
CONVST
The AD7822/AD7825/AD7829 have two possible modes of
t
CONVST
operation, depending on the state of the
approximately 100 ns after the end of a conversion, that is, upon
EOC
pulse
CYCLE
10µs @ 100kSPS
Figure 21. Automatic Power-Down
the rising edge of the
pulse.
For example, if the AD7822 is operated in a continuous
sampling mode, with a throughput rate of 100 kSPS and using
an external reference, the power consumption is calculated as
follows. The power dissipation during normal operation is
36 mW, VDD = 3 V. If the power-up time is 1 μs and the conversion
time is 330 ns (@ +25°C), the AD7822 can be said to dissipate
36 mW (maximum) for 1.33 μs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 μs and
the average power dissipated during each cycle is (1.33/10) ×
(36 mW) = 4.79 mW. This calculation uses the minimum
conversion time, thus giving the best-case power dissipation at
this throughput rate. However, the actual power dissipated
during each conversion cycle could increase, depending on the
actual conversion time (up to a maximum of 420 ns).
Mode 1 Operation (High Speed Sampling)
When the AD7822/AD7825/AD7829 are operated in Mode 1,
they are not powered down between conversions. This mode of
operation allows high throughput rates to be achieved.
Figure 24 shows how this optimum throughput rate is achieved
CONVST
by bringing
high before the end of a conversion, that
EOC
is, before the
pulses low. When operating in this mode, a
new conversion should not be initiated until 30 ns after the end
of a read operation. This allows the track-and-hold to acquire
the analog signal to 0.5 LSB accuracy.
Rev. C | Page 15 of 28
AD7822/AD7825/AD7829
The ADC is powered up again on the rising edge of the
CONVST
in this mode of operation by powering up the AD7822/AD7825/
AD7829 only to carry out a conversion. The parallel interface of
the AD7822/AD7825/AD7829 remains fully operational while
the ADCs are powered down. A read may occur while the part
is powered down, and, therefore, it does not necessarily need to
Mode 2 Operation (Automatic Power-Down)
signal. Superior power performance can be achieved
When the AD7822/AD7825/AD7829 are operated in Mode 2
(see Figure 25), they automatically power down at the end of
CONVST
a conversion. The
a conversion and is left logic low until after the
that is, approximately 100 ns after the end of the conversion.
CONVST
signal is brought low to initiate
EOC
goes high,
The state of the
signal is sampled at this point (that is,
CONVST
EOC
be placed within the
pulse, as shown in Figure 25.
530 ns maximum after
falling edge), and the AD7822/
CONVST
AD7825/AD7829 power down as long as
is low.
120ns
HOLD
TRACK
TRACK
HOLD
t2
CONVST
t1
EOC
CS
t3
RD
VALID
DATA
DB0 TO DB7
Figure 24. Mode 1 Operation
tPOWER-UP
POWER
DOWN
HERE
CONVST
t1
EOC
CS
RD
VALID
DATA
DB0 TO DB7
Figure 25. Mode 2 Operation
Rev. C | Page 16 of 28
AD7822/AD7825/AD7829
EOC
However, the
RD EOC
pulse can be reset high by a rising edge
PARALLEL INTERFACE
of
interrupt of a microprocessor.
the 8-bit conversion result. It is possible to tie
RD
. This
line can be used to drive an edge-triggered
The parallel interface of the AD7822/AD7825/AD7829 is eight
bits wide. Figure 26 shows a timing diagram illustrating the
operational sequence of the AD7822/AD7825/AD7829 parallel
interface. The multiplexer address is latched into the AD7822/
AD7825/AD7829 on the falling edge of the
chip track-and-hold goes into hold mode on the falling edge of
CS RD
and
going low accesses
CS
permanently
to access the data. In systems where the
EOC
low and use only
part is interfaced to a gate array or ASIC, this
CS RD
pulse can be
inputs to latch data out of the AD7822/
RD
input. The on-
applied to the and
AD7825/AD7829 and into the gate array or ASIC. This means
that the gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7822/
AD7825/AD7829.
CONVST
, and a conversion is also initiated at this point. When
EOC
the conversion is complete, the end of conversion line (
pulses low to indicate that new data is available in the output
register of the AD7822/AD7825/AD7829. The
logic low for a maximum time of 110 ns.
)
EOC
pulse stays
t2
CONVST
t1
t4
EOC
t5
CS
t7
t6
t8
t3
RD
t9
t10
VALID
DATA
DB0 TO DB7
t13
t11
t12
NEXT
CHANNEL
ADDRESS
A0 TO A2
Figure 26. AD7822/AD7825/AD7829 Parallel Port Timing
Rev. C | Page 17 of 28
AD7822/AD7825/AD7829
MICROPROCESSOR INTERFACING
The parallel port on the AD7822/AD7825/AD7829 allows
the ADCs to be interfaced to a range of many different micro-
controllers. This section explains how to interface the AD7822/
AD7825/AD7829 with some of the more common microcontroller
parallel interface protocols.
1
PIC16C6x/7x
AD7822/
AD7825/
AD78291
DB0 TO DB7
PSP0 TO PSP7
CS
CS
AD7822/AD7825/AD7829 TO 8051
Figure 27 shows a parallel interface between the AD7822/AD7825/
RD
RD
EOC
AD7829 and the 8051 microcontroller. The
signal on the
INT
EOC
AD7822/AD7825/AD7829 provides an interrupt request to the
8051 when a conversion ends and data is ready. Port 0 of the 8051
can serve as an input or output port; or, as in this case when used
together with the address latch enable (ALE) of the 8051, can be
used as a bidirectional low order address and data bus. The ALE
output of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7822/AD7825/ AD7829 are addressed because they do not
have to be turned around (set to 1) for data input, as is the case
for Port 0.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 28. Interfacing to the PIC16C6x/ PIC16C7x
AD7822/AD7825/AD7829 TO ADSP-21xx
Figure 29 shows a parallel interface between the AD7822/
AD7825/AD7829 and the ADSP-21xx series of DSPs. As before,
the
EOC
signal on the AD7822/AD7825/AD7829 provides an
interrupt request to the DSP when a conversion ends.
1
ADSP-21xx
D7 TO D0
DB0 TO DB7
1
8051
A13 TO A0
DB0 TO DB7
AD7822/
AD7825/
ADDRESS
DECODE
LOGIC
AD0 TO AD7
AD78291
AD7822/
LATCH
DECODER
AD7825/
CS
AD78291
DMS
EN
RD
RD
CS
ALE
A8 TO A15
IRQ
EOC
RD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
RD
INT
EOC
Figure 29. Interfacing to the ADSP-21xx
1
ADDITIONAL PINS OMITTED FOR CLARITY.
INTERFACING MULTIPLEXER ADDRESS INPUTS
Figure 27. Interfacing to the 8051
Figure 30 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The multi-
AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x
Figure 28 shows a parallel interface between the AD7822/
AD7825/AD7829 and the PIC16C64/PIC16C65/PIC16C74.
RD
plexer address is latched on the falling edge of the
signal,
EOC
The
signal on the AD7822/AD7825/AD7829 provides an
as outlined in the Parallel Interface section, allowing the use of
the three LSBs of the address bus to select the channel address.
As shown in Figure 30, only Address Bit A3 to Address Bit A15
are address decoded, allowing A0 to A2 to be changed according to
desired channel selection without affecting chip selection.
interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/PIC16C7x range of microcontrollers,
only the PIC16C64/PIC16C65/PIC16C74 can provide the
option of a parallel slave port. Port D of the microcontroller
operates as an 8-bit wide parallel slave port when Control Bit
PSPMODE in the TRISE register is set. Setting PSPMODE
RD
CS
enables Port Pin RE0 to be the
output and RE2 to be the
(chip select) output. For this functionality, the corresponding
data direction bits of the TRISE register must be configured as
outputs (reset to 0). See the PIC16C6x/PIC16C7x microcontroller
user manual.
Rev. C | Page 18 of 28
AD7822/AD7825/AD7829
The resulting signal can be used as an interrupt request signal
AD7822 STANDALONE OPERATION
WR
(IRQ) on a DSP, as a
latch or ASIC. The timing for this interface, as shown in Figure 31,
CONVST
signal to memory, or as a CLK to a
The AD7822, being the single channel device, does not have any
multiplexer addressing associated with it and can be controlled
demonstrates how, with the
can be initiated, data is latched out, and the operating mode of
the AD7822 can be selected.
signal alone, a conversion
CONVST
with just one signal, that is, the
signal. As shown in
RD
CS
EOC
pins are both tied to the pin.
Figure 31, the
and
MICROPROCESSOR READ CYCLE
A0
A1
CS
A2
AD7825/
AD7829
RD
ADDRESS
A15 TO A3
CS
DECODE
ADC I/O ADDRESS
A15 TO A3
RD
A2 TO A0
MUX ADDRESS
A/D RESULT
DB7 TO DB0
DB0 TO DB7
MUX ADDRESS
(CHANNEL SELECTION A0 TO A2)
LATCHED
Figure 30. AD7825/AD7829 Simplified Microinterfacing Scheme
t1
CONVST
CONVST
DSP/
t4
RD
CS
LATCH/ASIC
EOC
AD7822
CS
RD
EOC
DB7 TO DB0
DB0 TO DB7
A/D RESULT
Figure 31. AD7822 Standalone Operation
Rev. C | Page 19 of 28
AD7822/AD7825/AD7829
OUTLINE DIMENSIONS
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
20
1
11
10
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AD
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 32. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
13.00 (0.5118)
12.60 (0.4961)
20
1
11
10
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.2
5 (0.0098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
1.27
(0.0500)
BSC
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
Rev. C | Page 20 of 28
AD7822/AD7825/AD7829
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 34. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
1
13
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AF
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
Rev. C | Page 21 of 28
AD7822/AD7825/AD7829
15.60 (0.6142)
15.20 (0.5984)
24
1
13
12
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
BSC
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
Rev. C | Page 22 of 28
AD7822/AD7825/AD7829
1.565 (39.75)
1.380 (35.05)
28
1
15
14
0.580 (14.73)
0.485 (12.31)
0.625 (15.88)
PIN 1
0.600 (15.24)
0.100 (2.54)
BSC
0.195 (4.95)
0.125 (3.17)
0.250
0.015 (0.38)
(6.35)
MAX
GAUGE
PLANE
0.015
(0.38)
MIN
0.200 (5.08)
0.115 (2.92)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.700 (17.78)
MAX
0.022 (0.56)
0.014 (0.36)
0.005 (0.13)
MIN
0.070 (1.78)
0.030 (0.76)
COMPLIANT TO JEDEC STANDARDS MS-011-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
18.10 (0.7126)
17.70 (0.6969)
28
15
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
14
10.00 (0.3937)
0.75 (0.0295)
0
.25 (0.0098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
BSC
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
Rev. C | Page 23 of 28
AD7822/AD7825/AD7829
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 40. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
Rev. C | Page 24 of 28
AD7822/AD7825/AD7829
ORDERING GUIDE
Model
AD7822BN
AD7822BNZ1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
20-Lead PDIP
20-Lead PDIP
Package Option
Linearity Error
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
0.75 LSB
N-20
N-20
AD7822BR
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead SOIC_W
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
24-Lead PDIP
RW-20
RW-20
RW-20
RW-20
RW-20
RW-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
N-24-1
N-24-1
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
N-28-2
N-28-2
RW-28
RW-28
RW-28
RW-28
RW-28
RW-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
AD7822BR-REEL
AD7822BR-REEL7
AD7822BRZ1
AD7822BRZ-REEL1
AD7822BRZ-REEL71
AD7822BRU
AD7822BRU-REEL
AD7822BRU-REEL7
AD7822BRUZ1
AD7822BRUZ-REEL1
AD7822BRUZ-REEL71
AD7825BN
AD7825BNZ1
AD7825BR
AD7825BR-REEL
AD7825BR-REEL7
AD7825BRZ1
AD7825BRZ-REEL1
AD7825BRZ-REEL71
AD7825BRU
AD7825BRU-REEL
AD7825BRU-REEL7
AD7825BRUZ1
AD7825BRUZ-REEL1
AD7825BRUZ-REEL71
AD7829BN
AD7829BNZ1
AD7829BR
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
28-Lead PDIP
28-Lead PDIP
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
AD7829BR-REEL
AD7829BR-REEL7
AD7829BRZ1
AD7829BRZ-REEL1
AD7829BRZ-REEL71
AD7829BRU
AD7829BRU-REEL
AD7829BRU-REEL7
AD7829BRUZ1
AD7829BRUZ-REEL1
AD7829BRUZ-REEL71
1 Z = Pb-free part.
Rev. C | Page 25 of 28
AD7822/AD7825/AD7829
NOTES
Rev. C | Page 26 of 28
AD7822/AD7825/AD7829
NOTES
Rev. C | Page 27 of 28
AD7822/AD7825/AD7829
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01321-0-8/06(C)
Rev. C | Page 28 of 28
相关型号：
AD7822BRZ-REEL7
1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20, LEAD FREE, MS-013AC, SOIC-20
ROCHESTER
AD7823YN
1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8
ROCHESTER
AD7823YNZ
IC 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8, Analog to Digital Converter
ADI
AD7823YNZ
1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8
ROCHESTER
©2020 ICPDF网 联系我们和版权申明