AD7861AP [ROCHESTER]
7-CH 11-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC44, PLASTIC, LCC-44;
| 型号： | AD7861AP |
| 厂家： | 
Rochester Electronics |
| 描述： | 7-CH 11-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC44, PLASTIC, LCC-44 转换器 |
| 文件： | 总7页 (文件大小：777K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
11-Bit Resolution
Simultaneous Sampling A/D Converter
a
AD7861
FEATURES
FUNCTIONAL BLOCK DIAGRAM
11-Bit Resolution Analog-to-Digital Converter
Seven Single-Ended Analog Inputs
Four Input Channels Simultaneously Sampled
Expansion with 4 Multiplexed Inputs
Internal 2.5 V Reference
3.2 s Conversion Time per Channel
User Definable Channel Sequencing
Single Supply +5 V Operation
REF IN
BUSY
2.5V
A0
A1
REF OUT
REFERENCE
VIN1
VIN2
VIN3
D0
12
11-BIT
ADC
D11
SHA
OUTPUT
REGISTERS
RD
CS
Double Buffered Register Outputs
6.25 MHz to 12.5 MHz Operating Clock Range
CLKIN
AUX0
AUX1
4-1
MUX
SGND
AGND
DGND
APPLICATIONS
Motor Control
3-Phase Power Measurement
Cellular Phones
AUX2
AUX3
S0
AD7861
V
DD
S1
Data Acquisition
CONVST RESET M 0 M1
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
Simultaneous Sampling of Four Inputs
The AD7861 is a multichannel simultaneous sampling A/D
Converter (ADC) configured for the acquisition of voltage
inputs in a motor control solution or three-phase power system.
Four channel sample and hold amplifier (SHA) allows out of
phase input signals to be sampled simultaneously, preserving
the relative phase information. Sample-and-hold acquisition
time is 1.6 µs and conversion time per channel is 3.2 µs (using
a 12.5 MHz system clock).
The AD7861 combined with Analog Devices’ 16-bit fixed-
point digital signal processor (DSP) provides a low cost 16-bit
fixed-point microcontroller solution.
Flexible Analog Channel Sequencing
The input stage has been designed to accommodate the types of
signals frequently found in motor drives. The VIN1, VIN2, and
VIN3 channels are simultaneously sampled inputs suitable for
stator current acquisition. The AUX0–AUX3 channels are
multiplexed and are suitable for slower moving inputs such as
temperature and bus voltage of the diode rectifier output in a
motor control application.
AD7861 supports acquisition of 2, 3 or 4 channels per group.
Converted channel results are stored in registers and the data
can be read in any order. The sampling and conversion time
for two channels is 8 µs, three channels is 11.2 µs, and four
channels is 14.4 µs (using a 12.5 MHz system clock).
Single 5 V dc Operation
Low power, digital process.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VDD = 5 V ؎ 5%; TA = –40؇C to +85؇C; REFIN = 2.5 V; Ext CLK @ 12.5 MHz, unless
otherwise noted)
AD7861–SPECIFICATIONS
Parameter
AD7861AP
Units
Conditions/Comments
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Error Match
Full-Scale Error
Full-Scale Error Match
11
2
2.5
Bits
Twos Complement Data Format
Integral Nonlinearity
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
9
Any Channel
Between Channels
Any Channel
4
4
13
Between Channels
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Isolation
M1 = 0
60
–60
–60
dB min
dB max
dB max
fIN = 1 kHz Sine Wave, fSAMPLE = 75 kHz
fIN = 1 kHz Sine Wave, fSAMPLE = 75 kHz
fIN = 1 kHz Sine Wave, fSAMPLE = 75 kHz
–58
–53
dB max
dB max
1 kHz Sine Wave Applied to Unselected Channels
1 kHz Sine Wave Applied to Unselected Channels
M1 = 1
REFERENCE
Input Voltage Range (REF IN)
Input Current
Onboard Reference Output (REF OUT)
Reference Tolerance
2.5
50
2.5
5
V
µA max
V
%
Reference Drive Capability
100
µA max
SAMPLE-AND-HOLD
Acquisition Time
Aperture Delay Time
Aperture Delay Time Match
Droop Rate
1.6
200
20
5
µs
20 CLK Cycles @ 12.5 MHz
ns max
ns max
mV/ms max
LOGIC
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Leakage Current
Input Capacitance
(VOH
(VOL
2
0.8
1
20
4.5
0.4
1
V min
V max
µA max
pF typ
V min
V max
µA max
)
)
ISOURCE Current = 20 µA, VDD = 5 V
ISINK Current = 400 µA, VDD = 5 V
Three-State Leakage Current
CONVERSION RATE
Conversion Time/Channel
40
2
CLK Cycles
CONVST
Pulsewidth
CLK Cycles min
ANALOG INPUTS
Nominal Input Level
Input Current
0–5
100
10
V
µA
pF
VIN1, VIN2, VIN3, AUX0–AUX3
Input Capacitance
SYSTEM CLOCK
6.25–12.5
MHz
POWER REQUIREMENTS
VDD
IDD
5
10
V dc
mA max
– 2 –
REV. B
AD7861
Table I. AD7861 Timing Parameters (TA = –40؇C to +85؇C and VDD = +5 V unless otherwise noted)
Number
Symbol
AD7861 Timing Requirements
Min
Max
Units
1
2
3
4
5
6
7
8
tsucsb_rdb
tsuaddr_rdb
CS Low Before Falling Edge of RD
ADDR Valid Before Falling Edge of RD
DATA Valid After Falling Edge of RD
RD Pulsewidth, Low
0
0
–
25
25
10
0
0
–
–
25
–
–
–
–
–
160
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
dlyrdb_data
pwlrdb
pwhrdb
RD Pulsewidth, High
thdrdb_data
thdrdb_addr
thdrdb_csb
DATA Hold After Rising Edge of RD
ADDR Hold After Rising Edge of RD
CS Hold After Rising Edge of RD
CLK Period
CLK Pulsewidth, High
CLK Pulsewidth, Low
9
t
t
t
perclk
pwhclk
pwlclk
80
20
20
10
11
12
–
–
tpwlresetb
RESET Pulsewidth, Low
2 × tperclk
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
)
CLK
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . . –0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . . –0.3 V to VDD
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280°C
1, 2
CS
7, 8
A0–A1
5
4
RD
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
6
3
DATA
BUS
Figure 1. Clock and Reset Timing
9
10
11
ORDERING GUIDE
CLK
Model
Temperature Range
Package Option
CLK
AD7861AP
–40°C to +85°C
P-44A
12
RESET
Figure 2. Write Cycle Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7861 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD7861
PIN DESCRIPTION
PIN CONFIGURATION
Pin
Mnemonic Type Description
1
AUX0
REFIN
AGND
REFOUT
S0
I/P
Auxiliary Input 0
Analog Reference Input
Analog Ground
2
I/P
6
5
4
3
2
1
44 43 42 41 40
3
GND
O/P
I/P
4
Internal 2.5 Analog Reference
Aux Channel Select 0
Aux Channel Select 1
Data Bit 0 LSB (Tied Low)
Data Bit 1
PIN 1
IDENTIFIER
D0
D1
7
8
39 NC
38 NC
5
6
S1
I/P
D2
9
37
VIN1
7
D0
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
GND
SUP
I/P
D3 10
36 V
DD
8
D1
D4
D5
11
12
35 SGND
34 DGND
AD7861
TOP VIEW
(Not to Scale)
9
D2
Data Bit 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D3
Data Bit 3
D6
D7
13
14
15
16
33 DGND
D4
Data Bit 4
CLK
32
D5
Data Bit 5
BUSY
NC
31
30
D8
D9
D6
Data Bit 6
D7
Data Bit 7
17
A0
29
D10
D8
Data Bit 8
19
26
27 28
18
20 21 22 23 24 25
D9
Data Bit 9
D10
D11
DGND
DGND
VDD
Data Bit 10
NC = NO CONNECT
Data Bit 11, MSB
Logic Ground
Logic Ground
+5 V Digital Supply
Conversion Mode Select 0
Conversion Mode Select 1
A/D Conversion Start
Chip Select
M0
M1
I/P
Pin Types
Pin Types
CONVST
CS
I/P
I/P = Input Pin
O/P = Output Pin
GND = Ground Pin
SUP = Supply Pin
I/P
RD
I/P
Read Input
RESET
A1
I/P
Chip Reset
I/P
Register Address Select 1
Register Address Select 0
No Connect
A0
I/P
NC
NC
O/P
I/P
BUSY
CLK
Busy, Conversion in Process
External Clock Input 6.25 MHz-12.5 MHz
Logic Ground
33–34 DGND
GND
GND
SUP
I/P
35
36
37
SGND
VDD
Signal Ground
+5 V Analog Supply
Analog Input 1
VIN1
38–39 NC
NC
I/P
No Connect
40
41
42
43
44
VIN2
Analog Input 2
VIN3
I/P
Analog Input 3
AUX3
AUX2
AUX1
I/P
Auxiliary Input 3
Auxiliary Input 2
Auxiliary Input 1
I/P
I/P
REV. B
–4–
AD7861
ANALOG INPUT BLOCK
The user must select which channels to convert using M0/M1, a
minimum of two clock cycles before the start of conversion.
The AD7861 is an 11-bit resolution, successive approximation
analog-to-digital (A/D) converter with twos complement output
data format. The analog input range is 0 V–5 V with a 2.5 V
reference as defined by the reference input pin (REFIN). The
AD7861 has an internal 2.5 V 5% reference, which is utilized
by connecting the reference output pin (REFOUT) to the
REFIN pin.
The AD7861 provides 4 auxiliary input channels which can be
individually multiplexed into the auxiliary ADC channel. Pins S0/
S1 are used to multiplex these auxiliary channels according to the
following table. It is important to note that the ADC performs a
series of conversions based on the input voltage on each pin
(including the AUX pin) at the start of the CONVST conversion
pulse. The user must select the auxiliary channel using S0/S1
a minimum of two clock cycles before the start of the conversion
sequence.
The A/D conversion time is determined by the system clock
frequency, which can range from 6.25 MHz to 12.5 MHz.
Forty clock cycles are required to complete each conversion.
There is a 4-channel simultaneous sample and hold amplifier
(SHA) at the AD7861 input stage. This allows up to 4 channels to
be simultaneously held and sequentially digitized. The SHA
acquisition time is 20 clock cycles and is independent of the
number of channels sampled.
S1
S0
Channel Selected
0
0
1
1
0
1
0
1
AUX0
AUX1
AUX2
AUX3
The minimum throughput time can be calculated as follows:
tAA = tSHA + (n × tCONV
)
where tAA = analog acquisition time, tSHA = SHA acquisition
time, n = # channels, tCONV = conversion time per channel
(40 clock cycles).
DIGITAL INTERFACE
The AD7861 is designed to interface with the ADSP-21xx
family of DSPs. The 12-bit parallel interface can also be used
with other DSPs and microcontrollers.
A/D conversions are initiated by an external analog sample
clock pin (CONVST).
The 11-bit A/D conversion output occupies the 11 most
significant bits of the 12-bit interface. The LSB (Data Bit 0) is
tied low.
The CONVST input can be run asynchronous to the AD7861
system clock. When CONVST is run asynchronous from CLK,
the falling edge of CLK subsequent to CONVST high initiates
the conversion.
REGISTER BASED INPUT/OUTPUT
To facilitate integration into most designs, a register based
input/output structure is provided. These registers can be
memory mapped into the user’s system along with other
memory mapped peripherals.
BUSY
The AD7861 BUSY pin goes low at the start of conversion, and
remains low for 40 clock cycles per channel. When BUSY goes
high, this indicates that the output data buffers have been
updated. Data from the previous conversion can be read up to
(n × 40 – 1) clock cycles after the start of conversion (n =
number of channels converted). Refer to Figure 3.
REGISTER ADDRESSING
Two address lines (A0 through A1) are used in conjunction with
control lines (CS, RD) to select registers VIN1, VIN2, VIN3, or
AUX. These control lines are active low. Timing and logical
sense is as for the ADSP-2100 family.
t
= (n x 40 –1) CLOCK CYCLES
= n x 40 CLOCK CYCLES
t
= 1 CLOCK CYCLE
t
Pin
Function
CLK
CS
Enables the AD7861 Register Interface
(n x 40 –1) CLOCK CYCLES
RD
Places the Internal Register on the Data Bus
BUSY
REGISTER LISTING
CONVST
The output of each channel is stored in its respective register.
The symbolic names and address locations are listed in the
following table.
OLD DATA VALID
NEW DATA VALID
DATA
Figure 3. Busy Pulse Timing
Name
A1
A0
Register Function
CHANNEL SELECTION
Determining which channels are converted is dependent on the
settings of M0 and M1. The available channel combinations are:
VIN1
VIN2
VIN3
AUX
0
0
1
1
0
1
0
1
A/D Conversion Result Channel VIN1
A/D Conversion Result Channel VIN2
A/D Conversion Result Channel VIN3
A/D Conversion Result Channel AUX
M1
M0
Channels Converted
0
0
1
1
0
1
0
1
VIN2, VIN3
VIN2, VIN3, AUX
VIN1, VIN2, VIN3
VIN1, VIN2, VIN3, AUX
REV. B
–5–
AD7861
DESCRIPTION OF THE REGISTERS
DIGITAL SIGNAL PROCESSOR INTERFACING
VIN1, VIN2, VIN3
These registers contain the results from
the conversion of the analog input voltages.
In the AD7861, this register contains the
conversion result of the auxiliary channel
which had been selected by S0, S1.
The AD7861 A/D converter is designed to be easily interfaced
to Analog Devices’ family of Digital Signal Processors (DSPs).
Figure 5 shows the interface between the AD7861 and the
ADSP-2101/2105/2115 16-bit fixed point DSP, and the ADSP-
2171 and ADSP-2181 DSP Microcomputers. FLAGOUT from
the DSP is used to initiate the AD7861 conversion and is also
used in conjunction with the BUSY signal to provide an end of
conversion interrupt for the DSP. With M0 and M1 tied low,
the AD7861 is set up in the VIN2, VIN3 channel conversion
mode. By mapping the 12-bit AD7861 data bus into the top 12
bits of the DSP data bus (D12–D23), full-scale outputs from the
AD7861 can be represented as 1.0 in fixed point arithmetic.
AUX
Reading Results
The A/D conversion results for channels VIN1, VIN2, VIN3
and AUX are stored in the VIN1, VIN2, VIN3 and AUX
registers respectively. The twos complement data is left justified
and the LSB (Data Bit 0) is set to zero. The relationship
between input voltage and output coding is shown in Figure 4.
OUTPUT
The AD7861 can operate with a clock frequency in the range of
6.25 MHz to 12.5 MHz. For the ADSP-2101/2105/2115 the
CLKOUT frequency is the system clock frequency. In the case
of the ADSP-2171/2181, the system clock is internally scaled, a
10 MHz system clock will result in a 20 MHz CLKOUT
frequency. If CLKOUT from the ADSP-2171/2181 is above
12.5 MHz, then an external clock divide down circuit will be
necessary.
FULL-SCALE
TRANSITION
CODE
01 1 1 1 1 1 1 1 1 1 0
FS = 5V
5V
2048
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
LSB =
ADDRESS BUS
0V
5V-1LSB
2.5
INPUT VOLTAGE
A0–A13
A0–A1
ADDRESS
DECODE
Figure 4. AD7861 Transfer Function
Power Supply Connections and Setup
The nominal power supply level (VDD) is +5 V 5%. The
positive power supply (VDD) should be connected to Pins 21
and 36. The SGND and DGND pins should be star point
connected to AGND at a point close to the AD7861.
CS
DMS
EN
ADSP-2101/
ADSP-2105/
ADSP-2115–12MHz
BUSY
IRQ2
AD7861
CONVST
FLAGOUT
ADSP-2171–10MHz
ADSP-2181–10MHz
RD
CLK
M0
RD
CLKOUT
Power supplies should be bypassed at the power pins using a
0.1 µF capacitor. A 200 nF capacitor should also be connected
between REFIN and SGND.
M1
D0–D23
D0–D11*
DATA BUS
Figure 5. ADI Digital Signal Processor/Microcomputer
Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leadless Chip Carrier
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
IDENTIFIER
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
REV. B
–6–
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