AD7874ANZ_技术文档

2

LC MOS 4-Channel, 12-Bit Simultaneous

a

Sampling Data Acquisition System

AD7874

FEATURES

FUNCTIO NAL BLO CK D IAGRAM

Four On-Chip Track/ Hold Am plifiers

Sim ultaneous Sam pling of 4 Channels

Fast 12-Bit ADC w ith 8 ␮s Conversion Tim e/ Channel

29 kHz Sam ple Rate for All Four Channels

On-Chip Reference

V_DDV_DD

INT CS

RD CONVST

INTERNAL

CLOCK

CONTROL LOGIC

CLK

TRACK/

HOLD 1

V

؎10 V Input Range

IN1

؎5 V Supplies

TRACK/

HOLD 2

V

COMP

IN2

APPLICATIONS

Sonar

Motor Controllers

Adaptive Filters

Digital Signal Processing

MUX

SAR

TRACK/

HOLD 3

V

IN3

DATA

DB0

REGISTERS

DB11

TRACK/

HOLD 4

V

IN4

REFERENCE

BUFFER

12-BIT

DAC

REF IN

AD7874

GENERAL D ESCRIP TIO N

3V

REFERENCE

REF OUT

T he AD7874 is a four-channel simultaneous sampling, 12-bit

data acquisition system. T he part contains a high speed 12-bit

ADC, on-chip reference, on-chip clock and four track/hold am-

plifiers. T his latter feature allows the four input channels to be

sampled simultaneously, thus preserving the relative phase

information of the four input channels, which is not possible if

all four channels share a single track/hold amplifier. T his makes

the AD7874 ideal for applications such as phased-array sonar

and ac motor controllers where the relative phase information is

important.

V_SS

AGND DGND

P RO D UCT H IGH LIGH TS

1. Simultaneous Sampling of Four Input Channels.

Four input channels, each with its own track/hold amplifier,

allow simultaneous sampling of input signals. T rack/hold ac-

quisition time is 2 µs, and the conversion time per channel is

8 µs, allowing 29 kHz sample rate for all four channels.

T he aperture delay of the four track/hold amplifiers is small and

specified with minimum and maximum limits. T his allows sev-

eral AD7874s to sample multiple input channels simultaneously

without incurring phase errors between signals connected to

several devices. A reference output/reference input facility also

allows several AD7874s to be driven from the same reference

source.

2. T ight Aperture Delay Matching.

T he aperture delay for each channel is small and the aperture

delay matching between the four channels is less than 4 ns.

Additionally, the aperture delay specification has upper and

lower limits allowing multiple AD7874s to sample more than

four channels.

3. Fast Microprocessor Interface.

In addition to the traditional dc accuracy specifications such as

linearity, full-scale and offset errors, the AD7874 is also fully

specified for dynamic performance parameters including distor-

tion and signal-to-noise ratio.

T he high speed digital interface of the AD7874 allows direct

connection to all modern 16-bit microprocessors and digital

signal processors.

T he AD7874 is fabricated in Analog Devices’ Linear Compat-

ible CMOS (LC²MOS) process, a mixed technology process

that combines precision bipolar circuits with low-power CMOS

logic. T he part is available in a 28-pin, 0.6" wide, plastic or her-

metic dual-in-line package (DIP), in a 28-terminal leadless ce-

ramic chip carrier (LCCC) and in a 28-pin SOIC.

REV. C

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

(V = +5 V, V = –5 V, AGND = DGND = 0 V, REF IN = +3 V, f_CLK= 2.5 MHz

DD

SS

external. All specifications T_MINto T_MAXunless otherwise noted.)

AD7874–SPECIFICATIONS

P aram eter

A Version B Version S Version Units

Test Conditions/Com m ents

SAMPLE-AND-HOLD

Acquisition T ime²to 0.01%

Droop Rate^{2, 3}

2

1

500

0

2

1

500

0

2

500

0

µs max

mV/ms max

kHz typ

ns min

–3 dB Small Signal Bandwidth³

Aperture Delay²

V_IN= 500 mV p-p

40

200

4

40

200

4

40

200

4

ns max

ps typ

ns max

Aperture Jitter^{2, 3}

Aperture Delay Matching²

SAMPLE-AND-HOLD AND ADC

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio

T otal Harmonic Distortion

Peak Harmonic or Spurious Noise

Intermodulation Distortion

2nd Order T erms

70

–78

71

–80

70

–78

dB min

dB max

f_IN= 10 kHz Sine Wave, f_SAMPLE= 29 kHz

fa = 9 kHz, fb = 9.5 kHz, f_SAMPLE= 29 kHz

–80

dB max

3rd Order T erms

Channel-to-Channel Isolation²

DC ACCURACY

Resolution

Relative Accuracy

12

±1

±5

5

12

±1/2

±1

±5

5

12

±1

±5

5

Bits

LSB max

Differential Nonlinearity

Positive Full-Scale Error⁴

Negative Full-Scale Error⁴

Full-Scale Error Match

Bipolar Zero Error

No Missing Codes Guaranteed

Any Channel

Between Channels

Any Channel

Between Channels

±5

4

±5

4

±5

4

Bipolar Zero Error Match

ANALOG INPUT S

Input Voltage Range

Input Current

±10

±600

±10

±600

±10

±600

Volts

µA max

REFERENCE OUT PUT S

REF OUT

3

V nom

REF OUT Error @ +25°C

T _MINto T _MAX

±0.33

±1

±0.33

±1

±0.33

±1

% max

REF OUT T emperature Coefficient

Reference Load Change

±35

±1

±35

±1

±35

±2

ppm/°C typ

mV max

Reference Load Current Change (0–500 µA)

Reference Load Should Not Be Changed During Conversion

REFERENCE INPUT

Input Voltage Range

Input Current

2.85/3.15 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%

±1

µA max

Input Capacitance³

10

pF max

LOGIC INPUT S

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

±10

10

2.4

0.8

±10

10

2.4

0.8

±10

10

V min

V_DD= 5 V ± 5%

V_IN= 0 V to V_DD

V max

µA max

pF max

3

Input Capacitance, C_IN

LOGIC OUT PUT S

Output High Voltage, V_OH

Output Low Voltage, V_OL

DB0–DB11

4.0

0.4

4.0

0.4

4.0

0.4

V min

V max

V_DD= 5 V ± 5%; I_SOURCE= 40 µA

V_DD= 5 V ± 5%; I_SINK= 1–6 mA

Floating-State Leakage Current

±10

µA max

V_IN= 0 V to V_DD

Floating-State Output Capacitance 10

Output Coding

10

pF max

2s COMPLEMENT

POWER REQUIREMENT S

V_DD

V_SS

+5

–5

+5

–5

+5

–5

V nom

±5% for Specified Performance

I_DD

I_SS

18

12

150

18

12

150

18

12

150

mA max

mW max

CS = RD = CONVST = +5 V; T ypically 12 mA

CS = RD = CONVST = +5 V; T ypically 8 mA

CS = RD = CONVST = +5 V; T ypically 100 mW

Power Dissipation

NOT ES

¹T emperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.

²See T erminology.

³Sample tested @ +25°C to ensure compliance.

⁴Measured with respect to the REF IN voltage and includes bipolar offset error.

⁵For capacitive loads greater than 50 pF a series resistor is required.

Specifications subject to change without notice.

–2–

REV. C

AD7874

(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = O V, t_CLK= 2.5 MHz external unless

otherwise noted.)

DD

SS

1

TIMING CHARACTERISTICS

P aram eter

A, B Versions

S Version

Units

Conditions/Com m ents

t₁

t₂

t₃

t₄

t₅

50

0

60

0

50

0

70

0

ns min

ns max

ns min

ns max

ns min

µs min

µs max

µs min

µs max

CONVST Pulse Width

CS to RD Setup T ime

RD Pulse Width

CS to RD Hold T ime

RD to INT Delay

60

57

5

45

130

31

32.5

31

35

10

60

70

5

50

150

31

32.5

31

35

10

2

t₆

t₇

Data Access T ime after RD

Bus Relinquish T ime after RD

3

t₈

t_CONV

Delay T ime between Reads

CONVST to INT, External Clock

CONVST to INT, Internal Clock

Minimum Input Clock Period

t_CLK

NOT ES

¹T iming Specifications in bold pr int are 100% production tested. All other times are sample tested at +25 °C to ensure compliance. All input signals are specified with

tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

²t₆is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

³t₇is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. T he measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t ₇, quoted in the timing characteristics is the true bus relinquish

time of the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

1.6mA

ABSO LUTE MAXIMUM RATINGS*

(T _A= +25°C unless otherwise noted)

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

TO OUTPUT

+2.1V

50pF

V_SSto AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

V_INto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V_DD

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating T emperature Range

200µA

Figure 1. Load Circuit for Access Tim e

1.6mA

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . 1,000 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

TO OUTPUT

+2.1V

50pF

200µA

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Figure 2. Load Circuit for Bus Relinquish Tim e

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7874 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–3–

AD7874

TERMINO LO GY

P IN CO NFIGURATIO NS

D IP and SO IC

ACQ UISITIO N TIME

Acquisition T ime is the time required for the output of the

track/hold amplifiers to reach their final values, within ±1/2

LSB, after the falling edge of INT (the point at which the track/

holds return to track mode). T his includes switch delay time,

slewing time and settling time for a full-scale voltage change.

V

1

2

28

27

26

V

IN1

IN4

IN3

SS

IN2

V

3

DD

INT

CONVST

RD

4

25 REF OUT

24 REF IN

23 AGND

22 DB0 (LSB)

21 DB1

AP ERTURE D ELAY

Aperture Delay is defined as the time required by the internal

switches to disconnect the hold capacitors from the inputs. T his

produces an effective delay in sample timing. It is measured by

applying a step input and adjusting the CONVST input position

until the output code follows the step input change.

5

6

AD7874

TOP VIEW

(Not to Scale)

CS

7

CLK

8

V

9

20 DB2

DD

10

DB11 (MSB)

19 DB3

AP ERTURE D ELAY MATCH ING

Aperture Delay Matching is the maximum deviation in aperture

delays across the four on-chip track/hold amplifiers.

DB10 11

12

18 DB4

DB9

17 DB5

DB8 13

14

16 DB6

AP ERTURE JITTER

DGND

15 DB7

Aperture Jitter is the uncertainty in aperture delay caused by

internal noise and variation of switching thresholds with signal

level.

LCCC

D RO O P RATE

Droop Rate is the change in the held analog voltage resulting

from leakage currents.

4

3

2

28 27 26

1

25

24

23

5

6

CONVST

RD

REF OUT

REF IN

AGND

CH ANNEL-TO -CH ANNEL ISO LATIO N

7

CS

AD7874

TOP VIEW

(Not to Scale)

Channel-to-Channel Isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 1 kHz signal to the other three inputs. T he figure given is

the worst case across all four channels.

8

22 DB0 (LSB)

CLK

9

21

20

V

DB1

DB2

DD

10

11

DB11 (MSB)

DB10

19 DB3

SNR, TH D , IMD

12 13 14 15 16 17 18

See DYNAMIC SPECIFICAT IONS section.

–4–

REV. C

AD7874

P IN FUNCTIO N D ESCRIP TIO N

P in

Mnem onic

D escription

1

V_IN1

Analog Input Channel 1. T his is the first of the four input channels to be converted in a con-

version cycle. Analog input voltage range is ±10 V.

2

3

4

5

V_IN2

Analog Input Channel 2. Analog input voltage range is ±10 V.

V_DD

Positive supply voltage, +5 V ± 5%. T his pin should be decoupled to AGND.

Interrupt. Active low logic output indicating converter status. See Figure 7.

INT

CONVST

Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its

hold mode and starts conversion. T he four channels are converted sequentially, Channel 1 to

Channel 4. T he CONVST input is asynchronous to CLK and independent of CS and RD.

6

RD

Read. Active low logic input. T his input is used in conjunction with CS low to enable the

data outputs. Four successive reads after a conversion will read the data from the four chan-

nels in the sequence, Channel 1, 2, 3, 4.

7

8

CS

Chip Select. Active low logic input. T he device is selected when this input is active.

CLK

Clock Input. An external T T L-compatible clock may be applied to this input pin. Alterna-

tively, tying this pin to V_SSenables the internal laser trimmed clock oscillator.

9

V_DD

Positive Supply Voltage, +5 V ± 5%. Same as Pin 3; both pins must be tied together at the

package. T his pin should be decoupled to DGND.

10

DB11

Data Bit 11 (MSB). T hree-state T T L output. Output coding is 2s complement.

Data Bit 10 to Data Bit 8. T hree-state T T L outputs.

11–13

14

DB10–DB8

DGND

DB7–DB1

DB0

Digital Ground. Ground reference for digital circuitry.

Data Bit 7 to Data Bit 1. T hree-state T T L outputs.

15–21

22

Data Bit 0 (LSB). T hree-state T T L output.

23

AGND

Analog Ground. Ground reference for track/hold, reference and DAC.

24

REF IN

Voltage Reference Input. T he reference voltage for the part is applied to this pin. It is inter-

nally buffered, requiring an input current of only ±1 µA. T he nominal reference voltage for

correct operation of the AD7874 is 3 V.

25

REF OUT

Voltage Reference Output. T he internal 3 V analog reference is provided at this pin. T o oper-

ate the AD7874 with internal reference, REF OUT is connected to REF IN. T he external

load capability of the reference is 500 µA.

26

27

28

V_SS

Negative Supply Voltage, –5 V ± 5%.

V_IN3

V_IN4

Analog Input Channel 3. Analog input voltage range is ±10 V.

Analog Input Channel 4. Analog input voltage range is ±10 V.

O RD ERING GUID E

Relative

Tem perature

Range

SNR

(dBs)

Accuracy

(LSB)

P ackage

O ption²

Model¹

AD7874AN

AD7874BN

AD7874AR

AD7874BR

AD7874AQ

AD7874BQ

AD7874SQ³

AD7874SE³

–40°C to +85°C

70 min

72 min

70 min

72 min

70 min

72 min

±1 max

±1/2 max

±1 max

±1/2 max

±1 max

±1/2 max

±1 max

N-28

R-28

Q-28

E-28A

–55°C to +125°C 70 min

NOT ES

¹T o order MIL-ST D-883, Class B processed parts, add /883B to part number. Contact

¹our local sales office for military data sheet and availability.

²E = Leaded Ceramic Chip Carrier; N = Plastic DIP; Q = Cerdip; R = SOIC.

³Available to /883B processing only.

REV. C

–5–

AD7874

CO NVERTER D ETAILS

EXTERNAL REFERENCE

T he AD7874 is a complete 12-bit, 4-channel data acquisition

system. It is comprised of a 12-bit successive approximation

ADC, four high speed track/hold circuits, a four-channel analog

multiplexer and a 3 V Zener reference. T he ADC uses a succes-

sive approximation technique and is based on a fast-settling,

voltage switching DAC, a high speed comparator, a fast CMOS

SAR and high speed logic.

In some applications, the user may require a system reference or

some other external reference to drive the AD7874 reference in-

put. Figure 4 shows how the AD586 5 V reference can be used

to provide the 3 V reference required by the AD7874 REF IN.

+

15V

+V

IN

V

7R*

IN1

TO INTERNAL

COMPARATOR

GND

Conversion is initiated on the rising edge of CONVST. All four

input track/holds go from track to hold on this edge. Conversion

is first performed on the Channel 1 input voltage, then Channel

2 is converted and so on. T he four results are stored in on-chip

registers. When all four conversions have been completed, INT

goes low indicating that data can be read from these locations.

T he conversion sequence takes either 78 or 79 rising clock edges

depending on the synchronization of CONVST with CLK. In-

ternal delays and reset times bring the total conversion time

from CONVST going high to INT going low to 32.5 µs maxi-

mum for a 2.5 MHz external clock. T he AD7874 uses an im-

plicit addressing scheme whereby four successive reads to the

same memory location access the four data words sequentially.

T he first read accesses Channel 1 data, the second read accesses

Channel 2 data and so on. Individual data registers cannot be

accessed independently.

V

OUT

TRACK/HOLD 1

AD586

10kΩ

2.1R*

3R*

REF

IN

1kΩ

TO ADC

REFERENCE

CIRCUITRY

15kΩ

AGND

AD7874**

*R = 3.6kΩ TYP

**ADDITIONAL PINS OMITTED FOR CLARITY

Figure 4. AD586 Driving AD7874 REF IN

TRACK-AND -H O LD AMP LIFIER

INTERNAL REFERENCE

T he track-and-hold amplifier on each analog input of the

AD7874 allows the ADC to accurately convert an input sine

wave of 20 V p-p amplitude to 12-bit accuracy. T he input band-

width of the track/hold amplifier is greater than the Nyquist rate

of the ADC even when the ADC is operated at its maximum

throughput rate. T he small signal 3 dB cutoff frequency occurs

typically at 500 kHz.

T he AD7874 has an on-chip temperature compensated buried

Zener reference which is factory trimmed to 3 V ± 10 mV (see

Figure 3). T he reference voltage is provided at the REF OUT

pin. T his reference can be used to provide both the reference

voltage for the ADC and the bipolar bias circuitry. T his is

achieved by connecting REF OUT to REF IN.

T he four track/hold amplifiers sample their respective input

channels simultaneously. T he aperture delay of the track/hold

circuits is small and, more importantly, is well matched across

the four track/holds on one device and also well matched from

device to device. T his allows the relative phase information be-

tween different input channels to be accurately preserved. It also

allows multiple AD7874s to sample more than four channels

simultaneously.

V_DD

TEMPERATURE

COMPENSATION

AD7874

T he operation of the track/hold amplifiers is essentially transpar-

ent to the user. Once conversion is initiated, the four channels

are automatically converted and there is no need to select which

channel is to be digitized.

V

SS

REF OUT

Figure 3. AD7874 Internal Reference

ANALO G INP UT

T he reference can also be used as a reference for other compo-

nents and is capable of providing up to 500 µA to an external

load. In systems using several AD7874s, using the REF OUT of

one device to provide the REF IN for the other devices ensures

good full-scale tracking between all the AD7874s. Because the

AD7874 REF IN is buffered, each AD7874 presents a high im-

pedance to the reference so one AD7874 REF OUT can drive

several AD7874 REF INs.

T he analog input of Channel 1 of the AD7874 is as shown in

Figure 4. T he analog input range is ±10 V into an input resis-

tance of typically 30 kΩ. T he designed code transitions occur

midway between successive integer LSB values (i.e., 1/2 LSB,

3/2 LSBs, 5/2 LSBs, . . . FS – 3/2 LSBs). T he output code is

2s complement binary with 1 LSB = FS/4096 = 20 V/4096 =

4.88 mV. T he ideal input/output transfer function is shown in

Figure 5.

T he maximum recommended capacitance on REF OUT for

normal operation is 50 pF. If the reference is required for other

system uses, it should be decoupled to AGND with a 200 Ω re-

sistor in series with a parallel combination of a 10 µF tantalum

capacitor and a 0.1 µF ceramic capacitor.

–6–

REV. C

AD7874

Gain error can be adjusted at either the first code transition

(ADC negative full scale) or the last code transition (ADC posi-

tive full scale). T he trim procedures for both cases are as

follows:

OUTPUT

CODE

011...111

011...110

P ositive Full-Scale Adjust

Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V₁. Adjust

R2 until the ADC output code flickers between 0111 1111 1110

and 0111 1111 1111.

000...010

000...001

000...000

–

FS

2

Negative Full-Scale Adjust

+

FS

2

– 1LSB

111...111

111...110

Apply a voltage of –9.9976 V ( –FS + 1/2 LSB) at V₁and adjust

R2 until the ADC output code flickers between 1000 0000 0000

and 1000 0000 0001.

FS=20V

FS

1LSB =

4096

100...001

100...000

An alternative scheme for adjusting full-scale error in systems

which use an external reference is to adjust the voltage at the

REF IN pin until the full-scale error for any of the channels is

adjusted out. T he good full-scale matching of the channels will

ensure small full-scale errors on the other channels.

0V

INPUT VOLTAGE

Figure 5. Input/Output Transfer Function

TIMING AND CO NTRO L

Conversion is initiated on the AD7874 by asserting the

CONVST input. T his CONVST input is an asynchronous input

which is independent of the ADC clock. T his is essential for

applications where precise sampling in time is important. In

these applications, the signal sampling must occur at exactly

equal intervals to minimize errors due to sampling uncertainty

or jitter. In these cases, the CONVST input is driven from a

timer or precise clock source. Once conversion is started,

CONVST should not be asserted again until conversion is com-

plete on all four channels.

O FFSET AND FULL-SCALE AD JUSTMENT

In most Digital Signal Processing (DSP) applications, offset and

full-scale errors have little or no effect on system performance.

Offset error can always be eliminated in the analog domain by

ac coupling. Full-scale error effect is linear and does not cause

problems as long as the input signal is within the full dynamic

range of the ADC. Invariably, some applications will require

that the input signal span the full analog input dynamic range.

In such applications, offset and full-scale error will have to be

adjusted to zero.

In applications where precise time interval sampling is not criti-

cal, the CONVST pulse can be generated from a microproces-

sor WRIT E or READ line gated with a decoded address

(different to the AD7874 CS address). CONVST should not be

derived from a decoded address alone because very short

CONVST pulses (which may occur in some microprocessor sys-

tems as the address bus is changing at the start of an instruction

cycle) could initiate a conversion.

Figure 6 shows a circuit which can be used to adjust the offset

and full-scale errors on the AD7874 (Channel 1 is shown for ex-

ample purposes only). Where adjustment is required, offset er-

ror must be adjusted before full-scale error. T his is achieved by

trimming the offset of the op amp driving the analog input of

the AD7874 while the input voltage is a 1/2 LSB below analog

ground. T he trim procedure is as follows: apply a voltage of

–2.44 mV (–1/2 LSB) at V₁in Figure 6 and adjust the op amp

offset voltage until the ADC output code flickers between 1111

1111 1111 and 0000 0000 0000.

All four track/hold amplifiers go from track to hold on the rising

edge of the CONVST pulse. T he four track/hold amplifiers re-

main in their hold mode while all four channels are converted.

T he rising edge of CONVST also initiates a conversion on the

Channel 1 input voltage (V_IN1). When conversion is complete

on Channel 1, its result is stored in Data Register 1, one of four

on-chip registers used to store the conversion results. When the

result from the first conversion is stored, conversion is initiated

on the voltage held by track/hold 2. When conversion has been

completed on the voltage held by track/hold 4 and its result is

stored in Data Register 4, INT goes low to indicate that the

conversion process is complete.

INPUT

RANGE = ±10V

V

1

R1

10kΩ

R2

500Ω

V

IN1

R4

10kΩ

AD7874*

R5

R3

10kΩ

T he sequence in which the channel conversions takes place is

automatically taken care of by the AD7874. T his means that the

user does not have to provide address lines to the AD7874 or

worry about selecting which channel is to be digitized.

AGND

Reading data from the device consists of four read operations to

the same microprocessor address. Addressing of the four

on-chip data registers is again automatically taken care of by the

AD7874.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 6. AD7874 Full-Scale Adjust Circuit

REV. C

–7–

AD7874

T he first read operation to the AD7874 after conversion always

accesses data from Data Register 1 (i.e., the conversion result

from the V_IN1input). INT is reset high on the falling edge of

RD during this first read operation. T he second read always ac-

cesses data from Data Register 2 and so on. T he address pointer

is reset to point to Data Register 1 on the rising edge of

CONVST. A read operation to the AD7874 should not be at-

tempted during conversion. T he timing diagram for the

AD7874 conversion sequence is shown in Figure 7.

TRACK/HOLDS GO

INTO HOLD

t₁

t_CONV

CONVST

INT

t_ACQUISITION

t₅

t₈

CS

RD

t₂

t₄

t₇

t₃

t₆

CH1

DATA

CH4

DATA

CH2

DATA

CH3 HIGH-

HIGH-

Z

HIGH-

Z

HIGH-Z

HIGH-IMPEDANCE

DATA

Z

TIMES t₂, t₃, t₄, t₆, t₇, AND t₈ARE THE SAME FOR ALL FOUR READ OPERATIONS.

Figure 7. AD7874 Tim ing Diagram

Figure 8. AD7874 FFT Plot

Effective Num ber of Bits

T he formula given in Equation 1 relates the SNR to the number

of bits. Rewriting the formula, as in Equation 2, it is possible to

get a measure of performance expressed in effective number of

bits (N).

AD 7874 D YNAMIC SP ECIFICATIO NS

T he AD7874 is specified and 100% tested for dynamic perfor-

mance specifications as well as traditional dc specifications such

as Integral and Differential Nonlinearity. T hese ac specifications

are required for the signal processing applications such as

phased array sonar, adaptive filters and spectrum analysis.

T hese applications require information on the ADC’s effect on

the spectral content of the input signal. Hence, the parameters

for which the AD7874 is specified include SNR, harmonic dis-

tortion, intermodulation distortion and peak harmonics. T hese

terms are discussed in more detail in the following sections.

SNR −1. 76

N =

(2)

6.02

T he effective number of bits for a device can be calculated di-

rectly from its measured SNR.

Figure 9 shows a typical plot of effective number of bits versus

frequency for an AD7874BN with a sampling frequency of

29 kHz. T he effective number of bits typically falls between

11.75 and 11.87 corresponding to SNR figures of 72.5 dB and

73.2 dB.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal to noise ratio at the output of the

ADC. T he signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (fs/2) excluding dc. SNR is depen-

dent upon the number of quantization levels used in the digiti-

zation process; the more levels, the smaller the quantization

noise. T he theoretical signal to noise ratio for a sine wave input

is given by

SNR = (6.02N + 1.76) dB

where N is the number of bits.

(1)

T hus for an ideal 12-bit converter, SNR = 74 dB.

T he output spectrum from the ADC is evaluated by applying a

sine wave signal of very low distortion to the V_INinput which is

sampled at a 29 kHz sampling rate. A Fast Fourier T ransform

(FFT ) plot is generated from which the SNR data can be ob-

tained. Figure 8 shows a typical 2048 point FFT plot of the

AD7874BN with an input signal of 10 kHz and a sampling

frequency of 29 kHz. T he SNR obtained from this graph is

73.2 dB. It should be noted that the harmonics are taken into

account when calculating the SNR.

z

Figure 9. Effective Num bers of Bits vs. Frequency

–8–

REV. C

AD7874

Total H ar m onic D istor tion (TH D )

P eak H ar m onic or Spur ious Noise

T otal Harmonic Distortion (T HD) is the ratio of the rms sum

of harmonics to the rms value of the fundamental. For the

AD7874, T HD is defined as

Harmonic or Spurious Noise is defined as the ratio of the rms

value of the next largest component in the ADC output spec-

trum (up to fs/2 and excluding dc) to the rms value of the fun-

damental. Normally, the value of this specification will be

determined by the largest harmonic in the spectrum, but for

parts where the harmonics are buried in the noise floor the peak

will be a noise peak.

2

V₂+V₃+V₄+V₅+V₆

THD = 20 log

V₁

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonic. T he T HD is also derived from the FFT plot of

the ADC output spectrum.

AC Linear ity P lot

When a sine wave of specified frequency is applied to the V_INin-

put of the AD7874 and several million samples are taken, a his-

togram showing the frequency of occurrence of each of the 4096

ADC codes can be generated. From this histogram data it is

possible to generate an ac integral linearity plot as shown in Fig-

ure 11. T his shows very good integral linearity performance

from the AD7874 at an input frequency of 10 kHz. T he absence

of large spikes in the plot shows good differential linearity. Sim-

plified versions of the formulae used are outlined below.

Inter m odulation D istor tion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for

which neither m or n are equal to zero. For example, the second

order terms include (fa + fb) and (fa – fb) while the third order

terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

(V(i) −V(o)) 4096

INL(i) =

− i

V( fs) −V(o)

Using the CCIF standard where two input frequencies near the

top end of the input bandwidth are used, the second and third

order terms are of different significance. T he second order terms

are usually distanced in frequency from the original sine waves

while the third order terms are usually at a frequency close to

the input frequencies. As a result, the second and third order

terms are specified separately. T he calculation of the intermodu-

lation distortion is as per the T HD specification where it is the

ratio of the rms sum of the individual distortion products to the

rms amplitude of the fundamental expressed in dBs. In this case,

the input consists of two, equal amplitude, low distortion sine

waves. Figure 10 shows a typical IMD plot for the AD7874.

where INL(i) is the integral linearity at code i. V(fs) and V(o) are

the estimated full-scale and offset transitions, and V(i) is the es-

timated transition for the i^thcode.

V(i), the estimated code transition point is derived as follows:

π cum(i)

[

]

V(i) = −A Cos

N

where A is the peak signal amplitude, N is the number of histo-

gram samples

i

and cum(i) =

V(n)occurrences

∑

n=o

Figure 11. AD7874 AC INL Plot

Figure 10. AD7874 IMD Plot

REV. C

–9–

AD7874

MICRO P RO CESSO R INTERFACING

TIMER

T he AD7874 high speed bus timing allows direct interfacing to

DSP processors as well as modern 16-bit microprocessors.

Suitable microprocessor interfaces are shown in Figures 12

through 16.

PA2

PA0

ADDRESS BUS

ADDR

DECODE

CONVST

CS

AD 7874–AD SP -2100 Inter face

MEN

Figure 12 shows an interface between the AD7874 and the

ADSP-2100. Conversion is initiated using a timer which allows

very accurate control of the sampling instant on all four chan-

nels. T he AD7874 INT line provides an interrupt to the ADSP-

2100 when conversion is completed on all four channels. T he

four conversion results can then be read from the AD7874 using

four successive reads to the same memory address. T he follow-

ing instruction reads one of the four results (this instruction is

repeated four times to read all four results in sequence):

EN

AD7874*

TMS32010

INT

RD

DEN

DB11

DB0

MR0 = DM(ADC)

D15

D0

DATA BUS

where MR0 is the ADSP-2100 MR0 register and

ADC is the AD7874 address.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. AD7874–TMS32010 Interface

AD 7874–TMS320C25 Inter face

DMA13

TIMER

ADDRESS BUS

DMA0

Figure 14 shows an interface between the AD7874 and the

T MS320C25. As with the two previous interfaces, conversion is

initiated with a timer and the processor is interrupted when the

conversion sequence is completed. T he T MS320C25 does not

have a separate RD output to drive the AD7874 RD input di-

rectly. T his has to be generated from the processor ST RB and

R/W outputs with the addition of some logic gates. T he RD sig-

nal is OR-gated with the MSC signal to provide the one WAIT

state required in the read cycle for correct interface timing.

Conversion results are read from the AD7874 using the follow-

ing instruction:

CONVST

ADDR

DECODE

CS

DMS

EN

AD7874*

ADSP-2100

(ADSP-2101/

ADSP-2102)

IRQn

INT

RD

DMRD (RD)

DB11

DB0

IN D,ADC

where D is Data Memory address and

ADC is the AD7874 address.

DMD15

DMD0

DATA BUS

* ADDITIONAL PINS OMITTED FOR CLARITY

TIMER

A15

ADDRESS BUS

Figure 12. AD7874–ADSP-2100 Interface

A0

AD 7874–AD SP -2101/AD SP -2102 Inter face

T he interface outlined in Figure 12 also forms the basis for an

interface between the AD7874 and the ADSP-2101/ADSP-2102.

T he READ line of the ADSP-2101/ADSP-2102 is labeled RD.

In this interface, the RD pulse width of the processor can be

programmed using the Data Memory Wait State Control Regis-

ter. T he instruction used to read one of the four results is as

outlined for the ADSP-2100.

ADDR

CONVST

DECODE

CS

IS

EN

AD7874*

TMS320C25

INTn

INT

STRB

R/W

RD

AD 7874–TMS32010 Inter face

An interface between the AD7874 and the T MS32010 is shown

in Figure 13. Once again the conversion is initiated using an ex-

ternal timer and the T MS32010 is interrupted when all four

conversions have been completed. T he following instruction is

used to read the conversion results from the AD7874:

READY

MSC

DB11

DB0

D15

D0

IN D,ADC

DATA BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

where D is Data Memory address and

ADC is the AD7874 address.

Figure 14. AD7874–TMS320C25 Interface

–10–

REV. C

AD7874

Some applications may require that the conversion is initiated

by the microprocessor rather than an external timer. One option

is to decode the AD7874 CONVST from the address bus so

that a write operation starts a conversion. Data is read at the

end of the conversion sequence as before. Figure 16 shows an

example of initiating conversion using this method. Note that

for all interfaces, a read operation should not be attempted dur-

ing conversion.

AD 7874–8086 Inter face

Figure 16 shows an interface between the AD7874 and the 8086

microprocessor. Unlike the previous interface examples, the

microprocessor initiates conversion. T his is achieved by gating

the 8086 WR signal with a decoded address output (different to

the AD7874 CS address). T he AD7874 INT line is used to in-

terrupt the microprocessor when the conversion sequence is

completed. Data is read from the AD7874 using the following

instruction:

AD 7874–MC68000 Inter face

MOV AX,ADC

An interface between the AD7874 and the MC68000 is shown

in Figure 15. As before, conversion is initiated using an external

timer. T he AD7874 INT line can be used to interrupt the pro-

cessor or, alternatively, software delays can ensure that conver-

sion has been completed before a read to the AD7874 is

attempted. Because of the nature of its interrupts, the 68000

requires additional logic (not shown in Figure 15) to allow it to

be interrupted correctly. For further information on 68000 in-

terrupts, consult the 68000 users manual.

where AX is the 8086 accumulator and

ADC is the AD7874 address.

ADDRESS BUS

ADDR

8086

DECODE

CS

T he MC68000 AS and R/W outputs are used to generate a

separate RD input signal for the AD7874. CS is used to drive

the 68000 DTACK input to allow the processor to execute a

normal read operation to the AD7874. T he conversion results

are read using the following 68000 instruction:

AD7874*

LATCH

ALE

CONVST

RD

WR

RD

MOVE.W ADC,D0

DB11

DB0

where D0 is the 68000 D0 register and

ADC is the AD7874 address.

AD15

AD0

TIMER

A15

ADDRESS/DATA BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

ADDRESS BUS

A0

ADDR

CONVST

Figure 16. AD7874–8086 Interface

MC68000

DECODE

CS

RD

EN

DTACK

AD7874*

AS

R/W

DB11

DB0

D15

D0

DATA BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. AD7874–MC68000 Interface

REV. C

–11–

AD7874

AP P LICATIO NS

Vector Motor Contr ol

A block diagram of a vector motor control application using the

AD7874 is shown in Figure 17. T he position of the field is de-

rived by determining the current in each phase of the motor.

Only two phase currents need to be measured because the third

can be calculated if two phases are known. Channel 1 and

Channel 2 of the AD7874 are used to digitize this information.

T he current drawn by a motor can be split into two compo-

nents: one produces torque and the other produces magnetic

flux. For optimal performance of the motor, these two compo-

nents should be controlled independently. In conventional

methods of controlling a three-phase motor, the current (or

voltage) supplied to the motor and the frequency of the drive are

the basic control variables. However, both the torque and flux

are functions of current (or voltage) and frequency. T his cou-

pling effect can reduce the performance of the motor because,

for example, if the torque is increased by increasing the fre-

quency, the flux tends to decrease.

Simultaneous sampling is critical to maintain the relative phase

information between the two channels. A current sensing isola-

tion amplifier, transformer or Hall effect sensor is used between

the motor and the AD7874. Rotor information is obtained by

measuring the voltage from two of the inputs to the motor.

Channel 3 and Channel 4 of the AD7874 are used to obtain this

information. Once again the relative phase of the two channels

is important. A DSP microprocessor is used to perform the

mathematical transformations and control loop calculations on

the information fed back by the AD7874.

Vector control of an ac motor involves controlling phase in addi-

tion to drive and current frequency. Controlling the phase of the

motor requires feedback information on the position of the rotor

relative to the rotating magnetic field in the motor. Using this

information, a vector controller mathematically transforms the

three phase drive currents into separate torque and flux compo-

nents. T he AD7874, with its four-channel simultaneous sam-

pling capability, is ideally suited for use in vector motor control

applications.

DSP

MICROPROCESSOR

I_C

DAC

TORQUE & FLUX

CONTROL LOOP

CALCULATIONS &

TWO TO THREE

PHASE

I_B

V_B

V_A

3

DRIVE

CIRCUITRY

PHASE

MOTOR

DAC

I_A

INFORMATION

TORQUE

SETPOINT

ISOLATION

AMPLIFIERS

FLUX

SETPOINT

V

IN1

TRANSFORMATION

TO TORQUE &

FLUX CURRENT

COMPONENTS

V

IN2

AD7874*

V

IN3

V

IN4

VOLTAGE

ATTENUATORS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. Vector Motor Control Using the AD7874

–12–

REV. C

AD7874

MULTIP LE AD 7874s

the input signal connects to the buffer amplifier driving the ana-

log input of the ADC. If the shorting plug is omitted, a wire link

can be used to connect the input signal to the PCB component

grid.

Figure 18 shows a system where a number of AD7874s can be

configured to handle multiple input channels. T his type of con-

figuration is common in applications such as sonar, radar, etc.

T he AD7874 is specified with maximum and minimum limits on

aperture delay. T his means that the user knows the maximum

difference in the sampling instant between all channels. T his al-

lows the user to maintain relative phase information between the

different channels.

Microprocessor connections to the board are made via a 26-

contact IDC connector, SKT 8, the pinout for which is shown in

Figure 19. T his connector contains all data, control and status

signals of the AD7874 (with the exception of the CLK input

and the CONVST input which are provided via SKT 5 and

SKT 7, respectively). It also contains decoded R/W and STRB

inputs which are necessary for T MS32020 interfacing (and also

for 68000 interfacing although pin labels on the 68000 are dif-

ferent). Note that the AD7874 CS input must be decoded prior

to the AD7874 evaluation board.

A common read signal from the microprocessor drives the RD

input of all AD7874s. Each AD7874 is designated a unique ad-

dress selected by the address decoder. T he reference output of

AD7874 number 1 is used to drive the reference input of all

other AD7874s in the circuit shown in Figure 18. One REF

OUT pin can drive several AD7874 REF IN pins. Alternatively,

an external or system reference can be used to drive all REF IN

inputs. A common reference ensures good full-scale tracking be-

tween all channels.

SKT 1, SKT 2, SKT 3 and SKT 4 provide the inputs for V_IN1

_IN2, V_IN3, V_IN4respectively. Assuming LK1 to LK4 are in

,

V

place, these input signals are fed to four buffer amplifiers, IC1,

before being applied to the AD7874. T he use of an external

clock source is optional; there is a shorting plug (LK5) on the

AD7874 CLK input which must be connected to either –5 V

(for the ADCs own internal clock) or to SKT 5. SKT 6 and

SKT 7 provide the reference and CONVST inputs respectively.

Shorting plug LK6 provides the option of using the external ref-

erence or the ADCs own internal reference.

V

CH1

RD

V

CH2

CH3

CH4

AD7874(1)

CS

REF OUT

1

3

5

2

4

R/W

STRB

N/C

RD

CS

6

N/C

V

CH5

CH6

CH7

CH8

8

7

9

N/C

INT

RD

AD7874(2)

10

ADDRESS

DECODE

N/C

DB10

DB8

DB6

DB4

DB2

DB0

N/C

ADDRESS

CS

11

13

15

17

19

12

14

16

18

20

DB11

REF IN

DB9

DB7

DB5

DB3

DB1

REF IN

RD

V

CHm

V

21

23

25

22

24

26

CHm+1

CHm+2

CHm+3

AD7874(n)

CS

+

5V

GND

Figure 18. Multiple AD7874s in Multichannel System

Figure 19. SKT8, IDC Connector Pinout

P O WER SUP P LY CO NNECTIO NS

D ATA ACQ UISITIO N BO ARD

Figure 20 shows the AD7874 in a data acquisition circuit. T he

corresponding printed circuit board (PCB) layout and silkscreen

are shown in Figures 21 to 23. A 26-contact IDC connector pro-

vides for a microprocessor connection to the board.

T he PCB requires two analog power supplies and one 5 V digi-

tal supply. T he analog supplies are labeled V+ and V– and the

range for both supplies is 12 V to 15 V (see silkscreen in Figure

23). Connection to the 5 V digital supply is made via SKT 8.

T he +5 V supply and the –5 V supply required by the AD7874

are generated from voltage regulators (IC3 and IC4) on the V+

and V– supplies.

A component grid is provided near the analog inputs on the

PCB which may be used to provide antialiasing filters for the

analog input channels or to provide signal conditioning circuitry.

T o facilitate this option, four shorting plugs (labeled LK1 to

LK4 on the PCB) are provided on the analog inputs, one plug

per input. If the shorting plug for a particular channel is used,

REV. C

–13–

AD7874

IC3

78L05

+

V

CONVST

SKT6

C3

C7

C8

V_DD

C4

IC1

AD713

V_DD

LK1

SKT1

SKT2

SKT3

SKT8

11

V

IN1

CONVST

DB11

LK2

LK3

LK4

DATA BUS

22

8

DB0

INT

CS

V

IN2

5

+

5V

23, 24

V

IC2

R2 R1

^IN3AD7874

IC5

A

B

2

1

IC5

SKT4

3

V

RD

IN4

A

DGND

25, 26

REF IN

B

V_SS

AGND

DGND

REF

OUT

C1

C2

V_SS

CLK

LK5

B

OUT

A

IC4

V–

79L05

REFERENCE

SKT6

IN

C6

CLK

SKT5

C5

Figure 20. Data Acquisition Circuit Using the AD7874

Figure 21. PCB Silkscreen for Figure 20

–14–

REV. C

AD7874

Figure 22. PCB Com ponent Side Layout for the Circuit of Figure 20

Figure 23. PCB Solder Side Layout for the Circuit of Figure 20

REV. C

–15–

AD7874

SH O RTING P LUG O P TIO NS

CO MP O NENT LIST

T here are seven shorting plug options which must be set before

using the board. T hese are outlined below:

IC1

IC2

IC3

IC4

AD713 Quad Op Amp

AD7874 Analog-to-Digital Converter

MC78L05 +5 V Regulator

MC79L05 –5 V Regulator

74HC00 Quad NAND Gate

10 µF Capacitors

0.1 µF Capacitors

10 kΩ Pull-Up Resistors

Shorting Plugs

LK1–LK4

Connects the analog inputs to the buffer amplifi-

ers. T he analog inputs may also be connected to a

component grid for signal conditioning.

IC5

C1, C3, C5, C7, C9

C2, C4, C6, C8, C10

R1, R2

LK1, LK2, LK3

LK4, LK5, LK6

LK7

SKT 1, SKT 2, SKT 3,

SKT 4, SKT 5, SKT 6,

SKT 7

LK5

LK6

LK7

Selects either the AD7874 internal clock or an ex-

ternal clock source.

Selects either the AD7874 internal reference or an

external reference source.

Connects the AD7874 RD input directly to the

RD input of SKT 8 or to a decoded STRB and

R/W input. T his shorting plug setting depends on

the microprocessor, e.g., the T MS32020 and

68000 require a decoded RD signal.

BNC Sockets

SKT 8

26-Contact (2-Row) IDC Connector

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

P lastic (N-28)

SO IC (R-28)

Cer dip (Q -28)

LCCC (E-28A)

1

0.100 (2.54)

0.055 (1.40)

0.045 (1.14)

0.075

(1.91)

REF

0.064 (1.63)

0.028 (0.71)

0.022 (0.56)

28

NO. 1 PIN INDEX

0.050 ± 0.005

(1.27 ± 0.13)

BOTTOM VIEW

0.040 x 45°

(1.02 x 45°)

REF 3 PLCS

0.020 x 45°

(0.51 x 45°) REF

0.458 (11.63) ²

0.442 (11.23)

NOTES

1. THIS DIMENSION CONTROLS THE OVERALL PACKAGE

THICKNESS.

2. APPLIES TO ALL FOUR SIDES.

3. ALL TERMINALS ARE GOLD PLATED.

–16–

REV. C


型号：	AD7874ANZ
厂家：	Rochester Electronics
描述：	4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 信息通信管理光电二极管转换器
文件：	总17页 (文件大小：1097K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7874ANZ [ROCHESTER]

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