AD7895ANZ-2 [ROCHESTER]
1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8;
| 型号： | AD7895ANZ-2 |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8 光电二极管 |
| 文件： | 总13页 (文件大小：996K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 V, 12-Bit, Serial 3.8 s
a
ADC in 8-Pin Package
AD7895
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fast 12-Bit ADC with 3.8 s Conversion Time
8-Pin Mini-DlP and SOIC
REF IN
V
DD
Single 5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Selection of Input Ranges
؎10 V for AD7895-10
AD7895
TRACK/HOLD
؎2.5 V for AD7895-3
0 V to +2.5 V for AD7895-2
High Input Impedance
SIGNAL
SCALING*
V
IN
12-BIT
ADC
Low Power: 20 mW max
14-Bit Pin Compatible Upgrade (AD7894)
OUTPUT
REGISTER
CONVST
GND
BUSY
SCLK
SDATA
*AD7895-10, AD7895-3
GENERAL DESCRIPTION
The AD7895 is a fast 12-bit ADC that operates from a single
+5 V supply and is housed in a small 8-pin mini-DIP and 8-pin
SOIC. The part contains a 3.8 µs successive approximation A/D
converter, an on-chip track/hold amplifier, an on-chip clock and
a high speed serial interface.
PRODUCT HIGHLIGHTS
1. Fast, 12-Bit ADC in 8-Pin Package
The AD7895 contains a 3.8 µs ADC, a track/hold amplifier,
control logic and a high speed serial interface, all in an 8-pin
package. This offers considerable space saving over alterna-
tive solutions.
Output data from the AD7895 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.
2. Low Power, Single Supply Operation
The AD7895 operates from a single +5 V supply and
consumes only 20 mW. The automatic power-down mode,
where the part goes into power-down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7895 ideal for battery-powered or portable
applications.
In addition to the traditional dc accuracy specifications such as
linearity and full-scale and offset errors, the AD7895 is specified
for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.
The part accepts an analog input range of ±10 V (AD7895-10),
±2.5 V (AD7895-3), 0 V to 2.5 V (AD7895-2) and operates
from a single +5 V supply, consuming only 20 mW max.
3. High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.
The AD7895 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power down once
conversion is complete and “wakes up” before the next conver-
sion cycle.
The part is available in a small, 8-pin, 0.3" wide, plastic dual-in-
line package (mini-DIP) and in an 8-pin, small outline IC (SOIC).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
(VDD = +5 V, GND = 0 V, REF IN = +2.5 V.
AD7895–SPECIFICATIONS All specifications TMIN to TMAX unless otherwise noted)
Parameter
A Versionsl
B Versions
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE2
Signal to (Noise + Distortion) Ratio3
@ +25°C
70
70
–78
70
70
–78
dB min
dB min
dB max
fIN = 50 kHz Sine Wave, fSAMPLE = 200 kHz
TMIN to TMAX
Total Harmonic Distortion (THD)3
fIN = 50 kHz Sine Wave, fSAMPLE = 200 kHz,
Typically –87 dB
fIN = 50 kHz Sine Wave, fSAMPLE = 200 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 200 kHz
Peak Harmonic or Spurious Noise3
Intermodulation Distortion (IMD)3
2nd Order Terms
–89
–89
dB typ
–87
–87
–87
–87
dB typ
dB typ
3rd Order Terms
DC ACCURACY
Resolution
12
12
Bits
Minimum Resolution for which
No Missing Codes are Guaranteed
Relative Accuracy3
12
±1
±1
±3
12
±1
±1
±2
Bits
LSB max
LSB max
LSB max
Typically 0.4 LSB
Differential Nonlinearity3
Positive Full-Scale Error3
AD7895-2
Unipolar Offset Error
AD7895-10, AD7895-3 Only
Negative Full-Scale Error3
Bipolar Zero Error
±3
±2
LSB max
±3
±4
±2
±3
LSB max
LSB max
ANALOG INPUT
AD7895-10
Input Voltage Range
Input Resistance
AD7895-3
±10
24
±10
24
Volts
kΩ min
Input Voltage Range
Input Resistance
AD7895-2
±2.5
9
±2.5
9
Volts
kΩ min
Input Voltage Range
Input Current
0 to +2.5
500
0 to +2.5
500
Volts
nA max
REFERENCE INPUT
REF IN Input Voltage Range
Input Current
2.375/2.625
1
10
2.375/2.625
1
10
V min/V max
µA max
pF max
2.5 V ± 5%
Input Capacitance3
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
V max
µA max
pF ax
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
4
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Output Coding
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 200 µA
ISINK = 1.6 mA
AD7895-10, AD7895-3
AD7895-2
2s Complement
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Mode 1 Operation
3.8
9.8
0.5
3.8
9.8
0.5
µs max
µs max
µs max
Mode 2 Operation5
Track/Hold Acquisition Time3
POWER REQUIREMENTS
VDD
IDD
Power Dissipation
Power-Down Mode
IDD @ +25°C
+5
4
20
+5
4
20
V nom
mA max
mW max
±5% for Specified Performance
Digital Inputs @ VDD, VDD = 5 V ± 5%
Typically 16 mW
5
10
25
5
10
25
µA max
µA max
µW max
Digital Inputs @ GND, VDD = 5 V ± 5%
Digital Inputs @ GND, VDD = 5 V ± 5%
TMIN to TMAX
Power Dissipation @ +25°C
NOTES
1Temperature ranges are as follows: A, B Versions: –40°C to +85°C.
2Applies to Mode 1 operation. See section on “Operating Modes.”
3See Terminology.
4Sample tested @ +25°C to ensure compliance.
5This 9.8 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for
narrow CONVST pulse width the conversion time is effectively the “wake-up” time plus conversion time hence 9.8 µs. This can be seen from Figure 3. Note that if the CONVST pulse width
is greater than 6 µs then the effective conversion time will increase beyond 9.8 µs.
Specifications subject to change without notice.
REV. 0
–2–
AD7895
TIMING CHARACTERISTICS1, 2
(VDD = +5 V, GND = 0 V, REF IN = +2.5 V)
Parameter
A, B Versions
Units
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
40
ns min
ns min
ns min
ns max
ns min
ns max
CONVST Pulse Width
SCLK High Pulse Width
SCLK Low Pulse Width
Data Access Time after Falling Edge of SCLK, VDD = 5 V
Data Hold Time after Falling Edge of SCLK
352
352
603
10
± 5%
504
Bus Relinquish Time after Falling Edge of SCLK
NOTES
1 Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.4 V.
2The SCLK maximum frequency is 15 MHz. Care must be taken when interfacing to account for the data access time, t 4, and the setup time required for the user's
processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See “Serial Interface” section for more information.
3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t6, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD7895-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±17 V
AD7895-2, AD7895-3 . . . . . . . . . . . . . . . . . . . –5 V, +10 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W
Lead Temperature, Soldering
2.0mA
TO
OUTPUT
PIN
+1.6V
50pF
2.0mA
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ORDERING GUIDE
Model
Temperature Range
Linearity Error (LSB)
SNR (dB)
Package Option*
AD7895AN-2
AD7895AR-2
AD7895BR-2
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±1 LSB
±1 LSB
±1 LSB
70 dB
70 dB
70 dB
N-8
SO-8
SO-8
AD7895AN-10
AD7895AR-10
AD7895BR-10
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±1 LSB
±1 LSB
±1 LSB
70 dB
70 dB
70 dB
N-8
SO-8
SO-8
AD7895AN-3
AD7895AR-3
–40°C to +125°C
–40°C to +85°C
±1 LSB
±1 LSB
70 dB
70 dB
N-8
SO-8
*N = Plastic DIP, SO = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7895 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD7895
PIN FUNCTION DESCRIPTION
Pin
No.
Pin
Mnemonic
Description
1
REF IN
Voltage Reference Input. An external reference source should be connected to this pin to provide the refer-
ence voltage for the AD7895’s conversion process. The REF IN input is buffered on chip. The nominal ref-
erence voltage for correct operation of the AD7895 is +2.5 V.
2
VIN
Analog Input Channel. The analog input range is ±10 V (AD7895-10), ±2.5 V (AD7895-3) and 0 V to
+2.5 V (AD7895-2).
3
4
GND
Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.
SCLK
Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7895.
A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns
after this falling edge so that data can be accepted on the falling edge when a fast serial clock is used. The
serial clock input should be taken low at the end of the serial data transmission.
5
SDATA
Serial Data Output. Serial data from the AD7895 is provided at this output. The serial data is clocked out
by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is possible
because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 4).
Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data.
On the sixteenth falling edge of SCLK, the SDATA line is held for the data hold time and then is disabled
(three-stated). Output data coding is 2s complement for the AD7895-10, AD7895-3 and straight binary for
the AD7895-2.
6
7
BUSY
The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the
falling edge of CONVST and will return low when the conversion is complete.
CONVST
Convert Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold
mode, and conversion is initiated. If CONVST is low at the end of conversion, the part goes into power-
down mode. In this case, the rising edge of CONVST “wakes up” the part.
8
VDD
Positive supply voltage, +5 V ± 5%.
PIN CONFIGURATION
DIP and SOIC
V
REF IN
1
2
3
4
8
7
6
5
DD
AD7895
TOP VIEW
(Not to Scale)
CONVST
V
IN
GND
BUSY
SCLK
SDATA
REV. 0
–4–
AD7895
Relative Accuracy
TERMINOLOGY
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7895-10)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 × VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Positive Full-Scale Error (AD7895-3)
Thus for a 12-bit converter, this is 74 dB.
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal ( VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7895, it is defined as:
Positive Full-Scale Error (AD7895-2)
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar
Offset Error has been adjusted out.
2
V22 +V32 +V42 +V52 +V6
THD (dB)= 20 log
V1
Bipolar Zero Error (AD7895-10, AD7895-3)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (GND).
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Unipolar Offset Error (AD7895-2)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal 1 LSB.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Negative Full-Scale Error (AD7895-10)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 × VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Negative Full-Scale Error (AD7895-3)
Intermodulation Distortion
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF + 1 LSB) after Bipolar Zero
Error has been adjusted out.
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the VIN input of the AD7895. This means that the user must
wait for the duration of the track/hold acquisition time after the
end of conversion or after a step input change to VIN before
starting another conversion to ensure that the part operates to
specification.
The AD7895 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of
different significance. The second order terms are usually
distanced in frequency from the original sine waves, while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
REV. 0
–5–
AD7895
CONVERTER DETAILS
ance stage of the track/hold amplifier. For the AD7895-10,
R1 = 30 kΩ, R2 = 7.5 kΩ and R3 = 10 kΩ. For the AD7895-3,
R1 = R2 = 6.5 kΩ and R3 is open circuit.
The AD7895 is a fast, 12-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, A/D converter
and serial interface logic functions on a single chip. The A/D
converter section of the AD7895 consists of a conventional
successive-approximation converter based around an R-2R
ladder structure. The signal scaling on the AD7895-10 and
AD7895-3 allows the part to handle ±10 V and ±2.5 V input
signals, respectively, while operating from a single +5 V supply.
The AD7895-2 accepts an analog input range of 0 V to +2.5 V.
The part requires an external +2.5 V reference. The reference
input to the part is buffered on-chip. The AD7895 has two
operating modes, the high sampling mode and the auto sleep
mode, where the part automatically goes into sleep after the end of
conversion. These modes are discussed in more detail in the
“Timing and Control” section.
For the AD7895-10 and AD7895-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs,
3 LSBs . . .). Output coding is 2s complement binary with 1 LSB
= FS/4096. The ideal input/output transfer function for the
AD7895-10 and AD7895-3 is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7895-10/-3
Digital Output
Analog Inputl
Code Transition
+FSR/2 – 1 LSB2
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
A major advantage of the AD7895 is that it provides all of the
above functions in an 8-pin package, either 8-pin mini-DIP or
SOIC. This offers the user considerable spacing saving advantages
over alternative solutions. The AD7895 consumes only 20 mW
maximum, making it ideal for battery-powered applications.
GND + 1 LSB
GND
GND – 1 LSB
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
–FSR/2 + 3 LSBs
–FSR/2 + 2 LSBs
–FSR/2 + 1 LSB
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
Conversion is initiated on the AD7895 by pulsing the CONVST
input. On the falling edge of CONVST, the on-chip track/hold
goes from track to hold mode, and the conversion sequence is
started. The conversion clock for the part is generated internally
using a laser-trimmed clock oscillator circuit. Conversion time
for the AD7895 is 3.8 µs in the high sampling mode (9.8 µs for
the auto sleep mode), and the track/hold acquisition time is
0.3 µs. To obtain optimum performance from the part, the read
operation should not occur during the conversion or during
300 ns prior to the next conversion. This allows the part to
operate at throughput rates up to 192 kHz and achieve data sheet
specifications.
NOTES
1FSR is full-scale range = 20 V (AD7895-10) and = 5 V (AD7895-3)
with REF IN = +2.5 V.
21 LSB = FSR/4096 = 4.883 mV (AD7895-10) and 1.22 mV (AD7895-3)
with REF IN = +2.5 V.
The analog input section for the AD7895-2 contains no biasing
resistors, and the VIN pin drives the input to the track/hold
amplifier directly. The analog input range is 0 V to +2.5 V into
a high impedance stage with an input current of less than
500 nA. This input is benign with no dynamic charging cur-
rents. Once again, the designed code transitions occur on succes-
sive integer LSB values. Output coding is straight (natural) binary
with 1 LSB = FS/4096 = 2.5 V/4096 = 0.61 mV. Table II shows
the ideal input/output transfer function for the AD7895-2.
CIRCUIT DESCRIPTION
Analog Input Section
The AD7895 is offered as three part types: the AD7895-10,
which handles a ±10 V input voltage range; the AD7895-3,
which handles input voltage range ±2.5 V; and the AD7895-2,
which handles a 0 V to +2.5 V input voltage range.
Table II. Ideal Input/Output Code Table for AD7895-2
Digital Output
Analog Input1
Code Transition
REF IN
+FSR – 1 LSB2
+FSR – 2 LSB
+FSR – 3 LSB
111 . . . 110 to 111 . . . 111
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
TO ADC
REFERENCE
CIRCUITRY
R2
R1
TO INTERNAL
COMPARATOR
GND + 3 LSB
GND + 2 LSB
GND + 1 LSB
000 . . . 010 to 000 . . . 011
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
V
IN
TRACK/
HOLD
R3
AGND
NOTES
1FSR is full-scale range and is 2.5 V for AD7895-2 with VREF = +2.5 V.
21 LSB = FSR/4096 and is 0.61 mV for AD7895-2 with VREF = +2.5 V.
AD7895-10/AD7895-3
Track/Hold Section
Figure 2. AD7895-10/AD7895-3 Analog Input Structure
The track/hold amplifier on the analog input of the AD7895
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-bit accuracy. The input bandwidth of the
track/hold is greater than the Nyquist rate of the ADC even
when the ADC is operated at its maximum throughput rate of
192 kHz (i.e., the track/hold can handle input frequencies in
excess of 100 kHz).
Figure 2 shows the analog input section for the AD7895-10 and
AD7895-3. The analog input range of the AD7895-10 is ±10 V
into an input resistance of typically 33 kΩ. The analog input
range of the AD7895-3 is ±2.5 V into an input resistance of
typically 12 kΩ. This input is benign with no dynamic charging
currents, as the resistor stage is followed by a high input imped-
REV. 0
–6–
AD7895
The track/hold amplifier acquires an input signal to 12-bit
accuracy in less than 0.3 µs. The operation of the track/hold is
essentially transparent to the user. With the high sampling
operating mode, the track/hold amplifier goes from its tracking
mode to its hold mode at the start of conversion (i.e. the falling
edge of CONVST). The aperture time for the track/hold (i.e.
the delay time between the external CONVST signal and the
track/hold actually going into hold) is typically 15 ns. At the
end of conversion (on the falling edge of BUSY), the part returns
to its tracking mode. The acquisition time of the track/hold
amplifier begins at this point. For the auto shut down mode, the
rising edge of CONVST wakes up the part and the track, and
hold amplifier goes from its tracking mode to its hold mode 6 µs
after the rising edge of CONVST (provided that the CONVST
high time is less than 6 µs). Once again, the part returns to its
tracking mode at the end of conversion when the BUSY signal
goes low.
stated. If there are more serial clock pulses after the sixteenth
clock, the shift register will be moved on past its reset state.
However, the shift register will be reset again on the falling edge
of the CONVST signal to ensure that the part returns to a
known state every conversion cycle. As a result, a read opera-
tion from the output register should not straddle across the
falling edge of CONVST as the output shift register will be reset
in the middle of the read operation, and the data read back into
the microprocessor will appear invalid.
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The timing diagram in Figure 3 is for optimum performance in
operating Mode 1 where the falling edge of CONVST starts
conversion and puts the Track/Hold amplifier into its hold
mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 3.8 µs max after the falling edge of CONVST, and new
data from this conversion is available in the output register of
the AD7895. A read operation accesses this data. This read
operation consists of 16 clock cycles, and the length of this read
operation will depend on the serial clock frequency. For the
fastest throughput rate (with a serial clock of 15 MHz, 5 V
operation) the read operation will take 1.1 µs. The read opera-
tion must be complete at least 300 ns before the falling edge of
the next CONVST, and this gives a total time of 5.2 µs for the
full throughput time (equivalent to 192 kHz). This mode of
operation should be used for high sampling applications.
Reference Input
The reference input to the AD7895 is buffered on-chip with a
maximum reference input current of 1 µA. The part is specified
with a +2.5 V reference input voltage. Errors in the reference
source will result in gain errors in the AD7895’s transfer
function and will add to the specified full-scale errors on the
part. Suitable reference sources for the AD7895 include the
AD780 and AD680 precision +2.5 V references.
Timing and Control Section
Figure 3 shows the timing and control sequence required to
obtain optimum performance from the AD7895. In the se-
quence shown, conversion is initiated on the falling edge of
CONVST, and new data from this conversion is available in
the output register of the AD7895 3.8 µs later. Once the read
operation has taken place, a further 300 ns should be allowed
before the next falling edge of CONVST to optimize the settling
of the track/hold amplifier before the next conversion is initi-
ated. With the serial clock frequency at its maximum of
15 MHz, the achievable throughput rate for the part is 3.8 µs
(conversion time) plus 1.1 µs (read time) plus 0.3 µs (acquisi-
tion time). This results in a minimum throughput time of 8.2 µs
(equivalent to a throughput rate of 192 kHz). A serial clock of
less than 15 MHz can be used, but this will in turn mean that
the throughput time will increase.
Mode 2 Operation (Auto Sleep After Conversion)
The timing diagram in Figure 4 is for optimum performance in
operating mode 2 where the part automatically goes into sleep
mode once BUSY goes low after conversion and “wakes-up”
before the next conversion takes place. This is achieved by keep-
ing CONVST low at the end of conversion, whereas it was high
at the end of conversion for Mode 1 Operation. The rising edge
of CONVST “wakes up” the part. This wake-up time is 6 µs at
which point the Track/Hold amplifier goes into its hold mode,
provided the CONVST has gone low. The conversion takes
3.8 µs after this giving a total of 9.8 µs from the rising edge of
CONVST to the conversion being complete, which is indi-
cated by the BUSY going low. Note that since the wake-up time
from the rising edge of CONVST is 6 µs, when the CONVST
pulse width is greater than 6 µs, the conversion will take more
The read operation consists of sixteen serial clock pulses to the
output shift register of the AD7895. After sixteen serial clock
pulses, the shift register is reset, and the SDATA line is three-
t1
t1 = 40ns MIN
CONVST
BUSY
300ns MIN
SCLK
tCONVERT = 3.8µs
CONVERSION
ENDS
3.8µs LATER
READ OPERATION
SHOULD END 300ns
PRIOR TO NEXT
CONVERSION IS
INITIATED AND
TRACK/HOLD GOES INTO
SERIAL READ
OPERATION
OUTPUT
SERIAL
SHIFT
REGISTER
IS RESET
FALLING EDGE OF
HOLD
CONVST
Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance
–7–
REV. 0
AD7895
than the 9.8 µs shown in diagram from the rising edge of
CONVST. This is because the Track/Hold amplifier goes into
its hold mode on the falling edge of CONVST, and the conver-
sion will not be complete for a further 3.8 µs. In this case, the
BUSY will be the best indicator for when the conversion is
complete. Even though the part is in sleep mode, data can still
be read from the part. The read operation consists of 16 clock
cycles as in Mode 1 Operation. For the fastest serial clock of
15 MHz, the read operation will take 1.1 µs and this must be
complete at least 300 ns before the falling edge of the next
CONVST to allow the Track/Hold amplifier to have enough
time to settle. This mode is very useful when the part is convert-
ing at a slow rate as the power consumption will be significantly
reduced from that of Mode 1 Operation.
valid on the first falling edge of SCLK even though the data
access time is specified at 60 ns for the other bits. The reason
that the first bit will be clocked out faster than the other bits is
due to the internal architecture of the part. Sixteen clock pulses
must be provided to the part to access to full conversion result.
The AD7895 provides four leading zeros, followed by the 12-bit
conversion result starting with the MSB (DB11). The last data
bit to be clocked out on the penultimate falling clock edge is the
LSB (DB0). On the sixteenth falling edge of SCLK, the LSB
(DB0) will be valid for a specified time to allow the bit to be
read on the falling edge of the SCLK, then the SDATA line is
disabled (three-stated). After this last bit has been clocked
out, the SCLK input should return low and remain low until the
next serial data read operation. If there are extra clock pulses
after the sixteenth clock, the AD7895 will start over again with
outputting data from its output register, and the data bus will no
longer be three-stated even when the clock stops. Provided the
serial clock has stopped before the next falling edge of CONVST,
the AD7895 will continue to operate correctly with the output
shift register being reset on the falling edge of CONVST.
However, the SCLK line must be low when CONVST goes low in
order to reset the output shift register correctly.
Serial Interface
The serial interface to the AD7895 consists of just three wires: a
serial clock input (SCLK), the serial data output (SDATA) and
a conversion status output (BUSY). This allows for an easy-to-
use interface to most microcontrollers, DSP processors and shift
registers.
Figure 5 shows the timing diagram for the read operation to the
AD7895. The serial clock input (SCLK) provides the clock
source for the serial interface. Serial data is clocked out from the
SDATA line on the falling edge of this clock and is valid on
both the rising and falling edges of SCLK. The advantage of
having the data valid on both the rising and falling edges of the
SCLK is that it gives the user greater flexibility in interfacing to
the part and allows a wider range of microprocessor and micro-
controller interfaces to be accommodated. This also explains the
two timing figures, t4 and t5, that are quoted on the diagram.
The time t4 specifies how long after the falling edge of the
SCLK that the next data bit becomes valid, whereas the time t5
specifies how long after the falling edge of the SCLK that the
current data bit is valid for. The first leading zero is clocked out
on the first rising edge of SCLK. Note that the first zero will be
The serial clock input does not have to be continuous during the
serial read operation. The sixteen bits of data (four leading
zeros and 12 bit conversion result) can be read from the AD7895
in a number of bytes.
The AD7895 counts the serial clock edges to know which bit
from the output register should be placed on the SDATA
output. To ensure that the part does not lose synchronization,
the serial clock counter is reset on the falling edge of the
CONVST input, provided the SCLK line is low. The user
should ensure that the SCLK line remains low until the end of
the conversion. When the conversion is complete, BUSY goes
low, the output register will be loaded with the new conversion
result and can be read from with sixteen clock cycles of SCLK.
t1 = 6µs
WAKE-UP
TIME
t1
CONVST
BUSY
300ns MIN
SCLK
tCONVERT = 9.8µs
PART
WAKES
UP
CONVERSION
IS INITIATED
TRACK/HOLD
GOES INTO
HOLD
CONVERSION
ENDS
9.8µs LATER
SERIAL READ
OPERATION
READ OPERATION
SHOULD END 300ns
PRIOR TO NEXT
OUTPUT
SERIAL
SHIFT
REGISTER
IS RESET
FALLING EDGE OF
CONVST
Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated
t2 = t3 = 35ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 50ns MAX @ 5V, A, B, VERSIONS
t2
SCLK (I/P)
1
2
3
4
5
6
15
16
t3
t5
t6
t4
3-STATE
4 LEADING ZEROS
3-STATE
DOUT (O/P)
DB11
DB10
DB0
Figure 5. Data Read Operation
–8–
REV. 0
AD7895
MICROPROCESSOR/MICROCONTROLLER INTERFACE
The AD7895 provides a three-wire serial interface that can be
used for connection to the serial ports of DSP processors and
microcontrollers. Figures 6 through 9 show the AD7895
interfaced to a number of different microcontrollers and DSP
processors. The AD7895 accepts an external serial clock, and
as a result, in all interfaces shown here, the processor/controller
is configured as the master, providing the serial clock with the
AD7895 configured as the slave in the system.
AD7895–68HC11/L11 Interface
An interface circuit between the AD7895 and the 68HC11/L11
microcontroller is shown in Figure 7. For the interface shown,
the 68L11 SPI port is used, and the 68L11 is configured in its
single-chip mode. The 68L11 is configured in the master mode
with its CPOL bit set to a logic zero and its CPHA bit set to a
logic one. As with the previous interface, the diagram shows the
simplest form of the interface where the AD7895 is the only part
connected to the serial port of the 68L11 and, therefore, no
decoding of the serial read operations is required.
AD7895–8051 Interface
Figure 6 shows an interface between the AD7895 and the 8XL51
microcontroller. The 8XL51 is configured for its Mode 0 serial
interface mode. The diagram shows the simplest form of the
interface where the AD7895 is the only part connected to the
serial port of the 8XL51 and, therefore, no decoding of the
serial read operations is required.
PC2 OR
BUSY
IRQ
AD7895
68HC11/L11
SCK
SCLK
SDATA
MISO
P1.2
OR
INT1
BUSY
AD7895
Figure 7. AD7895 to 68HC11/L11 Interface
8X51/L51
P3.0
SDATA
Once again, to chip select the AD7895 in systems where more
than one device is connected to the 68HC11’s serial port, a port
bit configured as an output from one of the 68HC11’s parallel
ports can be used to gate on or off the serial clock to the
AD7895. A simple AND function on this port bit and the serial
clock from the 68L11 will provide this function. The port bit
should be high to select the AD7895 and low when it is not
selected.
SCLK
P3.1
Figure 6. AD7895 to 8X51/L51 Interface
To chip select the AD7895 in systems where more than one
device is connected to the 8XL51’s serial port, a port bit
configured as an output, from one of the 8XL51’s parallel ports
can be used to gate on or off the serial clock to the AD7895. A
simple AND function on this port bit and the serial clock from
the 8XL51 will provide this function. The port bit should be
high to select the AD7895 and low when it is not selected.
The end of conversion is monitored by using the BUSY signal
that is shown in the interface diagram of Figure 7. With the
BUSY line from the AD7895 connected to the Port PC0 of the
68HC11/L11, the BUSY line can be polled by the 68HC11/L11.
The BUSY line can be connected to the IRQ line of the
68HC11/L11 if an interrupt driven system is preferred. These
two options are shown in the diagram.
The end of conversion is monitored by using the BUSY signal
that is shown in the interface diagram of Figure 6. The BUSY
line from the AD7895 is connected to the Port P1.2 of the
8XL51 so the BUSY line can be polled by the 8XL51. The BUSY
line can be connected to the INT1 line of the 8XL51 if an
interrupt driven system is preferred. These two options are
shown in the diagram.
The serial clock rate from the 68HC11/L11 is limited to
significantly less than the allowable input serial clock frequency
with which the AD7895 can operate. As a result, the time to
read data from the part will actually be longer than the conver-
sion time of the part. This means that the AD7895 cannot run
at its maximum throughput rate when used with the 68HC11/L11.
Note also that the AD7895 outputs the MSB first during a read
operation, while the 8XL51 expects the LSB first. Therefore,
the data which is read into the serial buffer needs to be rear-
ranged before the correct data format from the AD7895 appears
in the accumulator.
AD7895–ADSP-2103/5 Interface
An interface circuit between the AD7895 and the ADSP-2103/5
DSP processor is shown in Figure 8. In the interface shown, the
RFS1 output from the ADSP-2103/5s SPORT1 serial port is
used to gate the serial clock (SCLK1) of the ADSP-2103/5
before it is applied to the SCLK input of the AD7895. The
RFS1 output is configured for active high operation. The BUSY
line from the AD7895 is connected to the IRQ2 line of the
ADSP-2103/5 so that at the end of conversion an interrupt is
generated telling the ADSP-2103/5 to initiate a read operation.
The interface ensures a noncontinuous clock for the AD7895’s
serial clock input with only sixteen serial clock pulses provided
and the serial clock line of the AD7895 remaining low between
data transfers. The SDATA line from the AD7895 is connected
to the DR1 line of the ADSP-2103/5’s serial port.
The serial clock rate from the 8XL51 is limited to significantly
less than the allowable input serial clock frequency with which
the AD7895 can operate. As a result, the time to read data
from the part will actually be longer than the conversion time of
the part. This means that the AD7895 cannot run at its maximum
throughput rate when used with the 8XL51.
REV. 0
–9–
AD7895
Because the BUSY line from the AD7895 is connected to the
MODA/IRQA input of the DSP56002/L002, an interrupt will
be generated at the end of conversion. This ensures that the
read operation will take place after conversion is finished.
BUSY
IRQ2
RFS1
AD7895
ADSP-2103/5
SCLK
SCLK1
DR1
AD7895 PERFORMANCE
Linearity
SDATA
The linearity of the AD7895 is determined by the on-chip
12-bit D/A converter. This is a segmented DAC that is laser
trimmed for 12-bit integral linearity and differential linearity.
Typical relative accuracy numbers for the part are ±1/4 LSB
while the typical DNL errors are ±1/2 LSB.
Figure 8. AD7896 to ADSP-2103 /5 Interface
The timing relationship between the SCLK1 and RFS1 outputs
of the ADSP-2103/5 are such that the delay between the rising
edge of the SCLK1 and the rising edge of an active high RFS1
is up to 30 ns. There is also a requirement that data must be
set up 10 ns prior to the falling edge of the SCLK1 to be read
correctly by the ADSP-2103/5. The data access time for the
AD7895 is 60 ns (5 V (A, B versions)) from the rising edge of
its SCLK input. Assuming a 10 ns propagation delay through
the external AND gate, the high time of the SCLK1 output of
the ADSP-2105 must be ≥ (30 + 60 +10 +10) ns, i.e., ≥ 110 ns.
This means that the serial clock frequency with which the
interface of Figure 8 can work is limited to 4.5 MHz. However,
there is an alternative method that allows for the ADSP-2105
SCLK1 to run at 5 MHz (the max serial clock frequency of the
SCLK1 output). The arrangement occurs when the first leading
zero of the data stream from the AD7895 cannot be guaranteed
to be clocked into the ADSP-2105 due to the combined delay of
the RFS signal and the data access time of the AD7895. In most
cases, this is acceptable because there will still be three leading
zeros followed by the 12 data bits. For the ADSP-2103, the
SCLK1 frequency will need to be limited to < 4 MHz to
account for the 100 ns data access time of the AD7895.
Another alternative scheme is to configure the ADSP-2103/5 so
that it accepts an external noncontinuous serial clock. In this
case, an external noncontinuous serial clock is provided that
drives the serial clock inputs of both the ADSP-2103/5 and the
AD7895. In this scheme, the serial clock frequency is limited to
15 MHz by the AD7895.
Noise
In an A/D converter, noise exhibits itself as code uncertainty in
dc applications and as the noise floor (in an FFT, for example)
in ac applications. In a sampling A/D converter like the AD7895,
all information about the analog input appears in the baseband
from dc to 1/2 the sampling frequency. The input bandwidth of
the track/hold exceeds the Nyquist bandwidth and, therefore, an
antialiasing filter should be used to remove unwanted signals above
fS/2 in the input signal in applications where such signals exist.
Figure 10 shows a histogram plot for 8192 conversions of a dc
input using the AD7895. The analog input was set at the center
of a code transition. It can be seen that almost all the codes
appear in the one output bin, indicating very good noise
performance from the ADC.
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
AD7895–DSP56002/L002 Interface
Figure 9 shows an interface circuit between the AD7895 and the
DSP56002/L002 DSP processor. The DSP56002/L002 is
configured for normal mode asynchronous operation with gated
clock. It is also set up for a 16-bit word with SCK as gated
clock output. In this mode, the DSP56002/L002 provides
sixteen serial clock pulses to the AD7895 in a serial read
operation. Because the DSP56002/L002 assumes valid data on
the first falling edge of SCK, the interface is simply two-wire as
shown in Figure 9.
957
958
959
960
961
962
Figure 10. Histogram of 8192 Conversions of a DC Input
In this case where the output data read for the device occurs
during conversion, this has the effect of injecting noise onto the
die while bit decisions are being made, and this increases the
noise generated by the AD7895. A histogram plot for 8192
conversions of the same dc input would show a larger spread of
codes with the rms noise for the AD7895 increasing. This effect
will vary depending on where the serial clock edges appear with
respect to the bit trials of the conversion process. It is possible
to achieve the same level of performance when reading during
conversion as when reading after conversion, depending on the
relationship of the serial clock edges to the bit trial points.
BUSY
SCLK
MODA / IRQA
DSP56002/L002
SCK
AD7895
SDATA
SDR
Figure 9. AD7895 to DSP56002/L002 Interface
REV. 0
–10–
AD7895
12.0
11.8
Dynamic Performance (Mode 1 Only)
With a combined conversion and acquisition time of 4.1 µs, the
AD7895 is ideal for wide bandwidth signal processing applica-
tions. These applications require information on the ADC’s
effect on the spectral content of the input signal. Signal to
(Noise + Distortion), Total Harmonic Distortion, Peak Har-
monic or Spurious Noise, and Intermodulation Distortion are
all specified. Figure 11 shows a typical FFT plot of a 10 kHz,
0 V to +5 V input after being digitized by the AD7895 operating
at a 198.656 kHz sampling rate. The Signal to (Noise + Distor-
tion) Ratio is 73.04 dB, and the Total Harmonic Distortion is
–84.91 dB.
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
The formula for Signal to (Noise + Distortion) Ratio (see
Terminology section) is related to the resolution or number of
bits in the converter. Rewriting the formula, below, gives a
measure of performance expressed in effective number of bits (N):
0
200
400
600
800
1000
FREQUENCY – kHz
Figure 12. Effective Number of Bits vs. Frequency
N = (SNR 1.76)/6.02
Power Considerations
In the automatic power-down mode, then, the part may be
operated at a sample rate that is considerably less than
100 kHz. In this case, the power consumption will be reduced
and will depend on the sample rate. Figure 13 shows a graph
of the power consumption versus sampling rates from 100 Hz to
90 kHz in the automatic power-down mode. The conditions
are 5 V supply 25°C, serial clock frequency of 8.33 MHz, and
the data was read after conversion.
where SNR is Signal to (Noise + Distortion) Ratio.
–0
F
F
= 198656
SAMPLE
= 10kHz
–10
–20
IN
SNR = –73.04dB
THD = –84.91dB
–30
–40
–50
–60
11
10
9
–70
–80
–90
8
–100
–110
–120
7
6
0
10k
30k
50k
70k
90k 9.9k
5
4
Figure 11. AD7896 FFT Plot Effective Number of Bits
3
2
The effective number of bits for a device can be calculated from
its measured Signal to (Noise + Distortion) Ratio. Figure 12
shows a typical plot of effective number of bits versus frequency
for the AD7895 from dc to fSAMPLING/2. The sampling frequency
is 198.656 kHz. The plot shows that the AD7895 converts an
input sine wave of 10 kHz to an effective numbers of bits of
11.84, which equates to a Signal to (Noise + Distortion) level of
73.04 dB.
1
0
0.1
10
20
30
40
50
60
70
80
90
FREQUENCY – kHz
Figure 13. Power vs. Sample Rate in Auto Power-Down
Mode
REV. 0
–11–
AD7895
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
8
5
4
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.008 (0.204)
SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
0.102 (2.59)
0.094 (2.39)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500 0.0192 (0.49)
0.0500 (1.27)
0.0160 (0.41)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
(1.27)
0.0138 (0.35)
BSC
–12–
REV. 0
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