AD820ARMZ-RL [ROCHESTER]
OP-AMP, 1500 uV OFFSET-MAX, 1.9 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8;
| 型号： | AD820ARMZ-RL |
| 厂家： | 
Rochester Electronics |
| 描述： | OP-AMP, 1500 uV OFFSET-MAX, 1.9 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8 光电二极管 |
| 文件： | 总25页 (文件大小：1541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply, Rail-to-Rail,
Low Power, FET Input Op Amp
AD820
FEATURES
PIN CONFIGURATIONS
True single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 5 V to 30 V
Dual-supply capability from 2.5 V to 15 V
Excellent load drive
NULL
–IN
1
2
3
4
8
7
6
5
NC
AD820
+V
S
+IN
V
OUT
TOP VIEW
(Not to Scale)
–V
NULL
S
NC = NO CONNECT
Capacitive load drive up to 350 pF
Minimum output current of 15 mA
Excellent ac performance for low power
800 μA maximum quiescent current
Unity-gain bandwidth: 1.8 MHz
Slew rate of 3 V/μs
Figure 1. 8-Lead PDIP
NC
–IN
+IN
1
2
3
4
8
7
6
5
NC
AD820
+V
S
V
OUT
TOP VIEW
–V
NC
S
Excellent dc performance
(Not to Scale)
800 μV maximum input offset voltage
2 μV/°C typical offset voltage drift
25 pA maximum input bias current
Low noise: 13 nV/√Hz @ 10 kHz
NC = NO CONNECT
Figure 2. 8-Lead SOIC_N and 8-Lead MSOP
APPLICATIONS
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 14-bit data acquisition systems
Medical instrumentation
Low power references and regulators
GENERAL DESCRIPTION
The AD820 is a precision, low power FET input op amp that
can operate from a single supply of 5 V to 36 V, or dual supplies
of 2.5 V to 18 V. It has true single-supply capability, with an
input voltage range extending below the negative rail, allowing
the AD820 to accommodate input signals below ground in the
single-supply mode. Output voltage swing extends to within
10 mV of each rail, providing the maximum output dynamic range.
The AD820 is available in two performance grades. The A and
B grades are rated over the industrial temperature range of
−40°C to +85°C. The AD820 is offered in three 8-lead package
options: plastic DIP (PDIP), surface mount (SOIC) and (MSOP).
20µs
1V
1V
100
90
Offset voltage of 800 μV maximum, offset voltage drift of
2 μV/°C, typical input bias currents below 25 pA, and low input
voltage noise provide dc precision with source impedances up
to 1 GΩ. 1.8 MHz unity gain bandwidth, −93 dB THD at
10 kHz, and 3 V/μs slew rate are provided for a low supply
current of 800 μA. The AD820 drives up to 350 pF of direct
capacitive load and provides a minimum output current of
15 mA. This allows the amplifier to handle a wide range of load
conditions. This combination of ac and dc performance, plus
the outstanding load drive capability, results in an exceptionally
versatile amplifier for the single-supply user.
10
0%
1V
Figure 3. Gain-of-2 Amplifier; VS = 5 V, 0 V, VIN = 2.5 V Sine Centered at 1.25 V
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved.
AD820
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 16
Input Characteristics.................................................................. 16
Output Characteristics............................................................... 17
Single-Supply Half-Wave and Full-Wave Rectifiers .............. 17
4.5 V Low Dropout, Low Power Reference............................. 18
Low Power, 3-Pole, Sallen Key Low-Pass Filter...................... 18
Offset Voltage Adjustment ............................................................ 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 21
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Typical Performance Characteristics ........................................... 10
REVISION HISTORY
3/11—Rev. G to Rev. H
Changes to Figure 43...................................................................... 18
Added Table 5; Renumbered Sequentially .....................................9
Changes to Figure 26...................................................................... 13
Changes to Figure 27...................................................................... 14
Changed Application Notes Section to Applications
2/10—Rev. F to Rev. G
Changes to Features Section............................................................ 1
Changes to Open-Loop Gain Parameter....................................... 3
Changes to Input Voltage Parameter ............................................. 9
Updated Outline Dimensions....................................................... 20
Information Section ....................................................................... 16
Changes to Figure 40, Figure 41, and Figure 42......................... 17
Changes to Figure 44...................................................................... 18
Moved Offset Voltage Adjustment Section................................. 19
Updated Outline Dimensions....................................................... 20
Added Figure 49; Renumbered Sequentially .............................. 21
Changes to Ordering Guide.......................................................... 21
11/08—Rev. E to Rev. F
Added 8-Lead MSOP .........................................................Universal
Changes to Features Section, Figure 2 Caption, and General
Description Section.......................................................................... 1
Changes to Settling Time Parameter, Common-Mode Voltage
Range Parameter, and Power Supply Rejection Parameter in
Table 1 ................................................................................................ 3
Changes to Settling Time Parameter, Common-Mode Voltage
Range Parameter, and Power Supply Rejection Parameter in
Table 2 ................................................................................................ 5
Changes to Settling Time Parameter, Common-Mode Voltage
Range Parameter, and Power Supply Rejection Parameter in
Table 3 ................................................................................................ 7
Changes to Table 4............................................................................ 9
Added Thermal Resistance Section ............................................... 9
2/07—Rev. D to Rev. E
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 21
Changes to the Ordering Guide ................................................... 22
5/02—Rev. C to Rev. D
Change to SOIC Package (R-8) Drawing .................................... 15
Edits to Features.................................................................................1
Edits to Product Description ...........................................................1
Delete Specifications for AD820A-3 V...........................................5
Edits to Ordering Guide ...................................................................6
Edits to Typical Performance Characteristics................................8
Rev. H | Page 2 of 24
AD820
SPECIFICATIONS
VS = 0 V, 5 V @ TA = 25°C, VCM = 0 V, V OUT = 0.2 V, unless otherwise noted.
Table 1.
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Initial Offset
Maximum Offset over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
0.1
0.5
2
2
0.5
2
0.8
1.2
0.1
0.5
2
2
0.5
2
0.4
0.9
mV
mV
μV/°C
pA
nA
pA
VCM = 0 V to 4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
VOUT = 0.2 V to 4 V
RL = 100 kΩ
400
400
80
80
15
1000
150
30
500
400
80
80
15
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
10
10
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ to 2.5 V
VOUT = 0.25 V to 4.75 V
−93
−93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.8
210
3
1.8
210
3
MHz
kHz
V/μs
VOUT p-p = 4.5 V
Settling Time
VOUT = 0.2 V to 4.5 V
To 0.1%
To 0.01%
1.4
1.8
1.4
1.8
μs
μs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
CMRR
TMIN to TMAX
−0.2
66
66
+4
–0.2
72
66
+4
V
dB
dB
VCM = 0 V to 2 V
80
80
Input Impedance
Differential
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Common Mode
Rev. H | Page 3 of 24
AD820
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
ISINK = 20 μA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
ISOURCE = 20 μA
ISINK = 2 mA
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
15
12
15
12
25
25
350
350
TMIN to TMAX
V+ = 5 V to 15 V
620
80
800
620
80
800
μA
dB
dB
70
70
66
66
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. H | Page 4 of 24
AD820
VS = 5 V @ TA = 25°C, VCM = 0 V, V OUT = 0 V, unless otherwise noted.
Table 2.
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Initial Offset
Maximum Offset over Temperature
Offset Drift
Input Bias Current
At TMAX
Input Offset Current
At TMAX
0.1
0.5
2
2
0.5
2
0.8
1.5
0.3
0.5
2
2
0.5
2
0.4
1
mV
mV
μV/°C
pA
nA
pA
VCM = −5 V to +4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
VOUT = −4 V to +4 V
RL = 100 kΩ
400
400
80
80
20
1000
150
30
400
400
80
80
20
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
10
10
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ
VOUT = 4.5 V
−93
−93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.9
105
3
1.8
105
3
MHz
kHz
V/μs
VOUT p-p = 9 V
Settling Time
VOUT = 0 V to 4.5 V
To 0.1%
To 0.01%
1.4
1.8
1.4
1.8
μs
μs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
CMRR
TMIN to TMAX
−5.2
66
66
+4
−5.2
72
66
+4
V
dB
dB
VCM = −5 V to +2 V
80
80
Input Impedance
Differential
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Common Mode
Rev. H | Page 5 of 24
AD820
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
ISINK = 20 μA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
ISOURCE = 20 μA
ISINK = 2 mA
10
40
80
300
800
10
40
80
300
800
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
TMIN to TMAX
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
15
12
15
12
30
30
350
350
TMIN to TMAX
V+ = 5 V to 15 V
650
80
800
620
80
800
μA
dB
dB
70
70
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. H | Page 6 of 24
AD820
VS = 15 V @ TA = 25°C, VCM = 0 V, V OUT = 0 V, unless otherwise noted.
Table 3.
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
DC PERFORMANCE
Initial Offset
Maximum Offset over Temperature
Offset Drift
0.4
0.5
2
2
3
0.3
0.5
2
1.0
2
mV
mV
μV/°C
pA
pA
nA
Input Bias Current
VCM = 0 V
VCM = −10 V
VCM = 0 V
2
25
2
10
40
0.5
2
40
0.5
2
At TMAX
Input Offset Current
At TMAX
5
20
2.5
10
pA
nA
0.5
0.5
Open-Loop Gain
VOUT = −10 V to +10 V
RL = 100 kΩ
500
500
100
100
30
2000
500
45
500
500
100
100
30
2000
500
45
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
TMIN to TMAX
TMIN to TMAX
RL = 10 kΩ
RL = 1 kΩ
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
f = 10 Hz
20
20
2
2
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
25
21
16
13
25
21
16
13
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
Harmonic Distortion
f = 10 kHz
RL = 10 kΩ
VOUT = 10 V
−85
−85
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.9
45
3
1.9
45
3
MHz
kHz
V/μs
VOUT p-p = 20 V
Settling Time
VOUT = 0 V to 10 V
To 0.1%
To 0.01%
4.1
4.5
4.1
4.5
μs
μs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
CMRR
TMIN to TMAX
−15.2
70
70
+14
−15.2
74
74
+14
V
dB
dB
VCM = –15 V to +12 V
80
90
Input Impedance
Differential
Common Mode
1013||0.5
1013||2.8
1013||0.5
1013||2.8
Ω||pF
Ω||pF
Rev. H | Page 7 of 24
AD820
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE
ISINK = 20 μA
5
7
10
5
7
10
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
pF
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
VCC − VOH
TMIN to TMAX
VOL − VEE
TMIN to TMAX
ISOURCE = 20 μA
ISINK = 2 mA
10
40
80
300
800
14
20
55
80
110
160
500
1000
1500
1900
10
40
80
300
800
14
20
55
80
110
160
500
1000
1500
1900
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
VCC − VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
20
15
20
15
45
45
350
350
TMIN to TMAX
V+ = 5 V to 15 V
700
80
900
700
80
900
μA
dB
dB
70
70
70
70
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Rev. H | Page 8 of 24
AD820
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage
18 V
Internal Power Dissipation
8-Lead PDIP (N)
8-Lead SOIC_N (R)
8-Lead MSOP (RM)
Input Voltage1
Table 5. Thermal Resistance
Package Type
1.6 W
1.0 W
0.8 W
((V+) + 0.2 V) to
(V−) − 20 V
θJA
90
160
190
Unit
°C/W
°C/W
°C/W
8-Lead PDIP (N)
8-Lead SOIC_N (R)
8-Lead MSOP (RM)
Output Short-Circuit Duration
Differential Input Voltage
Storage Temperature Range
8-Lead PDIP (N)
8-Lead SOIC_N (R)
8-Lead MSOP (RM)
Operating Temperature Range
AD820A/AD820B
Lead Temperature(Soldering, 60 sec)
Indefinite
30 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−65°C to +125°C
−65°C to +150°C
−65°C to +150°C
−40°C to +85°C
260°C
1 See Input Characteristics section.
ESD CAUTION
Rev. H | Page 9 of 24
AD820
TYPICAL PERFORMANCE CHARACTERISTICS
50
5
V
= 0V, 5V
S
40
30
20
10
0
0
V
= 0V, +5V AND ±5V
S
V
= ±5V
S
–5
–5
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–4
–3
–2
–1
0
1
2
3
4
5
OFFSET VOLTAGE (mV)
COMMON-MODE VOLTAGE (V)
Figure 4. Typical Distribution of Offset Voltage (248 Units)
Figure 7. Input Bias Current vs. Common-Mode Voltage;
VS = +5 V, 0 V and VS = 5 V
48
1k
V
V
= ±5V
S
= ±15V
40
32
24
16
8
S
100
10
1
0
–10
0.1
–16
–8
–6
–4
–2
0
2
4
6
8
10
–12
–8
–4
0
4
8
12
16
OFFSET VOLTAGE DRIFT (µV/ºC)
COMMON-MODE VOLTAGE (V)
Figure 5. Typical Distribution of Offset Voltage Drift (120 Units)
Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = 15 V
100k
10k
1k
50
45
40
35
30
25
20
15
10
5
100
10
1
0.1
20
40
60
80
100
120
140
0
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (ºC)
INPUT BIAS CURRENT (pA)
Figure 6. Typical Distribution of Input Bias Current (213 Units)
Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V
Rev. H | Page 10 of 24
AD820
10M
1M
40
20
POSITIVE
RAIL
R
= 2kΩ
L
R
= 20kΩ
L
V
= ±15V
S
NEGATIVE
RAIL
POSITIVE
RAIL
0
V
= 0V, +5V
S
100k
10k
POSITIVE
RAIL
NEGATIVE
RAIL
–20
–40
R
= 100kΩ
L
NEGATIVE RAIL
100
1k
10k
100k
0
60
120
180
240
300
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE FROM RAILS (mV)
Figure 10. Open-Loop Gain vs. Load Resistance
Figure 13. Input Error Voltage vs. Output Voltage Within 300 mV of Either
Supply Rail for Various Resistive Loads; VS = 5 V
10M
1M
1k
100
10
V
= ±15V
S
R
R
= 100kΩ
= 10kΩ
L
L
V
= 0V, +5V
= ±15V
S
V
S
V
= 0V, +5V
= ±15V
S
100k
10k
V
S
R
= 600Ω
L
V
= 0V, +5V
S
1
–60 –40 –20
0
20
40
60
80
100 120 140
1
10
100
1k
10k
TEMPERATURE (ºC)
FREQUENCY (Hz)
Figure 11. Open-Loop Gain vs. Temperature
Figure 14. Input Voltage Noise vs. Frequency
300
200
100
0
–40
–50
R
A
= 10kΩ
L
= –1
CL
–60
R
= 10kΩ
L
R
= 100kΩ
L
–70
–80
V
= ±15V; V = 20V p-p
OUT
S
–100
–200
–300
–90
V
V
= ±5V; V = 9V p-p
OUT
S
R
= 600Ω
L
= 0V, +5V; V
OUT
= 4.5V p-p
–100
–110
S
–16
–12
–8
–4
0
4
8
12
16
100
1k
10k
FREQUENCY (Hz)
100k
OUTPUT VOLTAGE (V)
Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads
Figure 15. Total Harmonic Distortion vs. Frequency
Rev. H | Page 11 of 24
AD820
100
80
60
40
20
0
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
PHASE
GAIN
V
= 0V, +5V
V = ±15V
S
S
R
C
= 2kΩ
= 100pF
L
L
–20
10
–20
10M
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Open-Loop Gain and Phase Margin vs. Frequency
Figure 19. Common-Mode Rejection vs. Frequency
1k
5
4
3
2
1
0
A
= +1
CL
= ±15V
V
S
100
10
NEGATIVE
RAIL
POSITIVE
RAIL
1
+25ºC
+125ºC
+125ºC
0.1
0.01
–55ºC
–55ºC
100
1k
10k
100k
1M
10M
–1
0
1
2
3
FREQUENCY (Hz)
COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V)
Figure 17. Output Impedance vs. Frequency
Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage
from Supply Rails (VS − VCM
)
16
12
8
1k
100
10
1%
4
V
– V
OH
S
0.1%
0.01%
ERROR
0
V
– V
S
–4
–8
–12
–16
OL
1%
1
0
1
2
3
4
5
0.001
0.01
0.1
1
10
100
SETTLING TIME (µs)
LOAD CURRENT (mA)
Figure 18. Output Swing and Error vs. Settling Time
Figure 21. Output Saturation Voltage vs. Load Current
Rev. H | Page 12 of 24
AD820
1k
100
10
120
110
100
90
80
70
60
50
40
30
20
10
0
I
I
= 10mA
SOURCE
= 10mA
SINK
I
= 1mA
SOURCE
+PSRR
I
= 1mA
SINK
–PSRR
I
I
= 10µA
SOURCE
= 10µA
SINK
1
–60 –40 –20
0
20
40
60
80
100 120 140
10
100
1k
10k
100k
1M
10M
TEMPERATURE (ºC)
FREQUENCY (Hz)
Figure 22. Output Saturation Voltage vs. Temperature
Figure 25. Power Supply Rejection vs. Frequency
80
30
25
20
15
10
5
R
= 2kΩ
L
70
60
50
40
30
20
10
0
V
V
= ±15V
S
S
V
= ±15V
S
–OUT
= ±15V
V
= 0V, +5V
S
+
–
V
= 0V, +5V
S
+
V
= 0V, +5V
S
0
10k
–60 –40 –20
0
20
40
60
80
100 120 140
100k
FREQUENCY (Hz)
1M
10M
TEMPERATURE (ºC)
Figure 23. Short-Circuit Current Limit vs. Temperature
Figure 26. Large Signal Frequency Response
800
700
600
500
400
300
200
100
0
T = +125ºC
T = +25ºC
T = –55ºC
0
4
8
12
16
20
24
28
32
36
TOTAL SUPPLY VOLTAGE (V)
Figure 24. Quiescent Current vs. Supply Voltage over Different Temperatures
Rev. H | Page 13 of 24
AD820
5V
5µs
+V
7
100
90
S
0.01µF
3
2
+
+
V
6
IN
–
+
AD820
–
4
V
OUT
100pF
0.01µF
R
L
–
10
–V
S
0%
Figure 27. Unity-Gain Follower, Used for Figure 28 Through Figure 32
Figure 30. Large Signal Response Unity-Gain Follower; VS = 15 V, RL = 10 kΩ
5V
10µs
10mV
500ns
100
90
100
90
10
10
0%
0%
Figure 28. 20 V, 25 kHz Sine Input; Unity-Gain Follower; RL = 600 Ω, V = 15 V
Figure 31. Small Signal Response Unity-Gain Follower; VS = 15 V, RL = 10 kΩ
S
1V
2µs
1V
2µs
100
90
100
90
10
10
0%
0%
GND
GND
Figure 29. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step
Figure 32. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step
Rev. H | Page 14 of 24
AD820
10kΩ
20kΩ
+
+V
7
S
V
IN
V
OUT
+V
7
S
–
0.01µF
6
3
2
0.01µF
+
V
IN
2
3
+
AD820
–
V
6
–
OUT
100pF
R
L
AD820
–
4
100pF
R
+
4
L
Figure 33. Unity-Gain Follower, Used for Figure 34
Figure 35. Gain-of-2 Inverter, Used for Figure 36 and Figure 37
10mV
2µs
1V
2µS
100
90
100
90
10
10
0%
0%
GND
GND
Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step
Centered 40 mV Above Ground
Figure 36. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step,
Centered −1.25 V Below Ground
10mV
2µs
100
90
10
0%
GND
Figure 37. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step, Centered
20 mV Below Ground
Rev. H | Page 15 of 24
AD820
APPLICATIONS INFORMATION
INPUT CHARACTERISTICS
1V
2µs
In the AD820, N-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input common-
mode voltage extends from 0.2 V below –VS to 1 V less than
+VS. Driving the input voltage closer to the positive rail causes a
loss of amplifier bandwidth (as can be seen by comparing the
large signal responses shown in Figure 29 and Figure 32) and
increased common-mode voltage error, as illustrated in
Figure 20.
100
90
10
0%
The AD820 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 38a shows the response of an
AD820 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output polarity
tracks the input polarity up to +VS with no phase reversal. The
reduced bandwidth above a 4 V input causes the rounding of
the output waveform. For input voltages greater than +VS, a
resistor in series with the AD820 positive input prevents phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 38b.
GND
1V
(a)
1V
1V
10µs
100
90
+V
S
Because the input stage uses N-channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS − 0.4 V, the input current reverses direction as internal
device junctions become forward biased. This is illustrated in
Figure 7.
10
0%
GND
1V
A current-limiting resistor should be used in series with the
input of the AD820 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage is applied to the AD820 when VS = 0 V. The
amplifier can be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
(b)
+
5V
R
P
+
V
IN
–
+
AD820
–
V
OUT
–
Input voltages less than −V are a completely different story.
S
Figure 38. (a) Response with RP = 0 Ω; VIN from 0 V to +VS
(b) VIN = 0 V to +VS + 200 mV,
The amplifier can safely withstand input voltages 20 V below
the negative supply voltage as long as the total voltage from
the positive supply to the input terminal is less than 36 V. In
addition, the input stage typically maintains picoamp level
input currents across that input voltage range.
VOUT = 0 V to +VS, RP = 49.9 kΩ
100k
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
10k
1k
1kHz
The AD820 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 14). This noise performance, along with the
AD820 low input current and current noise, means that the
AD820 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 39.
RESISTOR JOHNSON
NOISE
100
10
10Hz
1
AMPLIFIER-GENERATED
NOISE
0.1
10k
100k
1M
10M
100M
1G
10G
SOURCE IMPEDANCE (Ω)
Figure 39. Total Noise vs. Source Impedance
Rev. H | Page 16 of 24
AD820
5
4
3
2
1
OUTPUT CHARACTERISTICS
The AD820 unique bipolar rail-to-rail output stage swings
within 5 mV of the negative supply and 10 mV of the positive
supply with no external resistive load. The approximate output
saturation resistance of the AD820 is 40 Ω sourcing and 20 Ω
sinking. This can be used to estimate output saturation voltage
when driving heavier current loads. For instance, when sourcing
5 mA, the saturation voltage to the positive supply rail is 200 mV;
when sinking 5 mA, the saturation voltage to the negative rail
is 100 mV.
The open-loop gain characteristic of the amplifier changes
as a function of resistive load, as shown in Figure 10 through
Figure 13. For load resistances over 20 kΩ, the AD820 input
error voltage is virtually unchanged until the output voltage is
driven to 180 mV of either supply.
300
1k
3k
10k
30k
CAPACITIVE LOAD FOR 20º PHASE MARGIN (pF)
+
If the AD820 output is driven hard against the output saturation
voltage, it recovers within 2 μs of the input returning to the
linear operating region of the amplifier.
–
R
F
Direct capacitive load interacts with the effective output imped-
ance of the amplifier to form an additional pole in the amplifier
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. The worst case occurs when the
amplifier is used as a unity-gain follower. Figure 40 shows
AD820 pulse response as a unity-gain follower driving 350 pF.
This amount of overshoot indicates approximately 20 degrees
of phase margin—the system is stable, but is nearing the edge.
Configurations with less loop gain, and as a result less loop
bandwidth, are much less sensitive to capacitance load effects.
Figure 41 is a plot of noise gain vs. the capacitive load that results
in a 20 degree phase margin for the AD820. Noise gain is the
inverse of the feedback attenuation factor provided by the
feedback network in use.
R1
Figure 41. Noise Gain vs. Capacitive Load Tolerance
Figure 42 shows a possible configuration for extending
capacitance load drive capability for a unity-gain follower. With
these component values, the circuit drives 5000 pF with a 10%
overshoot.
+V
S
0.01µF
7
3
2
+
+
100Ω
V
6
IN
–
+
AD820
–
4
V
OUT
0.01µF
–
–V
S
20pF
20mV
2µs
20kΩ
100
90
Figure 42. Extending Unity-Gain Follower Capacitive Load Capability
Beyond 350 pF
SINGLE-SUPPLY HALF-WAVE AND FULL-WAVE
RECTIFIERS
An AD820 configured as a unity-gain follower and operated
with a single supply can be used as a simple half-wave rectifier.
The AD820 inputs maintain picoamp level input currents even
when driven well below the negative supply. The rectifier puts
that behavior to good use, maintaining an input impedance of
over 1011 Ω for input voltages from 1 V from the positive supply
to 20 V below the negative supply.
10
0%
Figure 40. Small Signal Response of AD820 as Unity-Gain Follower Driving
350 pF Capacitive Load
The full- and half-wave rectifier shown in Figure 43 operates as
follows: when VIN is above ground, R1 is bootstrapped through
the unity-gain follower, A1, and the loop of Amplifier A2. This
forces the inputs of A2 to be equal; thus, no current flows through
R1 or R2, and the circuit output tracks the input. When VIN is
below ground, the output of A1 is forced to ground. The
Rev. H | Page 17 of 24
AD820
noninverting input of Amplifier A2 sees the ground level output
of A1; therefore, A2 operates as a unity-gain inverter. The output at
Node C is then a full-wave rectified version of the input. Node B is
a buffered half-wave rectified version of the input. Input voltages
up to 18 V can be rectified, depending on the voltage supply used.
With a 1 mA load, this reference maintains the 4.5 V output
with a supply voltage down to 4.7 V. The amplitude of the
recovery transient for a 1 mA to 10 mA step change in load
current is under 20 mV, and settles out in a few microseconds.
Output voltage noise is less than 10 μV rms in a 25 kHz noise
bandwidth.
R1
R2
100kΩ
100kΩ
LOW POWER, 3-POLE, SALLEN KEY LOW-PASS
FILTER
+V
7
S
+V
7
S
0.01µF
0.01µF
2
3
The high input impedance of the AD820 makes it a good
selection for active filters. High value resistors can be used to
construct low frequency filters with capacitors much less than
1 μF. The AD820 picoamp level input currents contribute
minimal dc errors.
A
V
–
3
2
6
+
C
+
+
A2
6
IN
–
FULL-WAVE
RECTIFIED OUPUT
–
+
A1
–
AD820
4
AD820
4
B
+
Figure 45 shows an example of a 10 Hz three-pole Sallen Key
filter. The high value used for R1 minimizes interaction with
signal source resistance. Pole placement in this version of the
filter minimizes the Q associated with the two-pole section of
the filter. This eliminates any peaking of the noise contribution
of Resistor R1, Resistor R2, and Resistor R3, thus minimizing
the inherent output voltage noise of the filter.
HALF-WAVE
RECTIFIED OUPUT
–
100
A
90
C2
0.022µF
+V
7
S
B
C
0.01µF
R1
243kΩ
R2
R3
243kΩ
243kΩ
3
2
+
+
V
6
IN
–
C1
0.022µF
C3
0.022µF
+
10
AD820
–
4
V
–
OUT
0%
0.01µF
–V
S
Figure 43. Single-Supply Half- and Full-Wave Rectifier
4.5 V LOW DROPOUT, LOW POWER REFERENCE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
The rail-to-rail performance of the AD820 can be used to
provide low dropout performance for low power reference
circuits powered with a single low voltage supply. Figure 44
shows a 4.5 V reference using the AD820 and the AD680, a low
power 2.5 V band gap reference. R2 and R3 set up the required
gain of 1.8 to develop the 4.5 V output. R1 and C2 form a low-
pass RC filter to reduce the noise contribution of the AD680.
2.5V
OUTPUT
U2
AD820
4.5V
OUTPUT
6
5V
7
+
4
2
R2
90kΩ
(20kΩ)
2
–
0.1
1
10
100
1k
3
2.5V ± 10mV
FREQUENCY (Hz)
3
6
U1
C3
10µF/25V
AD680
R1
100kΩ
Figure 45. 10 Hz Sallen Key Low-Pass Filter
R3
100kΩ
(25kΩ)
C2
0.1µF FILM
4
C1
0.1µF
REF
COMMON
Figure 44. Single Supply 4.5 V Low Dropout Reference
Rev. H | Page 18 of 24
AD820
OFFSET VOLTAGE ADJUSTMENT
+V
7
S
The offset voltage of the AD820 is low, so external offset voltage
nulling is not usually required. Figure 46 shows the recommended
technique for the AD820 packaged in plastic DIP. Adjusting offset
voltage in this manner changes the offset voltage temperature drift
by 4 μV/°C for every millivolt of induced offset. The null pins
are not functional for the AD820 in the 8-lead SOIC and MSOP
packages.
3
2
+
6
AD820
1
5
–
20kΩ
4
–V
S
Figure 46. Offset Null
Rev. H | Page 19 of 24
AD820
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 47. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 48. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. H | Page 20 of 24
AD820
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 49. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description Package Option
Branding
AD820AN
AD820ANZ
AD820AR
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead PDIP
8-Lead PDIP
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
AD820AR-REEL
AD820AR-REEL7
AD820ARZ
AD820ARZ-REEL
AD820ARZ-REEL7
AD820ARMZ
AD820ARMZ-RL
AD820ARMZ-R7
AD820BR
AD820BR-REEL
AD820BRZ
AD820BRZ-REEL
AD820BRZ-REEL7
A2L
A2L
A2L
R-8
R-8
1 Z = RoHS Compliant Part.
Rev. H | Page 21 of 24
AD820
NOTES
Rev. H | Page 22 of 24
AD820
NOTES
Rev. H | Page 23 of 24
AD820
NOTES
©1996–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00873-0-3/11(H)
Rev. H | Page 24 of 24
相关型号：
AD820ARZ-REEL7
OP-AMP, 1500 uV OFFSET-MAX, 1.9 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8
ROCHESTER
AD820BQ
IC OP-AMP, 500 uV OFFSET-MAX, 2 MHz BAND WIDTH, CDIP8, HERMETIC SEALED, CERDIP-8, Operational Amplifier
ADI
AD820BRZ
OP-AMP, 1000 uV OFFSET-MAX, 1.8 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8
ROCHESTER
©2020 ICPDF网 联系我们和版权申明