AD8622ARZ-REEL7 [ROCHESTER]
DUAL OP-AMP, 230 uV OFFSET-MAX, 0.58 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8;
| 型号： | AD8622ARZ-REEL7 |
| 厂家： | 
Rochester Electronics |
| 描述： | DUAL OP-AMP, 230 uV OFFSET-MAX, 0.58 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8 光电二极管 |
| 文件： | 总21页 (文件大小：1454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, Precision
Rail-to-Rail Output Op Amp
AD8622/AD8624
PIN CONFIGURATIONS
FEATURES
Very low offset voltage
125 μV maximum
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8622
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Supply current: 215 μA/amp typical
Input bias current: 200 pA maximum
Low input offset voltage drift: 1.2 μV/°C maximum
Very low voltage noise: 11 nV/√Hz
Operating temperature: −40°C to +125°C
Rail-to-rail output swing
Figure 1. 8-Lead Narrow-Body SOIC
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8622
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Unity gain stable
2.5 V to 15 V operation
Figure 2. 8-Lead MSOP
APPLICATIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
Portable precision instrumentation
Laser diode control loops
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
AD8624
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
GENERAL DESCRIPTION
Figure 3. 14-Lead TSSOP
The AD8622/AD8624 are dual and quad precision rail-to-rail
output operational amplifiers with low supply currents of only
350 μA/amplifier maximum over temperature and supply
voltages. The AD8622/AD8624 also has an input bias current
cancellation circuitry that provides a very low input bias current
over the full operating temperature.
–IN A
+IN A
V+
1
12 –IN D
AD8624
2
3
4
11 +IN D
10 V–
TOP VIEW
(Not to Scale)
9
+IN C
+IN B
With a typical offset voltage of only 10 μV, offset drift of 0.5 μV/°C,
and noise of only 0.2 ꢀV p-p (0.1 Hz to 10 Hz), they are
perfectly suited for applications where large error sources
cannot be tolerated. Many systems can take advantage of the
low noise, dc precision, and rail-to-rail output swing provided
by the AD8622/AD8624 to maximize the signal-to-noise ratio
and dynamic range for low power operation. The AD8622/
AD8624 are specified for the extended industrial temperature
range of −40°C to +125°C. The AD8622 is available in lead-free
8-lead SOIC and MSOP packages, while the AD8624 is available
in lead-free 14-lead TSSOP and 16-lead LFCSP packages.
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED
PAD BE CONNECTED TO V–.
Figure 4. 16-Lead LFCSP
Table 1. Low Power Op Amps
Supply
40 V
36 V
12 V to 18 V
6 V
Single
OP97
OP777
OP1177
OP727
OP2177
OP747
OP4177
AD8663
Dual
OP297
OP497
AD8667
AD8669
ADA4692-2
ADA4692-4
Quad
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
AD8622/AD8624
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Applications Information.............................................................. 15
Input Protection ......................................................................... 15
Phase Reversal ............................................................................ 15
Micropower Instrumentation Amplifier................................. 15
Hall Sensor Signal Conditioning.............................................. 16
Simplified Schematic...................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics— 2.5 V Operation.......................... 3
Electrical Characteristics— 15 V Operation........................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
REVISION HISTORY
2/10—Rev. A to Rev. B
Changed 16-Lead to 14-Lead in Figure 62 Caption................... 19
1/10—Rev. 0 to Rev. A
Added 14-Lead TSSOP ......................................................Universal
Added 16-Lead LFCSP.......................................................Universal
Added Figure 3 and Figure 4; Renumbered Sequentially ........... 1
Changes to Table 5............................................................................ 5
Changes to Figure 10 to Figure 16.................................................. 6
Changes to Figure 26........................................................................ 9
Changes to Figure 29...................................................................... 10
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
7/09—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8622/AD8624
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS— 2.5 V OPERATION
VSY
= 2.5 V, VCM = 0 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
10
125
230
1.2
200
400
200
300
+1.3
μV
μV
ꢀV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
TΩ
pF
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
0.5
30
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
25
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = −1.3 V to +1.3 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −2.0 V to +2.0 V
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
−1.3
110
107
118
109
CMRR
AVO
120
135
Open-Loop Gain
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
RINDM
RINCM
CINDM
CINCM
1
1
5.5
3
pF
Output Voltage High
VOH
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
2.45
2.41
2.40
2.36
2.49
2.45
V
V
V
V
V
V
V
V
Output Voltage Low
VOL
−2.49 −2.45
−2.41
−2.45 −2.40
−2.36
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
30
2
mA
Ω
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.0 V to 18.0 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
125
120
145
dB
dB
μA
μA
Supply Current/Amplifier
175
225
310
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
ΦM
RL = 10 kΩ, CL = 100 pF AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
0.28
540
74
V/μs
kHz
Degrees
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Uncorrelated Current Noise Density
Correlated Current Noise Density
en p-p
en
in_uncorr
in_corr
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.2
12
0.15
0.07
μV p-p
nV/√Hz
pA/√Hz
pA/√Hz
f = 1 kHz
Rev. B | Page 3 of 20
AD8622/AD8624
ELECTRICAL CHARACTERISTICS— 15 V OPERATION
VSY
= 15 V, VCM = 0 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
10
125
230
1.2
200
500
200
500
+13.8
μV
μV
μV/°C
pA
pA
pA
pA
V
dB
dB
dB
dB
GΩ
TΩ
pF
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT −40°C ≤ TA ≤ +125°C
IB
0.5
45
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
35
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
−13.8
125
112
125
120
CMRR
AVO
VCM = −13.8 V to +13.8 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −13.5 V to +13.5 V
−40°C ≤ TA ≤ +125°C
135
137
Open-Loop Gain
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
RINDM
RINCM
CINDM
CINCM
1
1
5.5
3
pF
Output Voltage High
VOH
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to ground
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to ground
−40°C ≤ TA ≤ +125°C
14.94 14.97
14.84
14.86 14.89
14.75
V
V
V
V
V
V
V
V
Output Voltage Low
VOL
−14.97 −14.94
−14.92
−14.89 −14.90
−14.80
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
40
1.5
mA
Ω
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.0 V to 18.0 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
125
120
145
dB
dB
μA
μA
Supply Current/Amplifier
215
250
350
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
ΦM
RL = 10 kΩ, CL = 100 pF, AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
RL = 10 kΩ, CL = 20 pF, AV = 1
0.48
560
75
V/μs
kHz
Degrees
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Uncorrelated Current Noise Density
Correlated Current Noise Density
en p-p
en
in_uncorr
in_corr
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.2
11
0.15
0.06
μV p-p
nV/√Hz
pA/√Hz
pA/√Hz
f = 1 kHz
Rev. B | Page 4 of 20
AD8622/AD8624
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
THERMAL RESISTANCE
Rating
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 4-layer board.
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage2
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
18 V
VSY
10 mA
10 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 3. Thermal Resistance
Package Type
θJA
θJC
45
45
35
14
Unit
°C/W
°C/W
°C/W
°C/W
8-Lead SOIC_N (R-8)
8-Lead MSOP (RM-8)
14-Lead TSSOP (RU-14)
16-Lead LFCSP (CP-16-17)
120
142
112
55
1 The input pins have clamp diodes to the power supply pins. The input
current should be limited to 10 mA or less whenever input signals exceed
the power supply rail by 0.5 V.
ESD CAUTION
2 Differential input voltage is limited to 10 V or the supply voltage, whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 5 of 20
AD8622/AD8624
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
60
60
50
40
30
V
V
= ±2.5V
= 0V
V
V
= ±15V
= 0V
SY
SY
CM
CM
50
40
30
20
10
0
20
10
0
–100 –80 –60 –40 –20
0
20
(µV)
40
60
80 100
–100 –80 –60 –40 –20
0
20
(µV)
40
60
80
100
V
V
OS
OS
Figure 5. Input Offset Voltage Distribution
Figure 8. Input Offset Voltage Distribution
60
50
40
30
60
50
40
30
V
= ±2.5V
V
= ±15V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
20
10
0
20
10
0
0
0.2
0.4
0.6
(µV/°C)
0.8
1.0
1.2
0
0.2
0.4
0.6
TCV (µV/°C)
OS
0.8
1.0
1.2
TCV
OS
Figure 6. Input Offset Voltage Drift Distribution
Figure 9. Input Offset Voltage Drift Distribution
50
40
50
40
V
= ±15V
V
= ±2.5V
SY
SY
–40°C
+25°C
30
30
20
20
–40°C
10
10
0
0
+25°C
+85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
+85°C
+125°C
+125°C
–15
–10
–5
0
5
10
+15
–2.5
–1.5
–0.5
0.5
1.5
2.5
V
(V)
V
(V)
CM
CM
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
Figure 7. Input Offset Voltage vs. Common-Mode Voltage
Rev. B | Page 6 of 20
AD8622/AD8624
0
–10
–20
–30
–40
–50
–60
10
0
V
= ±15V
V
= ±2.5V
SY
SY
I
+
B
I
I
+
–
I
–
B
B
B
–10
–20
–30
–40
–50
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Input Bias Current vs. Temperature
Figure 11. Input Bias Current vs. Temperature
60
40
50
25
V
= ±15V
V
= ±2.5V
SY
SY
0
20
–25
–50
–75
–100
–125
–150
0
–20
–40
–60
–15
–10
–5
0
5
10
15
–2.5
–1.5
–0.5
0.5
1.5
2.5
V
(V)
V
(V)
CM
CM
Figure 15. Input Bias Current vs. Common-Mode Voltage
Figure 12. Input Bias Current vs. Common-Mode Voltage
100
10
1
100
10
1
V
= ±15V
SY
V
= ±2.5V
SY
V
– V
OH
CC
V
V
– V
OH
CC
V
– V
EE
OL
0.1
0.1
– V
EE
OL
0.01
0.01
0.001
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 13. Output Voltage to Supply Rail vs. Load Current
Figure 16. Output Voltage to Supply Rail vs. Load Current
Rev. B | Page 7 of 20
AD8622/AD8624
0.06
0.16
V
R
= ±15V
= 10kΩ
V
R
= ±2.5V
= 10kΩ
SY
SY
L
L
0.14
0.12
0.10
0.08
0.05
V
– V
OH
V
– V
OH
CC
CC
0.04
0.03
0.02
0.06
0.04
0.02
0
V
– V
EE
OL
V
– V
EE
OL
0.01
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Output Voltage to Supply Rail vs. Temperature
Figure 20. Output Voltage to Supply Rail vs. Temperature
0.35
0.35
0.30
0.30
0.25
0.20
0.15
+125°C
0.25
0.20
0.15
0.10
0.05
0
+85°C
+25°C
V
= ±15V
SY
–40°C
V
= ±2.5V
SY
0.10
0.05
–0.05
0
2
4
6
8
10
(±V)
12
14
16
18
–50
–25
0
25
50
75
100
125
V
TEMPERATURE (°C)
SY
Figure 18. Supply Current vs. Supply Voltage
Figure 21. Supply Current vs. Temperature
100
100
80
100
100
80
V
R
= ±2.5V
= 10kΩ
V
R
= ±15V
SY
SY
= 10kΩ
L
L
PHASE
80
60
40
80
60
40
PHASE
60
60
40
40
GAIN
GAIN
20
0
20
20
0
20
0
0
–20
–20
–20
–20
–40
1k
–40
10M
–40
1k
–40
10M
10k
100k
FREQUENCY (Hz)
1M
10k
100k
FREQUENCY (Hz)
1M
Figure 19. Open-Loop Gain and Phase vs. Frequency
Figure 22. Open-Loop Gain and Phase vs. Frequency
Rev. B | Page 8 of 20
AD8622/AD8624
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
R
= ±2.5V
= 10kΩ
V
R
= ±15V
SY
SY
= 10kΩ
L
L
A
= 100
= 10
A
= 100
= 10
V
V
A
A
V
V
A
= 1
A = 1
V
V
–10
–20
–30
–10
–20
–30
–40
100
–40
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Closed-Loop Gain vs. Frequency
Figure 26. Closed-Loop Gain vs. Frequency
10k
1k
10k
1k
V
= ±2.5V
V
= ±15V
SY
SY
A
= 100
V
A
= 100
V
A
= 10
V
A
= 10
V
100
10
100
10
A
= 1
V
A
= 1
V
1
1
0.1
100
0.1
100
1k
10k
FREQUENCY (Hz)
100k
1M
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 24. Output Impedance vs. Frequency
Figure 27. Output Impedance vs. Frequency
140
120
100
80
140
120
100
80
V
= ±2.5V
V
= ±15V
SY
SY
60
60
40
40
20
20
0
10
0
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. CMRR vs. Frequency
Figure 28. CMRR vs. Frequency
Rev. B | Page 9 of 20
AD8622/AD8624
120
100
80
120
100
80
V
= ±2.5V
V
= ±15V
SY
SY
PSRR+
PSRR–
PSRR+
PSRR–
60
60
40
40
20
0
20
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. PSRR vs. Frequency
Figure 32. PSRR vs. Frequency
50
45
50
45
V
A
R
= ±2.5V
= 1
= 10kΩ
V
A
R
= ±15V
SY
SY
= 1
V
L
V
L
= 10kΩ
40
35
30
25
40
35
30
25
OS–
OS–
OS+
OS+
20
15
10
20
15
10
5
0
5
0
0.01
0.1
1
10
100
0.01
0.1
1
10
100
CAPACITANCE (nF)
CAPACITANCE (nF)
Figure 30. Small-Signal Overshoot vs. Load Capacitance
Figure 33. Small-Signal Overshoot vs. Load Capacitance
V
= ±2.5V
= 1
= 10kΩ
= 100pF
SY
V
= ±15V
= 1
= 10kΩ
= 100pF
SY
A
R
C
V
L
L
A
R
C
V
L
L
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 31. Large-Signal Transient Response
Figure 34. Large-Signal Transient Response
Rev. B | Page 10 of 20
AD8622/AD8624
V
= ±2.5V
V
= ±15V
SY
SY
A
R
C
= 1
= 10kΩ
= 100pF
A
R
C
= 1
= 10kΩ
= 100pF
V
L
L
V
L
L
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 35. Small-Signal Transient Response
Figure 38. Small-Signal Transient Response
0.4
0.2
0
0.4
0.2
0
V
A
R
= ±2.5V
= –100
= 10kΩ
V
A
R
= ±15V
= –100
= 10kΩ
SY
SY
V
L
V
L
INPUT
INPUT
OUTPUT
OUTPUT
0
0
–1
–10
–20
–2
–3
TIME (20µs/DIV)
TIME (20µs/DIV)
Figure 39. Negative Overload Recovery
Figure 36. Negative Overload Recovery
0.2
0
0.2
0
INPUT
INPUT
–0.2
–0.2
20
10
0
3
2
1
OUTPUT
OUTPUT
V
= ±15V
SY
–10
–20
V
A
R
= ±2.5V
= –100
= 10kΩ
A
R
= –100
= 10kΩ
SY
V
L
0
V
L
–1
TIME (20µs/DIV)
TIME (20µs/DIV)
Figure 40. Positive Overload Recovery
Figure 37. Positive Overload Recovery
Rev. B | Page 11 of 20
AD8622/AD8624
12
12
10
8
V
A
= ±15V
V
= ±15V
A = +1
V
SY
= –1
SY
V
10
8
0.1%
0.1%
0.01%
0.01%
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
SETTLING TIME (µs)
SETTLING TIME (µs)
Figure 41. Output Step vs. Settling Time
Figure 44. Output Step vs. Settling Time
100
100
V
= ±15V
V
= ±2.5V
SY
SY
10
10
1
1
1
10
100
1k
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 45. Voltage Noise Density vs. Frequency
Figure 42. Voltage Noise Density vs. Frequency
1
1
R
R
R
R
S1
V
= ±15V
S1
V
= ±2.5V
SY
SY
S2
S2
UNCORRELATED
S1
UNCORRELATED
S1
R
= 0Ω
R
= 0Ω
CORRELATED
0.1
0.1
CORRELATED
R
= R
S1
S2
R
= R
S1
S2
0.01
0.01
1
10
100
1k
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 46. Current Noise Density vs. Frequency
Figure 43. Current Noise Density vs. Frequency
Rev. B | Page 12 of 20
AD8622/AD8624
V
= ±2.5V
V
= ±15V
SY
SY
TIME (1s/DIV)
TIME (1s/DIV)
Figure 47. 0.1 Hz to 10 Hz Noise
Figure 49. 0.1 Hz to 10 Hz Noise
1
0.1
1
0.1
V
= ±2.5V
V
= ±15V
SY
f = 1kHz
= 10kΩ
SY
f = 1kHz
R = 10kΩ
L
R
L
0.01
0.01
0.001
0.001
0.0001
0.0001
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 48. THD + Noise vs. Amplitude
Figure 50. THD + Noise vs. Amplitude
Rev. B | Page 13 of 20
AD8622/AD8624
0.1
0.1
V
R
V
= ±15V
= 10kΩ
= 300mV rms
SY
V
R
= ±2.5V
= 10kΩ
= 300mV rms
SY
L
L
IN
V
IN
0.01
0.001
0.01
0.001
0.0001
0.0001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 51. THD + Noise vs. Frequency
Figure 53. THD + Noise vs. Frequency
0
–20
–40
–60
100kΩ
1kΩ
R
L
–80
–100
–120
V
= ±2.5V TO ±15V
SY
R
A
= 10kΩ
= –100
L
V
–140
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 52. Channel Separation vs. Frequency
Rev. B | Page 14 of 20
AD8622/AD8624
APPLICATIONS INFORMATION
V
INPUT PROTECTION
IN
V
= ±15V
SY
The maximum differential input voltage that can be applied to
the AD8622/AD8624 is determined by the internal diodes
connected across its inputs and series resistors at each input. These
internal diodes and series resistors limit the maximum
V
OUT
differential input voltage to 10 V and are needed to prevent base-
emitter junction breakdown from occurring in the input stage of
the AD8622/AD8624 when very large differential voltages are
applied. In addition, the internal resistors limit the currents that
flow through the diodes. However, in applications where large
differential voltages can be inadvertently applied to the device,
large currents may still flow through these diodes. In such a
case, external resistors must be placed at both inputs of the op
amp to limit the input currents to 10 mA (see Figure 54).
TIME (200µs/DIV)
Figure 55. No Phase Reversal
MICROPOWER INSTRUMENTATION AMPLIFIER
The AD8622 is a dual, high precision, rail-to-rail output op amp
operating at just 215 ꢀA quiescent current per amplifier. Its
ultralow offset, offset drift, and voltage noise, combined with its
very low bias current and high common-mode rejection ratio
(CMRR), are ideally suited for high accuracy and micropower
instrumentation amplifier.
R1
R2
500Ω
500Ω
2
3
1
AD862x
Figure 56 shows the classic 2-op-amp instrumentation amplifier
with four resistors using the AD8622. The key to high CMRR
for this instrumentation amplifier are resistors that are well
matched from both the resistive ratio and the relative drift. For
true difference amplification, matching of the resistor ratio is
very important, where R3/R4 = R1/R2. Assuming perfectly
matched resistors, the gain of the circuit is 1 + R2/R1, which is
approximately 100. Tighter matching of two op amps in one
package, like the AD8622, offers a significant boost in
Figure 54. Input Protection
PHASE REVERSAL
An undesired phenomenon, phase reversal (also known as
phase inversion) occurs in many op amps when one or both of
the inputs are driven beyond the specified input voltage range
(IVR), in effect reversing the polarity of the output. In some
cases, phase reversal can induce lockups and even cause
equipment damage as well as self destruction.
performance over the classical 3-op-amp configuration. Overall,
The AD8622/AD8624 amplifiers have been carefully designed to
prevent output phase reversal when both inputs are maintained
within the specified input voltage range. In addition, even if one
or both inputs exceed the input voltage range but remain within
the supply rails, the output still does not phase reverse. Figure 55
shows the input/output waveforms of the AD8622/AD8624
configured as a unity-gain buffer with a supply voltage of 15 V.
the circuit only requires about 430 μA of supply current.
R3
10.1kΩ
R2
1MΩ
+15V
R4
+15V
1MΩ
–
R1
10.1kΩ
1/2
–
AD8622
1/2
V
V1
AD8622
+
+
O
V2
–15V
NOTES
1. V = 100(V2 – V1)
–15V
O
2. TYPICAL: 0.01mV < |V2 – V1| < 149.7mV
3. TYPICAL: –14.97V < V < +14.97V
O
4. USE MATCHED RESISTORS.
Figure 56. Micropower Instrumentation Amplifier
Rev. B | Page 15 of 20
AD8622/AD8624
netic field. Using the 4.12k:98.8k resistive divider, the bias
voltage of the Hall element is reduced to 100 mV, leading to only
250 μA of power consumption. The 3-op-amp in-amp
HALL SENSOR SIGNAL CONDITIONING
The AD8622/AD8624 is also highly suitable for high accuracy,
low power signal conditioning circuits. One such use is in Hall
sensor signal conditioning (see Figure 57). The magnetic
sensitivity of a Hall element is proportional to the bias voltage
applied across it. With 1 V bias voltage, the Hall element
consumes about 2.5 mA of supply current and has a sensitivity
of 5.5 mV/mT typical. To reduce power consumption, bias
voltage must be reduced, but at the risk of lower sensitivity. The
only way to achieve higher sensitivity is by introducing a gain
using a precision micropower amplifier. The AD8622/AD8624,
with all its features, is well suited to amplify the sensitivity of the
Hall element.
configuration of the AD8622/AD8624 then increases the
sensitivity to 55 mV/mT. The key to high CMRR for this in-amp
configuration are resistors that are well matched (where R1/R2
= R3/R4) from both the resistive ratio and relative drift. The
resistors are important in determining the performance over
manufacturing tolerances, time and temperature. At least 1% or
better resistors are recommended. Using the AD8622/AD8624 to
amplify the sensor signal can reduce power while also achieving
higher sensitivity. The total current consumed is just 1.2 mA,
resulting in 21× improvement in sensitivity/power.
The ADR121 is a precision micropower 2.5 V voltage reference.
A precision voltage reference is required to hold a constant current
so that the Hall voltage only depends on the intensity of the mag-
V
V
SY
SY
+
C1
R2
9.9kΩ
1µF TO 10µF
AD862x
–
HALL
ELEMENT
V
SY
R5
R1
ADR121 – 2.5V
9.9kΩ
9.9kΩ
–
V
R8
SY
4.12kΩ
400Ω
×4
C3
0.1µF
TO 10µF
R7
200Ω
AD862x
+
R6
9.9kΩ
R3
9.9kΩ
+
C2
0.1µF
+
55mV
mT
V
= 2.5V +
× MAGNETIC FIELD (mT)
OUT
R9
98.8kΩ
AD862x
–
V
SY
–
AD862x
+
R4
9.9kΩ
NOTES
1. USE MATCHED RESISTORS FOR IN-AMP.
2. FOR INFORMATION ON C1, C2, AND C3, REFER TO ADR121 DATA SHEET.
Figure 57. Hall Sensor Signal Conditioning
Rev. B | Page 16 of 20
AD8622/AD8624
SIMPLIFIED SCHEMATIC
V+
R3
R2
R1
Q10
Q11
C1
V
Q6
B2
Q3
V
B1
Q5
INPUT BIAS
CANCELLATION
CIRCUITRY
Q4
Q8
OUT x
500Ω
Q1
Q2
+IN x
D1
D2
500Ω
–IN x
Q7
Q12
Q9
D4
D3
V–
Figure 58. Simplified Schematic
Rev. B | Page 17 of 20
AD8622/AD8624
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 60. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 18 of 20
AD8622/AD8624
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
1
0.65
BSC
12
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
5
9
8
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8622ARMZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
Package Option
RM-8
RM-8
RM-8
R-8
Branding
A1P
A1P
AD8622ARMZ-REEL
AD8622ARMZ-R7
AD8622ARZ
AD8622ARZ-REEL
AD8622ARZ-REEL7
AD8624ACPZ-R2
AD8624ACPZ-R7
AD8624ACPZ-RL
AD8624ARUZ
8-Lead MSOP
A1P
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
14-Lead TSSOP
14-Lead TSSOP
R-8
R-8
CP-16-17
CP-16-17
CP-16-17
RU-14
AD8624ARUZ-RL
RU-14
1 Z = RoHS Compliant Part.
Rev. B | Page 19 of 20
AD8622/AD8624
NOTES
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07527-0-2/10(B)
Rev. B | Page 20 of 20
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