ADG438FBNZ [ROCHESTER]
8-CHANNEL, SGL ENDED MULTIPLEXER, PDIP16, PLASTIC, DIP-16;
| 型号： | ADG438FBNZ |
| 厂家： | 
Rochester Electronics |
| 描述： | 8-CHANNEL, SGL ENDED MULTIPLEXER, PDIP16, PLASTIC, DIP-16 光电二极管 |
| 文件： | 总9页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 4/8 Channel
a
Fault-Protected Analog Multiplexers
ADG438F/ADG439F
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Fast Switching Times
tON 250 ns max
tOFF 150 ns max
ADG439F
ADG438F
S1
S1A
S4A
Fault and Overvoltage Protection (–40 V, +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped Within Power
Supplies If an Overvoltage Occurs
Latch-Up Proof Construction
Break Before Make Construction
TTL and CMOS Compatible Inputs
DA
DB
D
S1B
S4B
S8
APPLICATIONS
Data Acquisition Systems
1 OF 8
DECODER
1 OF 4
DECODER
Industrial and Process Control Systems
Avionics Test Equipment
A0 A1 A2 EN
A0 A1 EN
Signal Routing Between Systems
High Reliability Control Systems
PRODUCT HIGHLIGHTS
1. Fault Protection.
GENERAL DESCRIPTION
The ADG438F/ADG439F are CMOS analog multiplexers, the
ADG438F comprising 8 single channels and the ADG439F
comprising four differential channels. These multiplexers pro-
vide fault protection. Using a series n-channel, p-channel, n-
channel MOSFET structure, both device and signal source
protection is provided in the event of an overvoltage or power
loss. The multiplexer can withstand continuous overvoltage
inputs from –40 V to +55 V. During fault conditions, the multi-
plexer input (or output) appears as an open circuit and only a
few nanoamperes of leakage current will flow. This protects not
only the multiplexer and the circuitry driven by the multiplexer,
but also protects the sensors or signal sources which drive the
multiplexer.
The ADG438F/ADG439F can withstand continuous volt-
age inputs up to –40 V or +55 V. When a fault occurs due
to the power supplies being turned off, all the channels
are turned off and only a leakage current of a few nano-
amperes flows.
2. ON channel turns OFF while fault exists.
3. Low RON.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
The ADG438F switches one of eight inputs to a common out-
put as determined by the 3-bit binary address lines A0, A1 and
A2. The ADG439F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used to
enable or disable the device. When disabled, all channels are
switched OFF.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latch-up.
7. Improved OFF Isolation.
Trench isolation enhances the channel-to-channel isolation
of the ADG438F/ADG439F.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADG438F/ADG439F–SPECIFICATIONS1
Dual Supply
(VDD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted)
B Version
–40؇C to
+85؇C
–40؇C to
+105؇C
Parameter
+25؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS + 1.2
VDD – 0.8
400
VSS + 1.2
VDD – 0.8
400
V min
V max
Ω max
% max
%/°C typ
% max
RON
∆RON
RON Drift
RON Match
–10 V < VS < +10 V, IS = 1 mA;
–5 V < VS < +5 V, IS = 1 mA;
VS = 0 V, IS = 1 mA
5
5
0.6
3
3
3
VS = ± 10 V, IS = 1 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
±0.01
±0.5
±0.01
±0.5
±0.5
±0.01
±0.5
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = ±10 V, VS = ϯ10 V;
Test Circuit 2
VD = ±10 V, VS = ϯ10 V;
Test Circuit 3
±2
±5
Drain OFF Leakage ID (OFF)
ADG438F
ADG439F
Channel ON Leakage ID, IS (ON)
ADG438F
ADG439F
±5
±5
±30
±15
VS = VD = ±10 V;
Test Circuit 4
±5
±5
±30
±15
±0.5
FAULT
Output Leakage Current
(With Overvoltage)
Input Leakage Current
(With Overvoltage)
Input Leakage Current
(With Power Supplies OFF)
±0.02
±0.1
±0.005
±0.1
±0.001
±0.1
nA typ
µA max
µA typ
µA max
µA typ
µA max
VS = –33 V, +33 V or +50 V, VD = 0 V, Test Circuit 3
±2
±1
±1
±10
±2
VS = ±25 V, VD = ϯ10 V, Test Circuit 5
VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
Test Circuit 6
±4
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
±1
±1
µA max
VIN = 0 or VDD
CIN, Digital Input Capacitance
5
pF typ
DYNAMIC CHARACTERISTICS2
tTRANSITION
170
220
10
ns typ
ns max
ns min
RL = 1 MΩ, CL = 35 pF;
VS1 = ±10 V, VS8 = ϯ10 V; Test Circuit 7
RL = 1 kΩ, CL = 35 pF;
300
10
320
10
tOPEN
VS = +5 V; Test Circuit 8
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 9
RL = 1 kΩ, CL = 35 pF;
tON (EN)
tOFF (EN)
200
250
110
150
ns typ
ns max
ns typ
ns max
300
180
300
180
VS = +5 V; Test Circuit 9
tSETT, Settling Time
0.1%
0.01%
Charge Injection
OFF Isolation
0.5
1.7
0.5
1.7
µs typ
µs typ
pC typ
dB typ
RL = 1 kΩ, CL = 35 pF;
VS = +5 V
VS = 0 V, RS = 0 Ω, CL= 1 nF; Test Circuit 10
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms; Test Circuit 11
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms; Test Circuit 12
4
80
Channel-to-Channel Crosstalk
85
5
dB typ
pF typ
CS (OFF)
CD (OFF)
ADG438F
ADG439F
50
25
pF typ
pF typ
POWER REQUIREMENTS
IDD
0.05
0.15
0.01
0.02
mA typ
mA max
mA typ
mA max
VIN = 0 V or 5 V
0.25
0.04
0.25
0.04
ISS
NOTES
1Temperature range is as follows: B Version: –40°C to +105°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. D
ADG438F/ADG439F
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
Table I. ADG438F Truth Table
A2
A1
A0
EN
ON SWITCH
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VEN, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,
Whichever Occurs First
VS, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V
to VDD + 40 V
VS, Analog Input Overvoltage with Power OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
X = Don’t Care
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Table II. ADG439F Truth Table
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package
A1
A0
EN
ON SWITCH PAIR
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
NONE
1
2
3
4
X = Don’t Care
θJA, Thermal Impedance
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ADG438F/ADG439F PIN CONFIGURATIONS
DIP/SOIC
DIP/SOIC
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
A0
EN
1
2
3
16 A1
15 A2
14 GND
A0
EN
1
2
3
16 A1
15 GND
14
V
V
V
SS
SS
DD
ADG438F
ADG439F
4
5
13
V
4
5
13 S1B
12 S2B
S1
S1A
DD
TOP VIEW
TOP VIEW
12 S5
S2
S3
S4
D
S2A
S3A
S4A
DA
(Not to Scale)
(Not to Scale)
6
7
11 S6
10 S7
6
7
11 S3B
10 S4B
ORDERING GUIDE
8
9
S8
8
9
DB
Model
Temperature Range
Package Option*
ADG438FBN
ADG438FBR
–40°C to +105°C
–40°C to +105°C
N-16
R-16N
ADG439FBN
ADG439FBR
ADG439FBRW
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
N-16
R-16N
R-16W
*N = Plastic DIP; R-16N = 0.15" Small Outline IC (SOIC); R-16W = 0.3"
Small Outline IC (SOIC).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG438F/ADG439F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
ADG438F/ADG439F
TERMINOLOGY
Typical Performance Graphs
VDD
VSS
Most positive power supply potential.
Most negative power supply potential.
Ground (0 V) reference.
2000
GND
RON
T
= +25؇C
A
1750
1500
1250
1000
750
500
250
0
Ohmic resistance between D and S.
∆RON
RON variation due to a change in the analog
input voltage with a constant load current.
V
V
= +5V
= –5V
DD
SS
R
R
ON Drift
ON Match
Change in RON when temperature changes
by one degree Celsius.
Difference between the RON of any two
channels.
V
V
= +10V
= –10V
DD
SS
IS (OFF)
Source leakage current when the switch is
off.
V
V
= +15V
= –15V
DD
SS
ID (OFF)
Drain leakage current when the switch is off.
–15
–10
–5
0
5
10
15
V
D
(V ) – Volts
S
ID, IS (ON)
Channel leakage current when the switch is
on.
Figure 1. On Resistance as a Function of VD (VS)
V
D (VS)
Analog voltage on terminals D, S.
CS (OFF)
Channel input capacitance for “OFF”
condition.
1m
V
V
V
= 0V
= 0V
= 0V
DD
100
10
1
SS
CD (OFF)
Channel output capacitance for “OFF”
condition.
D
CD, CS (ON)
CIN
“ON” switch capacitance.
Digital input capacitance.
100n
10n
1n
OPERATING RANGE
t
ON (EN)
Delay time between the 50% and 90% points
of the digital input and switch “ON”
condition.
100p
10p
1p
t
OFF (EN)
Delay time between the 50% and 90% points
of the digital input and switch “OFF”
condition.
–50 –40 –30 –20 –10
0
10
20
30 40
50
60
V
– INPUT VOLTAGE – Volts
IN
tTRANSITION
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
Figure 2. Input Leakage Current as a Function of VS
(Power Supplies OFF) During Overvoltage Conditions
tOPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
1m
V
V
V
= +15V
= –15V
= 0V
DD
100
10
SS
VINL
VINH
Maximum input voltage for Logic “0”.
Minimum input voltage for Logic “1”.
Input current of the digital input.
D
1
I
INL (IINH
)
100n
OPERATING RANGE
Off Isolation
A measure of unwanted signal coupling
through an “OFF” channel.
10n
1n
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
100p
10p
1p
IDD
ISS
Positive supply current.
Negative supply current.
–50 –40 –30 –20 –10
0
10 20
30 40 50
60
V
IN
– INPUT VOLTAGE – Volts
Figure 3. Output Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
–4–
REV. D
ADG438F/ADG439F
2000
1750
1500
1250
1000
750
100
10
V
V
= +15V
= –15V
DD
V
DD
V
SS
= +15V
= –15V
SS
V
V
= +10V
= –10V
D
S
I
D
(OFF)
1
I
S
(OFF)
+105؇C
500
0.1
0.01
+85؇C
I
D
(ON)
95
250
+25؇C
0
–15
–10
–5
0
5
10
15
25
35
45
55
65
75
85
105
V
D
(V ) – Volts
S
TEMPERATURE – ؇C
Figure 4. On Resistance as a Function of VD (VS) for
Different Temperatures
Figure 7. Leakage Currents as a Function of Temperature
1m
260
V
= +2V
IN
V
V
V
= +15V
= –15V
= 0V
DD
100
10
1
240
220
200
180
160
140
120
100
SS
D
tON (EN)
100n
10n
1n
OPERATING RANGE
tTRANSITION
100p
10p
1p
tOFF (EN)
–50 –40 –30 –20 –10
0
10 20
30
40
50
60
10
11
12
V
13
– Volts
14
15
V
S
– INPUT VOLTAGE – Volts
SUPPLY
Figure 5. Input Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
Figure 8. Switching Time vs. Power Supply
280
0.3
V
V
V
= +15V
= –15V
= +5V
DD
260
240
220
200
180
160
140
120
100
V
V
= +15V
= –15V
DD
SS
SS
IN
0.2
0.1
T
A
= +25؇C
tON (EN)
I
S
(OFF)
I
(OFF)
D
tTRANSITION
0.0
I
(ON)
D
–0.1
–0.2
tOFF (EN)
85
25
45
65
105
–14
–10
–6
–2
2
6
10
14
TEMPERATURE – ؇C
V , V – Volts
S
D
Figure 9. Switching Time vs. Temperature
Figure 6. Leakage Currents as a Function of VD (VS)
REV. D
–5–
ADG438F/ADG439F
THEORY OF OPERATION
n-channel threshold voltage (VTN). When a voltage more nega-
tive than VSS is applied to the multiplexer, the p-channel
MOSFET will turn off since the analog input is more negative
than the difference between VSS and the p-channel threshold
voltage (VTP).
The ADG438F/ADG439F multiplexers are capable of with-
standing overvoltages from –40 V to +55 V, irrespective of
whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET and an n-channel MOSFET, connected in series.
When the analog input exceeds the power supplies, one of the
MOSFETs will switch off, limiting the current to sub-microamp
levels, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. Figure 12 illustrates the
channel architecture that enables these multiplexers to with-
stand continuous overvoltages.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches on
the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off since the gate to source voltage applied to this
MOSFET is negative.
When an analog input of VSS + 1.2 V to VDD – 0.8 V is applied
to the ADG438F/ADG439F, the multiplexer behaves as a
standard multiplexer, with specifications similar to a standard
multiplexer, for example, the on-resistance is 180 Ω typically.
However, when an overvoltage is applied to the device, one of
the three MOSFETs will turn off.
During fault conditions, the leakage current into and out of the
ADG438F/ADG439F is limited to a few microamps. This pro-
tects the multiplexer and succeeding circuitry from over stresses
as well as protecting the signal sources which drive the multi-
plexer. Also, the other channels of the multiplexer will be
undisturbed by the overvoltage and will continue to operate
normally.
Figures 10 to 13 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input ap-
plied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between VDD and the
Q1
Q2
Q3
Q1
Q2
Q3
+55V
OVERVOLTAGE
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
n-CHANNEL
MOSFET IS
OFF
V
DD
V
SS
Figure 10. +55 V Overvoltage Input to the ON Channel
Figure 12. +55 V Overvoltage with Power OFF
Q1
Q2
Q3
Q1
Q2
Q3
–40V
OVERVOLTAGE
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
p-CHANNEL
MOSFET IS
OFF
V
V
DD
SS
Figure 13. –40 V Overvoltage with Power OFF
Figure 11. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
Test Circuits
I
V
DD
V
V
DS
SS
V
V
V
DD
SS
V
DD
SS
V
SS
DD
I
(OFF)
A
S
V1
S1
S2
S8
S1
S2
S8
I
(OFF)
A
D
D
D
V
S
V
D
D
S
+0.8V
EN
+0.8V
EN
V
S
V
D
V
S
R
= V /I
1 DS
ON
Test Circuit 1. On Resistance
Test Circuit 2. IS (OFF)
Test Circuit 3. ID (OFF)
–6–
REV. D
ADG438F/ADG439F
0V
0V
V
V
V
SS
DD
V
V
V
DD
SS
V
SS
V
DD
V
SS
DD
V
SS
DD
I
(ON)
A
V
S
0V
A
D
A2
S1
S1
S2
D
S1
S2
S8
A
A1
A0
EN
ADG438F*
GND
D
V
D
S8
D
S8
V
D
+0.8V
EN
+2.4V
EN
V
S
V
S
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 5. Input Leakage Current
(with Overvoltage)
Test Circuit 4. ID (ON)
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
V
SS
V
DD
3V
ADDRESS
V
V
50%
50%
SS
DD
DRIVE (V
)
IN
A2
A1
A0
V
S1
S1
V
IN
50⍀
S2 THRU S7
S8
V
S8
ADG438F*
90%
+2.4V
EN
D
V
OUT
V
OUT
GND
C
35pF
R
1M⍀
L
L
90%
tTRANSITION
tTRANSITION
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 7. Switching Time of Multiplexer, tTRANSITION
V
V
V
V
DD
SS
3V
SS
DD
A2
V
C
S1
S2 THRU S7
S
ADDRESS
A1
A0
V
IN
DRIVE (V )
IN
50⍀
ADG438F*S8
+2.4V
EN
D
V
OUT
80%
80%
GND
R
1k⍀
L
L
V
OUT
35pF
tOPEN
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 8. Break-Before-Make Delay, tOPEN
V
V
V
DD
SS
3V
V
SS
ENABLE
DD
50%
50%
A2
DRIVE (V
)
IN
S1
S2 THRU S8
V
S
A1
A0
0V
tOFF (EN)
0.9V
ADG438F*
V
O
EN
0.9V
O
D
V
OUT
O
R
1k⍀
C
L
35pF
L
50⍀
OUTPUT
V
IN
GND
0V
tON (EN)
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 9. Enable Delay, tON (EN), tOFF (EN)
REV. D
–7–
ADG438F/ADG439F
V
V
V
V
DD
SS
3V
DD
SS
A2
A1
A0
LOGIC
INPUT (V
)
IN
ADG438F*
R
S
0V
D
S
V
OUT
C
1nF
EN
L
V
S
V
⌬ V
OUT
OUT
V
IN
GND
Q
= C
؋
⌬V L
INJ
OUT
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 10. Charge Injection
V
SS
V
DD
V
DD
V
V
SS
2.4V
DD
A0
A1
A2
S1
EN
V
DD
S1
S8
A2
ADG438F*
A1
A0
EN
D
V
S
ADG438F*
V
OUT
V
OUT
D
S2
S8
1k⍀
1k⍀
R
1k⍀
L
GND
V
S
GND
CROSSTALK = 20 LOG V
* SIMILAR CONNECTION FOR ADG439F
/V
OUT IN
V
SS
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 11. OFF Isolation
Test Circuit 12. Channel-to-Channel Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic (N-16)
0.840 (21.34)
0.745 (18.92)
16
9
0.280 (7.11)
0.240 (6.10)
8
1
0.325 (8.26)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.045 (1.15)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
PLANE
16-Lead SOIC (R-16W)
16-Lead SOIC (R-16N)
(Narrow Body)
(Wide Body)
0.4133 (10.50)
0.3977 (10.00)
0.3937 (10.00)
0.3859 (9.80)
16
9
9
8
16
1
0.1574 (4.00)
0.2440 (6.20)
0.2284 (5.80)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
1
8
؋
45؇ 0.0098 (0.25)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
PIN 1
x 45°
8؇
0؇
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
–8–
REV. D
相关型号：
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