ADG786BCP-REEL [ROCHESTER]
TRIPLE 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, QCC20, 4 X 4 MM, CSP-20;
| 型号： | ADG786BCP-REEL |
| 厂家： | 
Rochester Electronics |
| 描述： | TRIPLE 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, QCC20, 4 X 4 MM, CSP-20 |
| 文件： | 总13页 (文件大小：823K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 ꢀ, 1.8 V to 5.5 V, ꢁ2.5 V Triple/Quad
a
SPDT Switches in Chip Scale Packages
ADG786/ADG788
FEATURES
FUNCTIO NAL BLO CK D IAGRAMS
1.8 V to 5.5 V Single Supply
ꢁ2.5 V Dual Supply
2.5 ꢀ On Resistance
0.5 ꢀ On Resistance Flatness
100 pA Leakage Currents
19 ns Switching Times
ADG786
S1A
D1
S4A
D2
S1B
D1
S3A
D3
S4B
S1A
S1B
IN1
IN4
S3B
Triple SPDT: ADG786
ADG788
S2A
Quad SPDT: ADG788
D2
IN2
IN3
20-Lead 4 mm ꢂ 4 mm Chip Scale Packages
Low Power Consumption
TTL/CMOS-Compatible Inputs
For Functionally-Equivalent Devices in 16-Lead TSSOP
Packages, See ADG733/ADG734
S2B
S3B
D3
S2B
D2
LOGIC
S2A
S3A
A0 A1 A2
SWITCHES SHOWN FOR A LOGIC “1” INPUT
EN
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he ADG786 and ADG788 are low voltage, CMOS devices
comprising three independently selectable SPDT (single pole,
double throw) switches and four independently selectable SPDT
switches respectively.
1. Small 20-Lead 4 mm × 4 mm Chip Scale Packages (CSP).
2. Single/Dual Supply Operation. T he ADG786 and ADG788
are fully specified and guaranteed with 3 V ± 10% and
5 V ± 10% single supply rails, and ±2.5 V ± 10% dual
supply rails.
Low power consumption and operating supply range of 1.8 V to
5.5 V and dual ±2.5 V make the ADG786 and ADG788 ideal
for battery powered, portable instruments and many other
applications. All channels exhibit break-before-make switch-
ing action preventing momentary shorting when switching
channels. An EN input on the ADG786 is used to enable or
disable the device. When disabled, all channels are switched OFF.
3. Low On Resistance (2.5 Ω typical).
4. Low Power Consumption (<0.01 µW).
5. Guaranteed Break-Before-Make Switching Action.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high switch-
ing speed, very low on resistance, high signal bandwidths and
low leakage currents. On resistance is in the region of a few
ohms, is closely matched between switches and very flat over
the full signal range. T hese parts can operate equally well in
either direction and have an input signal range which extends to
the supplies.
T he ADG786 and ADG788 are available in small 20-lead
chip scale packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
1
(V = 5 V ꢁ 10%, V = 0 V, GND = 0 V, unless otherwise noted.)
ADG786/ADG788–SPECIFICATIONS
DD
SS
B Version
–40ꢃC
P aram eter
+25ꢃC
to +85ꢃC
Unit
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
T est Circuit 1
VS = 0 V to VDD, IDS = 10 mA
5.0
0.1
0.4
On-Resistance Match between
Channels (∆RON
)
On-Resistance Flatness (RFLAT (ON)
)
0.5
VS = 0 V to VDD, IDS = 10 mA
1.2
LEAKAGE CURRENT S
VDD = 5.5 V
Source OFF Leakage IS (OFF)
±0.01
±0.1
±0.01
±0.1
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
T est Circuit 2
VD = VS = 1 V, or 4.5 V;
T est Circuit 3
±0.3
±0.5
Channel ON Leakage ID, IS (ON)
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
4
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACT ERIST ICS2
tON
19
7
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS1A = 3 V, VS1B = 0 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 3 V, T est Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 3 V, T est Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 3 V, T est Circuit 6
VS = 2 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 7
34
12
40
12
1
tOFF
ADG786
t
t
ON(EN)
OFF(EN)
20
7
Break-Before-Make T ime Delay, tD
Charge Injection
13
±3
–72
–67
Off Isolation
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 9
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
160
11
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, T est Circuit 10
f = 1 MHz
CD, CS (ON)
34
pF typ
f = 1 MHz
POWER REQUIREMENT S
IDD
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
0.001
µA typ
1.0
µA max
NOT ES
1T emperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG786/ADG788
1
SPECIFICATIONS
(V = 3 V ꢁ 10%, V = 0 V, GND = 0 V, unless otherwise noted.)
DD
SS
B Version
–40ꢃC
P aram eter
+25ꢃC
to +85ꢃC
Unit
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
6
11
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IDS = 10 mA;
T est Circuit 1
VS = 0 V to VDD, IDS = 10 mA
12
0.1
0.5
3
On-Resistance Match between
Channels (∆RON
)
On-Resistance Flatness (RFLAT (ON)
)
VS = 0 V to VDD, IDS = 10 mA
LEAKAGE CURRENT S
VDD = 3.3 V
Source OFF Leakage IS (OFF)
±0.01
±0.1
±0.01
±0.1
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V;
T est Circuit 2
VS = VD = 1 V or 3 V;
T est Circuit 3
±0.3
±0.5
Channel ON Leakage ID, IS (ON)
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.005
4
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACT ERIST ICS2
tON
28
9
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS1A = 2 V, VS1B = 0 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 2 V, T est Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 2 V, T est Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 2 V, T est Circuit 6
VS = 1 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 7
55
16
60
16
1
tOFF
ADG786 tON (EN)
29
9
t
OFF(EN)
Break-Before-Make T ime Delay, tD
Charge Injection
22
±3
–72
–67
Off Isolation
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 9
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
160
11
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, T est Circuit 10
f = 1 MHz
CD, CS (ON)
34
pF typ
f = 1 MHz
POWER REQUIREMENT S
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
0.001
µA typ
1.0
µA max
NOT ES
1T emperature ranges are as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–3–
REV. 0
1
ADG786/ADG788–SPECIFICATIONS
(V = +2.5 V ꢁ 10%, V = –2.5 V ꢁ 10%, GND = 0 V, unless otherwise noted.)
DUAL SUPPLY
DD
SS
B Version
–40ꢃC
P aram eter
+25ꢃC
to +85ꢃC
Unit
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
VSS to VDD
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 10 mA;
T est Circuit 1
VS = VSS to VDD, IDS = 10 mA
5.0
0.1
0.4
On-Resistance Match between
Channels (∆RON
)
On-Resistance Flatness (RFLAT (ON)
)
0.5
VS = VSS to VDD, IDS = 10 mA
1.2
LEAKAGE CURRENT S
Source OFF Leakage IS (OFF)
VDD = +2.75 V, VSS = –2.75 V
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
T est Circuit 2
±0.01
±0.1
±0.01
±0.1
nA typ
nA max
nA typ
nA max
±0.3
±0.5
Channel ON Leakage ID, IS (ON)
VS = VD = +2.25 V/–1.25 V, T est Circuit 3
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.7
0.7
V min
V max
IINL or IINH
0.005
4
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACT ERIST ICS2
tON
21
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS1A = 1.5 V, VS1B = 0 V, T est Circuit 4
35
16
40
16
1
tOFF
10
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, T est Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, T est Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, T est Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 7
ADG786
t
t
ON(EN)
OFF(EN)
21
10
Break-Before-Make T ime Delay, tD
Charge Injection
13
±5
–72
–67
Off Isolation
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 9
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
160
11
34
MHz typ RL = 50 Ω, CL = 5 pF, T est Circuit 10
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENT S
IDD
VDD = +2.75 V
Digital Inputs = 0 V or 2.75 V
0.001
0.001
µA typ
µA max
µA typ
µA max
1.0
1.0
ISS
VSS = –2.75 V
Digital Inputs = 0 V or 2.75 V
NOT ES
1T emperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG786/ADG788
ABSO LUTE MAXIMUM RATINGS1
(T A = 25°C unless otherwise noted)
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
20 Lead CSP, θJA T hermal Impedance . . . . . . . . . . . 32°C/W
Lead T emperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow, Peak T emperature . . . . . . . . . . . . . . . . . . . 220°C
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Digital Inputs2 . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating T emperature Range
2Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG786/ADG788 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
ADG786BCP
ADG788BCP
–40°C to +85°C
–40°C to +85°C
Chip Scale Package (CSP)
Chip Scale Package (CSP)
CP-20
CP-20
P IN CO NFIGURATIO NS
20 19 18 17 16
20 19 18 17 16
PIN 1
PIN 1
IDENTIFIER
IDENTIFIER
S2A
S3B
D3
D1
1
2
3
4
5
15 D2
14 NC
13 D1
1
2
3
4
5
15 S4B
14
13 S3B
D3
S1B
V
DD
ADG786
TOP VIEW
(Not to Scale)
ADG788
TOP VIEW
(Not to Scale)
V
SS
S3A
EN
S1B
GND
S2B
12
12
11 S3A
11 S1A
6
7
8
9
10
6
7
8
9
10
NC = NO CONNECT
EXPOSED PAD TIEDTO SUBSTRATE,V
SS
REV. 0
–5–
ADG786/ADG788
Table II. AD G788 Truth Table
Table I. AD G786 Truth Table
Logic
Switch A
Switch B
A2
A1
A0
EN
O N Switch
0
1
OFF
ON
ON
OFF
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
None
D1-S1A, D2-S2A, D3-S3A
D1-S1B, D2-S2A, D3-S3A
D1-S1A, D2-S2B, D3-S3A
D1-S1B, D2-S2B, D3-S3A
D1-S1A, D2-S2A, D3-S3B
D1-S1B, D2-S2A, D3-S3B
D1-S1A, D2-S2B, D3-S3B
D1-S1B, D2-S2B, D3-S3B
TERMINO LO GY
VDD
VSS
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
IDD
Positive Supply Current
ISS
Negative Supply Current
GND
S
Ground (0 V) Reference
Source T erminal. May be an input or output
Drain T erminal. May be an input or output
Logic Control Input
D
IN
VD (VS)
RON
∆RON
Analog Voltage on T erminals D, S
Ohmic Resistance between D and S
On Resistance Match between Any T wo Channels, i.e., RONmax – RONmin.
RFLAT (ON)
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured
over the specified analog signal range.
IS (OFF)
ID, IS (ON)
VINL
Source Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Maximum Input Voltage for Logic “0”
VINH
Minimum Input Voltage for Logic “1”
I
INL(IINH
)
Input Current of the Digital Input
CS (OFF)
CD, CS(ON)
CIN
“OFF” Switch Source Capacitance. Measured with reference to ground.
“ON” Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance
tON
Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condition.
Delay time measured between the 50% and 90% points of the digital input and the switch “OFF” condition.
Delay time between the 50% and 90% points of the EN digital input and the switch “ON” condition.
Delay time between the 50% and 90% points of the EN digital input and the switch “OFF” condition.
“OFF” time measured between the 80% points of both switches when switching from one address state to another.
A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.
A measure of unwanted signal coupling through an “OFF” switch.
tOFF
t
t
ON(EN)
OFF(EN)
tOPEN
Charge
Off Isolation
Crosstalk
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
On Response
Insertion Loss
T he Frequency Response of the “ON” Switch
T he Loss Due to the ON Resistance of the Switch.
–6–
REV. 0
Typical Performance Characteristics–
ADG786/ADG788
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
T
V
= 25ꢃC
T
= 25ꢃC
V
= 5V
= 0V
A
A
DD
= 0V
V
SS
SS
V
= 2.7V
DD
V
= 3.3V
DD
V
V
= +2.5V
= –2.5V
DD
V
= 4.5V
DD
+25ꢃC
SS
+85ꢃC
–40ꢃC
1
V
= 5.5V
DD
0
1
2
3
4
5
–3
–2
–1
0
1
2
3
0
2
3
4
5
V
, V , DRAIN OR SOURCE VOLTAGE – V
S
V
, V , DRAIN OR SOURCE VOLTAGE – V
S
V
, V , DRAIN OR SOURCE VOLTAGE – V
S
D
D
D
TPC 2. On Resistance as a Function
of VD(VS) for Dual Supply
TPC 3. On Resistance as a Function
of VD(VS) for Different Temperatures,
Single Supply
TPC 1. On Resistance as a Function
of VD(VS) for Single Supply
8
8
0.10
V = 5V
DD
V
= +2.5V
= –2.5V
V
= 3V
= 0V
DD
DD
7
V
= GND
V
7
6
5
4
3
2
1
0
V
SS
SS
SS
T
= 25ꢃC
A
0.05
0
6
5
4
3
I , I (ON), V = V
S
D
D
S
+85ꢃC
+25ꢃC
+25ꢃC
+85ꢃC
–40ꢃC
–0.05
–0.10
–0.15
I
(OFF)
S
2
1
–40ꢃC
–2
0
–3
–1
0
1
2
3
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
, V , DRAIN OR SOURCE VOLTAGE – V
D
S
V , V , DRAIN OR SOURCE VOLTAGE – V
D S
V , (V = V –V ) – V
S
D
DD
S
TPC 6. Leakage Currents as a
Function of VD(VS)
TPC 4. On Resistance as a Function
of VD(VS) for Different Temperatures,
Single Supply
TPC 5. On Resistance as a Function
of VD(VS) for Different Temperatures
Dual Supply
,
0.10
0.15
0.10
0.05
0
0.25
V
= 3V
= GND
= 25ꢃC
V
= +2.5V
= –2.5V
= +2.25V/–1.25V
= –1.25V/+2.25V
V = 5V
DD
V
= +2.5V
= –2.5V
= 25ꢃC
DD
DD
DD
0.08
0.06
0.04
0.02
0
V
T
V
V
V
V
V
V
= GND
= 4.5V/1.0V
= 1.0V/4.5V
V
T
SS
SS
SS
SS
0.20
0.15
0.10
0.05
0
A
D
S
D
S
A
I , I (ON), V = V
S
D
D
S
I , I (ON), V = V
S
D
D
S
I , I (ON)
S
D
–0.02
–0.04
–0.06
–0.05
I
(OFF)
S
I
(OFF)
1.0
S
I
(OFF)
20
S
–0.10
–0.15
–0.05
–0.10
–0.08
–0.10
0
0.5
1.5
2.0
2.5
3.0
–3
–2
–1
0
1
2
3
5
35
50
65
80
V , (V = V –V ) – V
DD
V , (V = V –V ) – V
TEMPERATURE – ꢃC
S
D
S
S
D
DD
S
TPC 7. Leakage Currents as a
Function of VD(VS)
TPC 8. Leakage Currents as a
Function of VD(VS)
TPC 9. Leakage Currents as a
Function of Temperature
REV. 0
–7–
ADG786/ADG788
0
–2
0.25
0.20
0.15
0.10
40
35
V
= 3V
= GND
= 2.7V/1V
= 1V/2.7V
V
= GND
DD
SS
V
V
V
SS
D
S
V
= 5V
t
, V = 3V
DD
ON DD
–4
T
= 25ꢃC
30
25
20
15
10
A
–6
t
, V = 5V
ON DD
–8
0.05
I , I (ON)
–10
–12
–14
–16
S
D
0
t
, V = 3V
OFF DD
–0.05
–0.10
t
, V = 5V
OFF DD
5
0
I
(OFF)
20
S
5
35
50
65
80
–20
0
20
40
60
80
10k
100k
1M
10M
100M
FREQUENCY – HZ
TEMPERATURE – ꢃC
TEMPERATURE – ꢃC
TPC 10. Leakage Currents as a
Function of Temperature
TPC 11. tON /tOFF Times vs.
Temperature
TPC 12. On Response vs. Frequency
10m
0
–10
–20
–30
–40
–50
–60
–70
–80
0
V
= 5V
= 25ꢃC
T
= 25ꢃC
DD
V
= 5V
= 25ꢃC
A
DD
T
–10
–20
–30
–40
–50
–60
–70
–80
–90
A
T
A
1m
100ꢄ
10ꢄ
1ꢄ
V
= 5V
DD
V
= GND
SS
V
= +2.5V
= –2.5V
DD
V
SS
V
V
= 3V
= GND
SS
100n
DD
–90
–100
10n
0.1
1
10
100
1000
10000
30k 100k
1M
10M
100M
30k 100k
1M
10M
100M
FREQUENCY – kHz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 13. Input Current, IDD vs.
Switching Frequency
TPC 14. Off Isolation vs. Frequency
TPC 15. Crosstalk vs. Frequency
30
T = 25ꢃC
A
V
= +2.5V
DD
V
= –2.5V
SS
20
10
0
V
= 3V
= GND
DD
V
SS
V
= 5V
DD
V
= GND
SS
–10
–3 –2
–1
0
1
2
3
4
5
VOLTAGE – V
TPC 16. Charge Injection vs. Source
Voltage
–8–
REV. 0
ADG786/ADG788
Test Circuits
I
DS
V1
I
(ON)
A
D
I
(OFF)
A
S
S
D
S
D
S
D
NC
V
V
D
S
V
V
D
S
R
= V1/I
ON
DS
NC = NO CONNECT
Test Circuit 3. ID (ON)
Test Circuit 2. IS (OFF)
Test Circuit 1. On Resistance
V
DD
0.1ꢄF
V
DD
ADDRESS
DRIVE
50%
50%
S1B
S1A
VS1B
VS1A
V
OUT
D1
VS1A
C
R
300ꢀ
L
L
90%
90%
35pF
V
OUT
VS1B
IN/EN
t
t
VSS
GND
0.1ꢄF
OFF
ON
V
SS
Test Circuit 4. Switching Times, tON, tOFF
V
V
DD
SS
0.1ꢄF
3V
V
V
ENABLE
SS
S1A
S1B
DD
50%
50%
A2
A1
A0
DRIVE (V
)
IN
V
S
0V
t
(EN)
OFF
ADG786
V
O
0.9V
0.9V
0
0
V
EN
D1
O
C
35pF
R
300ꢀ
L
L
50ꢀ
OUTPUT
0V
V
IN
GND
t
(EN)
ON
Test Circuit 5. Enable Delay, tON (EN), tOFF (EN)
V
DD
0.1ꢄF
3V
V
DD
ADDRESS
V
S
SA
SB
ADDRESS*
0V
V
IN
50ꢀ
ADG786/
ADG788
V
S
D1
SS
V
OUT
C
35pF
R
300ꢀ
L
V
80%
L
80%
OUT
V
GND
0.1ꢄF
t
OPEN
V
SS
*A0, A1, A2 for ADG786, IN1-4 for ADG788
Test Circuit 6. Break-Before-Make Delay, tOPEN
REV. 0
–9–
ADG786/ADG788
V
V
V
DD
SS
V
DD
SS
3V
LOGIC
ADG786/
ADG788
INPUT (V
)
IN
0V
R
S
S
D
V
OUT
C
L
EN*
V
S
1nF
V
OUT
V
OUT
GND
Q
= C ꢂ V
OUT
L
V
IN
INJ
* IN1–4 for ADG734
Test Circuit 7. Charge Injection
V
V
V
SS
V
DD
DD
SS
0.1ꢄF
0.1ꢄF
0.1ꢄF
0.1ꢄF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
V
DD
SS
DD
SS
S
S
50ꢀ
50ꢀ
50ꢀ
IN
IN
V
S
V
S
D
D
V
V
OUT
OUT
V
V
IN
R
IN
R
L
L
50ꢀ
50ꢀ
GND
GND
V
WITH SWITCH
V
OUT
OUT
INSERTION LOSS = 20 LOG
OFF ISOLATION = 20 LOG
V
WITHOUT SWITCH
V
S
OUT
Test Circuit 10. Bandwidth
Test Circuit 8. OFF Isolation
V
V
DD
P ower Supply Sequencing
SS
0.1ꢄF
0.1ꢄF
When using CMOS devices, care must be taken to ensure cor-
rect power supply sequencing. Incorrect sequencing can result
in the device being subjected to stresses beyond those maximum
ratings listed in the data sheet. Digital and analog inputs should
be applied to the device after supplies and ground. In dual sup-
ply applications, if digital and analog inputs may be applied
prior to VDD and VSS supplies, the addition of a Schottky diode
connected between VSS and GND will ensure that the device
powers on correctly. For single supply applications, VSS should
be tied to GND as close to the device as possible.
NETWORK
ANALYZER
V
V
SS
DD
V
OUT
SA
SB
R
L
50ꢀ
D
R
50ꢀ
50ꢀ
IN
V
S
GND
CHANNEL-TO-CHANNEL
V
OUT
CROSSTALK = 20 LOG
V
S
Test Circuit 9. Channel-to-Channel Crosstalk
–10–
REV. 0
ADG786/ADG788
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Lead Chip Select P ackage
(CP -20)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.010 (0.25)
MIN
0.157 (4.0)
BSC SQ
0.017 (0.42)
0.009 (0.24)
16
15
20
1
PIN 1
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
0.089 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
INDICATOR
0.148 (3.75)
BSC SQ
TOP
VIEW
BOTTOM
VIEW
11
10
5
6
0.028 (0.70) MAX
0.026 (0.65) NOM
0.080 (2.00)
REF
12ꢃ MAX
0.035 (0.90) MAX
0.033 (0.85) NOM
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
SEATING
PLANE
0.020 (0.50)
BSC
0.008 (0.20)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. 0
–11–
–12–
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