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ADP2102YCPZ-1-R7 [ROCHESTER]

SWITCHING REGULATOR, 3000 kHz SWITCHING FREQ-MAX, QCC16, 3 X 3 MM, ROHS COMPLIANT, LFCSP-16;
ADP2102YCPZ-1-R7
型号： ADP2102YCPZ-1-R7
厂家： Rochester Electronics    Rochester Electronics
描述：

SWITCHING REGULATOR, 3000 kHz SWITCHING FREQ-MAX, QCC16, 3 X 3 MM, ROHS COMPLIANT, LFCSP-16

开关 控制器 开关式稳压器 开关式控制器 电源电路 开关式稳压器或控制器
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Low Duty Cycle, 600 mA, 3 MHz Synchronous  
Step-Down DC-to-DC Converter  
ADP2102  
FEATURES  
GENERAL DESCRIPTION  
Input voltage range: 2.7 V to 5.5 V  
600 mA maximum load current  
95% efficiency  
The ADP2102 is a synchronous step-down dc-to-dc converter  
that converts a 2.7 V to 5.5 V unregulated input voltage to a lower  
regulated output voltage with up to 95% efficiency and 1%  
accuracy. The low duty cycle capability of the ADP2102 is ideal for  
USB applications or 5 V systems that power up submicron subvolt  
processor cores. Its 3 MHz typical operating frequency and excel-  
lent transient response allow the use of small, low cost 1 μH  
inductors and 2.2 μF ceramic capacitors. At medium-to-high  
load currents, it uses a current mode, pseudofixed frequency pulse-  
width modulation to extend battery life. To ensure the longest  
battery life in portable applications, the ADP2102 has a power save  
mode (PSM) that reduces the switching frequency under light  
load conditions to significantly reduce quiescent current.  
Low duty cycle operation  
Only 3 tiny external ceramic components  
3 MHz typical operating frequency  
Fixed output voltage from 0.8 V to 1.875 V  
Adjustable output voltage up to 3.3 V  
0.01 μA shutdown supply current  
Automatic power save mode  
Internal synchronous rectifier  
Internal soft start  
Internal compensation  
Enable/shutdown logic input  
Undervoltage lockout  
Current limit protection  
Thermal shutdown  
The ADP2102 is available in both fixed and adjustable output  
voltage options with 600 mA maximum output current. The preset  
output voltage options voltage are 1.875 V, 1.8 V, 1.5 V, 1.375 V,  
1.25 V, 1.2 V, 1.0 V, and 0.8 V. The adjustable voltage option is  
available from 0.8 V to 3.3 V. The ADP2102 requires only three  
external components and consumes 0.01 μA in shutdown mode.  
Small 8-lead, 3 mm × 3 mm LFCSP package  
APPLICATIONS  
USB powered devices  
WLAN and gateways  
Point of loads  
The ADP2102 is available in an 8-lead LFCSP package and is  
specified for the −40 °C to +85 °C temperature range.  
Processor core power from 5 V  
Digital cameras  
PDAs and palmtop computers  
Portable media players, GPS  
TYPICAL PERFORMANCE CHARACTERISTICS  
TYPICAL APPLICATIONS CIRCUIT  
100  
V
= 1.375V  
OUT  
= 25°C  
V
= 2.7V  
= 3V  
IN  
T
A
95  
90  
85  
80  
75  
70  
65  
60  
V
INPUT VOLTAGE  
2.7V TO 5.5V  
OUTPUT VOLTAGE  
0.8V TO 1.875V  
IN  
L
V
LX  
IN  
1µH  
C
C
IN  
OUT  
2.2µF  
2.2µF  
V
= 4.2V  
ADP2102  
IN  
V
= 3.6V  
IN  
FORCED  
CCM  
MODE  
EN  
FB/OUT  
GND  
DCM/  
CCM  
ON  
OFF  
10  
100  
1000  
LOAD CURRENT (mA)  
Figure 1.  
Figure 2.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 
 
ADP2102  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Current Limit.............................................................................. 14  
Soft Start ...................................................................................... 15  
Enable........................................................................................... 15  
Undervoltage Lockout ............................................................... 15  
Thermal Shutdown .................................................................... 15  
Applications Information.............................................................. 16  
Inductor Selection...................................................................... 16  
Input Capacitor Selection.......................................................... 16  
Output Capacitor Selection....................................................... 16  
Typical Applications Circuits.................................................... 17  
Setting the Output Voltage........................................................ 19  
Efficiency Considerations ......................................................... 19  
Thermal Considerations............................................................ 20  
Design Example.......................................................................... 20  
Circuit Board Layout Recommendations ................................... 22  
Recommended Layout............................................................... 22  
Outline Dimensions....................................................................... 24  
Ordering Guide .......................................................................... 24  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Typical Performance Characteristics ............................................. 1  
Typical Applications Circuit............................................................ 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Absolute Maximum Ratings............................................................ 4  
Thermal Resistance ...................................................................... 4  
Boundary Condition.................................................................... 4  
ESD Caution.................................................................................. 4  
Pin Configuration and Function Descriptions............................. 5  
Typical Performance Characteristics ............................................. 6  
Theory of Operation ...................................................................... 13  
Control Scheme .......................................................................... 13  
Constant On-Time Timer ......................................................... 13  
Forced Continuous Conduction Mode ................................... 13  
Power Save Mode........................................................................ 13  
Synchronous Rectification ........................................................ 14  
REVISION HISTORY  
6/07—Rev. 0 to Rev. A  
9/07—Rev. A to Rev. B  
Changes to Ordering Guide.......................................................... 23  
Changes to Features, Applications, and General Description.... 1  
Changes to Table 4............................................................................ 5  
Changes to Table 6.......................................................................... 17  
Changes to Table 7.......................................................................... 19  
Changes to Circuit Board Layout Recommendations Section.... 21  
Updated Outline Dimensions....................................................... 23  
Changes to Ordering Guide .......................................................... 23  
6/07—Revision 0: Initial Version  
Rev. B | Page 2 of 24  
 
ADP2102  
SPECIFICATIONS  
VIN = 3.6 V, EN = VIN, MODE = VIN, TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TA ≤ +85°C.1  
Table 1.  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
INPUT CHARACTERISTICS  
Input Voltage Range2  
Undervoltage Lockout Threshold  
Undervoltage Lockout Hysteresis  
OUTPUT CHARACTERISTICS  
Output Voltage Range  
2.7  
2.2  
5.5  
2.5  
V
V
mV  
VIN rising  
2.4  
220  
ADP2102-xx  
ADP2102-ADJ  
ADP2102-xx, TA= 25°C, ILOAD = 0 mA  
ADP2102-xx, −40°C ≤TA ≤ 85°C, ILOAD = 0 mA  
VOUT = 0.8 V to 1.875 V, ILOAD = 0 mA to 600 mA  
VIN = 2.7 V to 5.5 V, ILOAD = 10 mA  
0.8  
0.8  
−1  
−2  
1.875  
3.3  
+1  
V
V
%
%
%
%
Output Voltage Range  
Output Voltage Initial Accuracy  
+2  
Load Regulation  
Line Regulation  
0.5  
0.3  
FEEDBACK CHARACTERISTICS  
FB Regulation Voltage  
FB Bias Current  
ADP2102-ADJ  
ADP2102-ADJ, ADP2102-0.8  
ADP2102-xx  
800  
375  
mV  
nA  
kΩ  
784  
816  
50  
FB Impedance  
CURRENT CHARACTERISTICS  
Operating Current  
Shutdown Current  
ADP2102 PSM mode, ILOAD = 0 mA  
EN = 0 V  
ADP2102, VIN = 2.7 V to 5.5 V  
70  
0.01  
μA  
μA  
mA  
99  
1
600  
Output Current  
LX (SWITCH NODE) CHARACTERISTICS  
LX On Resistance  
P-channel switch, ILX = 100 mA  
N-channel synchronous rectifier, ILX = 100 mA  
VIN = 5.5 V, VLX = 0 V, 5.5 V  
ADP2102-xx, ADP2102-ADJ  
ADP2102-0.8  
ADP2102-1.0  
ADP2102-1.2  
ADP2102-1.25  
ADP2102-1.375  
ADP2102-1.5  
ADP2102-1.8  
ADP2102-1.875  
ADP2102-ADJ-1.2  
ADP2102-ADJ-1.5  
ADP2102-ADJ-1.875  
ADP2102-ADJ-3.3 (VIN = 5 V)  
325  
200  
mΩ  
mΩ  
μA  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A
600  
400  
1
LX Leakage Current  
LX Minimum Off-Time  
LX On-Time  
100  
87  
55  
70  
105  
135  
160  
169  
195  
210  
260  
270  
170  
210  
275  
270  
107  
131  
133  
165  
182  
220  
237  
131  
177  
226  
238  
1
100  
103  
135  
150  
180  
190  
80  
155  
200  
198  
Valley Current Limit  
ENABLE, MODE CHARACTERISTICS  
EN, MODE Input High Threshold  
EN, MODE Input Low Threshold  
EN, MODE Input Leakage Current  
SOFT START PERIOD  
V
V
μA  
μs  
1.3  
0.4  
1
VIN = 5.5 V, EN = MODE = 0 V, 5.5 V  
500  
250  
800  
THERMAL CHARACTERISTICS  
Thermal Shutdown Threshold  
Thermal Shutdown Hysteresis  
150  
15  
°C  
°C  
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).  
2 The input voltage (VIN) range over which the rest of the specifications are valid. The part operates as expected until VIN goes below the UVLO threshold.  
Rev. B | Page 3 of 24  
 
 
ADP2102  
ABSOLUTE MAXIMUM RATINGS  
THERMAL RESISTANCE  
Table 2.  
Junction-to-ambient thermal resistance (θJA) of the package is  
based on modeling and calculation using a 4-layer board. The  
junction-to-ambient thermal resistance is highly dependent on  
the application and board layout. In applications where high  
maximum power dissipation exists, attention to thermal board  
design is required. The value of θJA may vary, depending on PCB  
material, layout, and environmental conditions. Specified value  
of θJA is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board,  
as per JEDEC standards. For more information, see Application  
Note AN-772, A Design and Manufacturing Guide for the Lead  
Frame Chip Scale Package (LFCSP).  
Parameter  
Rating  
AVIN, EN, MODE, FB/OUT to AGND  
LX to PGND  
PVIN to PGND  
PGND to AGND  
AVIN to PVIN  
Operating Ambient Temperature Range  
Junction Temperature Range  
Storage Temperature Range  
Soldering Conditions  
−0.3 V to +6 V  
−0.3 V to (VIN + 0.3 V)  
−0.3 V to +6 V  
−0.3 V to +0.3 V  
−0.3 V to +0.3 V  
−40°C to +85°C1  
−40°C to +125°C  
−65°C to +150°C  
JEDEC J-STD-020  
1 The ADP2102 can be damaged when junction temperature limits are exceeded.  
Monitoring ambient temperature does not guarantee that TJ is within the  
specified temperature limits. In applications where high power dissipation  
and poor thermal resistance are present, the maximum ambient temperature  
may have to be derated. In applications with moderate power dissipation  
and low PCB thermal resistance, the maximum ambient temperature can  
exceed the maximum limit as long as the junction temperature is within  
specification limits. The junction temperature (TJ) of the device is dependent  
on the ambient temperature (TA), the power dissipation of the device (PD),  
and the junction-to-ambient thermal resistance of the package (θJA). Maximum  
junction temperature (TJ) is calculated from the ambient temperature (TA)  
and power dissipation (PD) using the formula TJ = TA + (θJA × PD). Unless  
otherwise specified, all other voltages are referenced to AGND.  
Table 3. Thermal Resistance  
Package Type  
θJA  
54  
0.74  
Unit  
°C/W  
W
8-Lead LFCSP  
Maximum Power Dissipation  
BOUNDARY CONDITION  
Natural convection, 4-layer board, exposed pad soldered to PCB.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
ESD CAUTION  
Rev. B | Page 4 of 24  
 
 
ADP2102  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
MODE  
1
2
3
4
8
7
6
5
AVIN  
PVIN  
LX  
EN  
ADP2102  
TOP VIEW  
(Not to Scale)  
FB/OUT  
AGND  
PGND  
Figure 3. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin  
No.  
Mnemonic Description  
1
MODE  
Mode Input. To set the ADP2102 to forced continuous conduction mode (CCM), drive MODE high. To set the ADP2102  
to power save mode/auto mode (PSM), drive MODE low.  
2
3
EN  
Enable Input. Drive EN high to turn on the ADP2102. Drive EN low to turn it off and reduce the input current to 0.1 μA.  
This pin cannot be left floating.  
Output Sense Input or Feedback Input. For fixed output versions, OUT is the top of the internal resistive voltage  
divider. Connect OUT to the output voltage. For adjustable (no suffix) versions, FB is the input to the error amplifier.  
Drive FB through a resistive voltage divider to set the output voltage. The FB regulation threshold is 0.8 V.  
FB/OUT  
4
AGND  
Analog Ground. Connect AGND to PGND at a single point as close to the ADP2102 as possible. The exposed paddle is  
electrically common with the analog ground pin.  
5
6
PGND  
LX  
Power Ground.  
Switch Output. LX is the drain of the P-channel MOSFET switch and the N-channel synchronous rectifier. Connect the  
output LC filter between LX and the output voltage.  
7
8
PVIN  
AVIN  
Power Source Input. Drive PVIN with a 2.7 V to 5.5 V power source. A ceramic bypass capacitor of 2.2 μF or greater is  
required on this pin to the nearest PGND plane.  
Power Source Input. AVIN is the supply for the ADP2102 internal circuitry. This pin can be connected in three different ways.  
For noise reduction, place an external RC filter between PVIN and AVIN. The recommended values for the  
external RC filter are 10 Ω and 0.1 μF, respectively. This configuration can be used for all loads.  
For light-to-medium loads up to 300 mA, the AVIN pin and the PVIN pin can be shorted together.  
For light-to-heavy loads (greater than 300 mA), bypass the AVIN pin with a 1 pF to 0.01 μF capacitor to the  
nearest PGND plane. Do not short the AVIN and PVIN pins when using only a bypass capacitor.  
Rev. B | Page 5 of 24  
 
ADP2102  
TYPICAL PERFORMANCE CHARACTERISTICS  
VIN = 3.6 V, L = 2.2 μH, CIN = 2.2 μF, COUT = 4.7 μF, unless otherwise noted.  
100  
1.22  
1.21  
1.20  
1.19  
1.18  
T
= 25°C  
T
= 25°C  
A
A
95  
90  
85  
80  
75  
70  
65  
60  
V
= 2.7V  
IN  
V
= 2.7V  
IN  
V
= 3.6V  
V
= 4.5V  
IN  
IN  
V
= 3.6V  
IN  
V
= 4.5V  
MODE = PSM  
L = 2.2µH  
IN  
C
C
= 2.2µF  
IN  
= 10µF  
OUT  
1
10  
100  
1000  
0
100  
200  
300  
400  
500  
600  
LOAD CURRENT (mA)  
LOAD CURRENT (mA)  
Figure 4. Efficiency vs. Load Current (VOUT = 1.2 V)  
Figure 7. Output Voltage Accuracy (VOUT = 1.2 V)  
100  
95  
90  
85  
80  
75  
70  
65  
60  
1.52  
1.51  
1.50  
1.49  
1.48  
T
= 25°C  
A
T
= 25°C  
A
V
= 2.7V  
IN  
V
= 3.6V  
IN  
V
= 2.7V  
IN  
V
= 4.5V  
IN  
V
= 3.6V  
IN  
MODE = PSM  
L = 2.2µH  
V
= 4.5V  
IN  
C
C
= 2.2µF  
IN  
= 10µF  
OUT  
1
10  
100  
1000  
0
100  
200  
300  
400  
500  
600  
LOAD CURRENT (mA)  
LOAD CURRENT (mA)  
Figure 5. Efficiency vs. Load Current (VOUT = 1.5 V)  
Figure 8. Output Voltage Accuracy (VOUT = 1.5 V)  
100  
95  
90  
85  
80  
75  
70  
65  
60  
1.82  
1.81  
1.80  
1.79  
1.78  
T
= 25°C  
A
T
= 25°C  
A
V
IN  
= 2.7V  
V
= 2.7V  
IN  
V
= 4.5V  
IN  
V
= 3.6V  
IN  
V
= 3.6V  
IN  
MODE = PSM  
L = 2.2µH  
V
= 4.5V  
IN  
C
C
= 2.2µF  
IN  
= 10µF  
OUT  
1
10  
100  
1000  
0
100  
200  
300  
400  
500  
600  
LOAD CURRENT (mA)  
LOAD CURRENT (mA)  
Figure 6. Efficiency vs. Load Current (VOUT = 1.8 V)  
Figure 9. Output Voltage Accuracy (VOUT = 1.8 V)  
Rev. B | Page 6 of 24  
 
 
ADP2102  
100  
95  
1.53  
1.52  
1.51  
1.50  
1.49  
1.48  
T
= 25°C  
FF  
A
T
= 25°C  
A
C
= 6.8pF  
V
= 4.5V  
IN  
PSM  
V
V
= 5.0V  
= 5.5V  
IN  
IN  
90  
CCM  
85  
MODE = PSM  
1000  
80  
1
10  
100  
0
100  
200  
300  
400  
500  
600  
LOAD CURRENT (mA)  
LOAD CURRENT (mA)  
Figure 10. Efficiency vs. Load Current (VOUT = 3.3 V)  
Figure 13. Output Voltage vs. Load Current (VOUT = 1.5 V)  
1.84  
1.83  
1.82  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
T
= 25°C  
A
T
= 25°C  
A
PSM  
PSM  
1.81  
1.80  
1.79  
1.78  
CCM  
CCM  
10  
100  
1k  
0
100  
200  
300  
400  
500  
600  
LOAD CURRENT (mA)  
LOAD CURRENT (mA)  
Figure 11. PSM vs. CCM Efficiency (VOUT = 1.8 V)  
Figure 14. Output Voltage vs. Load Current (VOUT = 1.8 V)  
1.22  
1.23  
T
= 25°C  
A
1.22  
1.21  
1.20  
1.19  
1.18  
I
= 0mA  
LOAD  
1.21  
1.20  
1.19  
1.18  
PSM  
I
= 300mA  
LOAD  
I
= 600mA  
LOAD  
CCM  
–45  
–25  
–5  
15  
35  
55  
75  
0
100  
200  
300  
400  
500  
600  
TEMPERATURE (°C)  
LOAD CURRENT (mA)  
Figure 12. Output Voltage vs. Load Current (VOUT = 1.2 V)  
Figure 15. Output Voltage vs. Temperature (VOUT = 1.2 V)  
Rev. B | Page 7 of 24  
ADP2102  
1.52  
85  
80  
+85°C  
1.51  
1.50  
+25°C  
I
= 0mA  
LOAD  
75  
70  
65  
60  
I
= 300mA  
LOAD  
1.49  
1.48  
1.47  
1.46  
–40°C  
I
= 600mA  
LOAD  
2.7  
3.0  
3.3  
3.6  
3.9  
4.2  
4.5  
4.8  
5.1  
5.4  
–40  
–15  
10  
35  
60  
85  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
Figure 16. Output Voltage vs. Temperature (VOUT = 1.5 V)  
Figure 19. Quiescent Current vs. Input Voltage  
1.81  
1.80  
1.79  
1.78  
1.77  
1.76  
77  
76  
75  
I
= 0mA  
LOAD  
I
I
= 300mA  
LOAD  
74  
73  
72  
71  
70  
= 600mA  
LOAD  
–40  
–15  
10  
35  
60  
85  
–40  
–20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 17. Output Voltage vs. Temperature (VOUT = 1.8 V)  
Figure 20. Quiescent Current vs. Temperature  
3.40  
0.8005  
V
= 3.6V  
IN  
0.8000  
0.7995  
0.7990  
0.7985  
3.36  
3.32  
3.28  
3.24  
3.20  
+85°C  
+25°C  
0.7980  
0.7975  
0.7970  
0.7965  
–40°C  
0
100  
200  
300  
400  
500  
600  
–50  
0
50  
100  
LOAD CURRENT (mA)  
TEMPERATURE (°C)  
Figure 18. Output Voltage Accuracy (VOUT = 3.3 V)  
Figure 21. Feedback Voltage vs. Temperature  
Rev. B | Page 8 of 24  
ADP2102  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
400  
350  
300  
250  
200  
150  
100  
50  
T
= 25°C  
A
PMOS SWITCH  
1.25V  
1.2V  
1V  
0.8V  
NMOS SWITCH  
1.375V  
500  
1.5V  
1.8V  
1.875V  
0
–40  
0
100  
200  
300  
400  
600  
–20  
0
20  
40  
60  
80  
100  
120  
LOAD CURRENT (mA)  
TEMPERATURE (°C)  
Figure 22. Switching Frequency vs. Load Current  
Figure 25. Switch On Resistance vs. Temperature  
1.08  
1.07  
1.06  
1.05  
T
T
= 25°C  
T
= 25°C  
A
A
CH4: LX  
4
1.04  
1.03  
1.02  
CH1: IL  
1
2
CH2: V  
OUT  
1.01  
1.00  
B
B
B
2.7  
3.0  
3.3  
3.6  
3.9  
4.2  
4.5  
4.8  
5.1  
5.4  
5.7  
CH1 500mA Ω  
W
CH2 2.00V  
CH4 2.00V  
W
M 1.00µs  
51.00%  
A
CH4  
2.76V  
W
INPUT VOLTAGE (V)  
T
Figure 23. Valley Current Limit  
Figure 26. PSM Mode Operation at Very Light Loads (10 mA)  
400  
350  
300  
250  
200  
T
T
= 25°C  
PSM  
T
= 25°C  
A
A
PSM  
CCM  
CH1: V  
OUT  
PMOS SWITCH  
NMOS SWITCH  
1
150  
100  
50  
CH3: IL  
3
0
2.7  
B
B
3.0  
3.3  
3.6  
3.9  
4.2  
4.5  
4.8  
5.1  
5.4  
CH1 50.0mV  
CH3 50.0mA Ω  
W
M 100µs A CH3  
86.0mA  
W
INPUT VOLTAGE (V)  
Figure 24. Switch On Resistance vs. Input Voltage  
Figure 27. PSM Mode Entry—Exit Operation (10 mA to 50 mA to 10 mA)  
Rev. B | Page 9 of 24  
 
 
ADP2102  
180  
160  
140  
120  
100  
80  
T
T
= 25°C  
A
T
= 25°C  
A
V
= 1.5V  
CH4: LX  
OUT  
V
= 1.375V  
OUT  
4
CH1: IL  
1
2
60  
CH2: V  
OUT  
40  
20  
L = 2.2µH  
5.0 5.5  
0
B
B
CH1 500mA Ω  
W
CH2 2.00V  
CH4 2.00V  
W
M 10.0µs  
T 51.00%  
A CH4  
2.72V  
2.5  
3.0  
3.5  
4.0  
4.5  
B
W
INPUT VOLTAGE (V)  
Figure 28. PSM Mode Operation at Light Loads (75 mA)  
Figure 31. Typical PSM Threshold vs. Input Voltage  
T
T
T
= 25°C  
T = 25°C  
A
A
CH1: IL  
CH1: V  
(AC)  
OUT  
1
CH3: LX  
1
3
4
CH4: V  
OUT  
CH2: I  
(0mA TO 300mA)  
LOAD  
2
B
B
B
W
CH1 200mA Ω  
CH3 2.00V  
W
M 200ns A CH1  
388mA  
CH1 50.0mV  
CH2 200mA Ω M 100µs  
23.60%  
A
CH2  
220mA  
B
W
W
CH4 2.00V  
T
T
–4.00000ns  
Figure 29. CCM Mode Operation at Medium/Heavy Loads (0.3 A)  
Figure 32. Load Transient Response (VOUT = 1.2 V)  
T
V
V
= 3.6V  
T
IN  
T
= 25°C  
A
T
= 25°C  
A
= 1.5V  
OUT  
I
= 0mA - 75mA - 0mA  
LOAD  
CH1: LX  
CH1: V  
(AC)  
OUT  
1
1
CH3: V  
OUT  
75mA  
3
2
CH2: IL  
0mA  
CH2: I  
(0mA TO 300mA)  
LOAD  
2
0mA  
B
B
CH1 2.00V  
CH3 1.00V  
W
CH2 100mA Ω M 200µs A CH2  
82.0mA  
B
CH1 50.0mV  
W
CH2 200mA Ω M 100µs A CH2  
236mA  
W
Figure 30. Light Load Behavior  
Figure 33. Load Transient Response (VOUT = 1.5 V)  
Rev. B | Page 10 of 24  
ADP2102  
T
T
T
= 25°C  
T
= 25°C  
A
A
CH1: V  
(AC)  
OUT  
1
CH1: V  
(AC)  
OUT  
1
CH3: V (3.6V TO 4.2V STEP)  
IN  
CH2: I  
(0mA TO 300mA)  
LOAD  
2
3
B
B
B
CH1 50.0mV  
W
CH2 200mA Ω M 100µs A CH2  
–300.000µs  
264mA  
CH1 50.0mV  
CH3 1.00V  
W
M 40.0µs A CH3  
3.70V  
W
T
Figure 34. Load Transient Response (VOUT = 1.8 V)  
Figure 37. Line Transient Response (VOUT = 1.8 V)  
T
T
T
= 25°C  
T
= 25°C  
A
A
CH4: EN  
CH1: V  
(AC)  
OUT  
1
4
1
CH1: LX  
CH3: V (3V TO 4V STEP)  
IN  
CH2: V  
OUT  
2
3
B
B
B
B
B
CH1 50.0mV  
CH3 1.00V  
W
M 200µs  
A CH3  
3.74V  
W
W
CH1 200mA Ω  
CH2 1.00V  
CH4 2.00V  
M 20.0ms A CH3  
14.60%  
2.00V  
W
W
T
Figure 35. Line Transient Response (VOUT = 1.2 V)  
Figure 38. Start-Up and Shutdown Waveform  
T
T
T
= 25°C  
T
= 25°C  
A
A
CH1: V  
IN  
CH1: V  
(AC)  
OUT  
1
1
2
CH2: V  
OUT  
CH3: V (3V TO 4V STEP)  
IN  
CH3: LX  
3
3
B
B
B
B
W
CH1 50.0mV  
CH3 1.00V  
W
M 100µs  
A CH3  
3.72V  
CH1 2.00V  
CH3 200mA Ω  
W
CH2 500mV  
M 400µs  
27.60%  
A CH1  
1.40V  
B
W
W
T
Figure 36. Line Transient Response (VOUT = 1.5 V)  
Figure 39. Light Load Start-Up Waveform  
Rev. B | Page 11 of 24  
ADP2102  
T
T
= 25°C  
T = 25°C  
A
A
CH1: LX  
CH1: EN  
1
3
1
2
3
CH2: V  
OUT  
CH2: V  
OUT  
CH4: IL  
CH3: IL  
4
B
B
B
B
W
W
M 1.00s  
A CH3  
440mV  
CH1 2.00V  
CH3 200mA Ω  
W
CH2 500mV  
W
M 2.00ms A CH2  
6.600%  
350mV  
CH1 5.00V  
CH3 1.00V  
B
B
W
W
CH4 500mA Ω  
T
Figure 40. Heavy Load Start-Up Waveform  
Figure 42. Short-Circuit Response at Output  
T
T
V
V
C
= 3.6V  
IN  
T
A
= 25°C  
T
= 25°C  
A
= 1.375V  
= 4.7µF  
OUT  
CH4: V  
(AC)  
OUT  
OUT  
I
= 100mA  
LOAD  
4
CH4: V  
OUT  
L = 2.2µH  
4
3
C
C
= 2.2µF  
IN  
= 4.7µF  
OUT  
CH1: LX  
CH3: IL  
1
B
CH1 2.00V  
W
M 2.00µs  
A CH1  
4.20V  
M 100µs A CH4  
680mV  
B
B
B
W
CH4 20.00mV  
W
W
CH3 200mA Ω CH4 500mV  
T
51.00%  
T 43.40%  
Figure 41. PSM Mode Ripple (VIN = 3.6 V, Load = 50 mA)  
Figure 43. Soft Start Waveform  
Rev. B | Page 12 of 24  
ADP2102  
THEORY OF OPERATION  
The ADP2102 is a high frequency, synchronous step-down,  
dc-to-dc converter optimized for battery-powered, portable  
applications. It is based on constant on-time current-mode  
control architecture with voltage feed forward to null frequency  
variation with line voltage, creating a pseudofixed frequency.  
Equating Equation 1 and Equation 2 gives  
SW = 1/K  
f
(3)  
where K is an internally set on-time scale factor constant resulting  
in a constant switching frequency.  
As shown in Equation 1, the steady state switching frequency  
is theoretically independent of both the input and output voltages  
to a first order. This means the loop switches at a nearly constant  
frequency until a load step occurs.  
This type of control allows generation of very low output voltages  
at a higher switching frequency and offers a very fast load and  
line transient response with minimal external component count  
and size. The ADP2102 provides features such as undervoltage  
lockout, thermal shutdown, and short-circuit protection.  
When a load step occurs, the constant on-time control loop  
responds by modulating the off time up or down to quickly  
return to regulation. This momentary frequency variation  
results in a faster load transient response than a fixed frequency  
current-mode control loop of similar bandwidth with a similar  
external filter inductor and capacitor. This is an advantage of  
a constant on-time control scheme.  
The ADP2102 uses valley current-mode control, which helps to  
prevent minimum on-time limitations at very low output voltages.  
This allows high frequency operation, resulting in low filter  
inductor and capacitor values.  
CONTROL SCHEME  
The ADP2102 high-side power switch on-time is determined by  
a one-shot timer whose pulse width is directly proportional to  
the output voltage and inversely proportional to the input or  
line voltage. Another one-shot timer sets a minimum off time to  
allow for inductor valley current sensing.  
Resistive voltage losses in the high-side and low-side power  
switches, package parasitics, inductor DCR, and board parasitic  
resistance cause the loop to compensate by reducing the off time  
and, therefore, increase the switching frequency with increasing  
load current.  
The constant on-time, one-shot timer is triggered at the rising  
edge of EN and, subsequently, when the low-side power switch  
current is below the valley current limit threshold and the  
minimum off-time one-shot timer has timed out.  
A minimum off-time constraint is introduced to allow inductor  
valley current sensing on the synchronous switch.  
FORCED CONTINUOUS CONDUCTION MODE  
When the MODE pin is high, the ADP2102 operates in forced  
continuous conduction mode (CCM). In this mode, irrespective  
of the load current, the inductor current stays continuous, and  
CCM is the preferred mode of operation for low noise applications.  
During this mode, the switching frequency stays close to 3 MHz  
typical. In this mode, efficiency is lower at light loads, compared to  
the power save mode, but the output voltage ripple is minimized.  
While the constant on-time is asserted, the high-side power  
switch is turned on. This causes the inductor current to ramp  
positively. After the constant on-time has completed, the high-  
side power switch turns off and the low-side power switch turns  
on. This causes the inductor current to ramp negatively until  
the sensed current flowing in this switch has reached valley  
current limit. At this point, the low-side power switch turns off  
and a new cycle begins with the high-side switch turning on,  
provided that the minimum off-time one shot has timed out.  
POWER SAVE MODE  
When the MODE pin is low, the ADP2102 operates in power  
save mode (PSM). In this mode, at light load currents, the part  
automatically goes into reduced frequency operation where  
some pulses are skipped to increase efficiency while remaining  
in regulation. At light loads, a zero-crossing comparator  
truncates the low-side switch on-time when the inductor  
current becomes negative. In this condition, the part works in  
discontinuous conduction mode (DCM). The threshold between  
CCM and DCM is approximately  
CONSTANT ON-TIME TIMER  
The constant on-time timer sets the high-side switch on-time.  
This fast, low jitter, adjustable one shot varies the on-time in  
response to input voltage for a given output voltage. The high-  
side switch on-time is inversely proportional to the input  
voltage and directly proportional to the output voltage.  
t
ON = K(VOUT/VIN)  
(1)  
The duty cycle for a buck converter operating in continuous  
conduction mode (CCM) is given by D = VOUT/VIN and, by  
definition, D = tON/(tON + tOFF). Therefore, equating the duty cycle  
(VIN − VOUT ) ×VOUT  
2 × L ×VIN × fSW  
I
LOAD (skip) =  
(4)  
terms of VOUT/VIN and tON/(tON + tOFF) gives  
There is a first-order dependency of this threshold on the internally  
set on-time scale factor indicated in Equation 3. For higher load  
currents, the inductor current does not cross zero threshold. The  
device switches to the continuous conduction mode, and the  
frequency is fixed to the nominal value.  
tON = VOUT/(VIN × fSW)  
(2)  
Rev. B | Page 13 of 24  
 
ADP2102  
As a result of this auto mode control technique, losses are  
minimized at light loads, improving system efficiency.  
When the load current is further increased such that the lower  
peak is above the current limit threshold, the off time is lengthened  
to allow the current to decrease to this threshold before the next  
on-time begins.  
The PSM reverse current comparator controls the entry and exit  
into forced continuous conduction mode. Some minor jitter is  
normal during transition from DCM to CCM with loads at  
approximately 100 mA typical, and it has no adverse impact on  
regulation.  
Both VOUT and the switching frequency are reduced as the circuit  
operates in constant current mode. The load current (IOCL) under  
these conditions is equal to the current limit threshold plus half  
the ripple current, as shown in Equation 5 and in Figure 44.  
SYNCHRONOUS RECTIFICATION  
I
OCL = IVALLEY + ΔIL/2  
(5)  
In addition to the P-channel MOSFET switch, the ADP2102  
includes an integrated N-channel MOSFET synchronous recti-  
fier. The synchronous rectifier improves efficiency, especially  
at low output voltages, and reduces cost and board space by  
eliminating the need for an external rectifier.  
DC CURRENT LIMIT = MAX LOAD  
I
CURRENT LIMIT  
OCL  
INDUCTOR  
CURRENT  
ΔI  
The current limit circuit employs a valley current sensing scheme.  
Current limit detection occurs during the off time through  
sensing of the voltage drop across the on resistance of the  
synchronous rectifier switch. The detection threshold is 1 A  
typical.  
VALLEY CURRENT LIMIT  
TIME  
Figure 44. Valley Current Limit  
Figure 45 illustrates the inductor current waveform during normal  
The ripple current is calculated using Equation 6.  
operation and during current limit. The output current, IOUT  
is the average of the inductor ripple current waveform. The  
,
VOUT ×(VIN −VOUT  
VIN × fSW × L  
)
ΔIL =  
(6)  
low-to-medium load current waveform illustrates the continuous  
conduction mode operation with peak and valley inductor  
currents below the current limit threshold. When the load  
current is increased, the ripple waveform maintains the same  
amplitude and frequency because the current falls below the  
current limit threshold at the valley of the ripple waveform.  
As the current falls below the threshold during the normal off-  
time of each cycle, the start of each on-time is not delayed, and  
the circuit output voltage is regulated at the correct value.  
The ADP2102 also provides a negative current limit to prevent  
an excessive reverse inductor current when the switching section  
sinks current from the load in forced continuous conduction  
mode. Under negative current limit conditions, both the high-  
side and low-side switches are disabled.  
I
PEAK  
I
OCL  
CURRENT LIMIT  
THRESHOLD  
I
VALLEY  
I
OUT  
INDUCTOR  
CURRENT  
ΔI  
MEDIUM LOAD  
CURRENT  
HIGH LOAD  
CURRENT  
CURRENT LIMIT  
NORMAL OPERATION  
Figure 45. Inductor Current—Current Limit Operation  
Rev. B | Page 14 of 24  
 
 
 
ADP2102  
SOFT START  
UNDERVOLTAGE LOCKOUT  
The ADP2102 has an internal soft start function that ramps the  
output voltage in a controlled manner upon startup, therefore  
limiting the inrush current. This prevents possible input voltage  
drops when a battery or a high impedance power source is  
connected to the input of the converter.  
The undervoltage lockout circuit prevents the device from  
operating incorrectly at low input voltages. It prevents the  
converter from turning on the main switch and the synchronous  
switch under undefined conditions and, therefore, prevents  
deep discharge of the battery supply.  
ENABLE  
THERMAL SHUTDOWN  
The device starts operation with soft start when the EN pin is  
toggled from logic low to logic high. Pulling the EN pin low  
forces the device into shutdown mode, with a typical shutdown  
current of 0.01 μA. In shutdown mode, both the high-side and  
low-side power switches are turned off, the internal resistor feed-  
back divider is disconnected, and the entire control circuitry is  
switched off. For proper operation, the device is in shutdown  
mode when voltage applied to this pin is less than 0.4 V and  
enabled when voltage applied is greater than 1.3 V. This pin  
must not be left floating.  
When the junction temperature, TJ, exceeds 150°C typical,  
the device goes into thermal shutdown. In this mode, the high-  
side and low-side power switches are off. The device resumes  
operation when the junction temperature again falls below  
135°C typical.  
AVIN  
8
MODE  
1
PVIN  
7
THERMAL  
UVLO  
SHUTDOWN  
BANDGAP  
REFERENCE  
MIN OFF-TIMER  
2
EN  
NON-  
OVERLAPPING  
DRIVERS  
S
R
RISE-  
DETECT  
Q
6
LX  
ON-TIME TIMER  
REGULATION  
COMPARATOR  
3
FB/OUT  
R
R
5
PGND  
ERROR  
AMPLIFIER  
CURRENT SENSE  
AMPLIFIER  
4
AGND  
INTERNAL  
COMPENSATION  
REVERSE CURRENT  
COMPARATOR  
FIXED  
ADJUSTABLE  
Figure 46. Internal Block Diagram  
Rev. B | Page 15 of 24  
 
ADP2102  
APPLICATIONS INFORMATION  
In principle, different types of capacitors can be considered, but  
for battery-powered applications, the best choice is a multilayer  
ceramic capacitor, due to its small size and equivalent series  
resistance (ESR).  
The external component selection for the ADP2102 applications  
circuit, as shown in Figure 2, is driven by the load requirement  
and begins with the selection of Inductor L. Once the inductor  
is chosen, CIN and COUT can be selected.  
It is recommended that the PVIN pin be bypassed with a 2.2 μF  
or larger ceramic input capacitor. The size of the input capacitor  
can be increased without any limit for better input voltage filtering.  
X5R or X7R dielectrics are recommended, with a voltage rating of  
6.3 V or 10 V. Y5U and Z5U dielectrics are not recommended,  
due to their poor temperature and dc bias characteristics.  
INDUCTOR SELECTION  
The high switching frequency of the ADP2102 allows for minimal  
output voltage ripple, even with small inductors. Inductor sizing  
is a trade-off between efficiency and transient response. A small  
inductor leads to a larger inductor current ripple that provides  
excellent transient response but degrades efficiency. Due to the  
high switching frequency of the ADP2102, multilayer ceramic  
inductors can be used for an overall smaller solution size. Shielded  
ferrite core inductors are recommended for their low core losses  
and low electromagnetic interference (EMI).  
In applications with greater than 300 mA load current, a ceramic  
bypass capacitor of 0.01 μF is recommended on the AVIN pin  
for better regulation performance.  
OUTPUT CAPACITOR SELECTION  
As a guideline, the inductor peak-to-peak current ripple, ΔIL,  
is typically set to 1/3 of the maximum load current for optimal  
transient response and efficiency.  
The output capacitor selection affects both the output voltage  
ripple and the loop dynamics of the converter. For a given loop  
crossover frequency (the frequency at which the loop gain drops  
to 0 dB), the maximum voltage transient excursion (overshoot) is  
inversely proportional to the value of the output capacitor. The  
ADP2102 is designed to operate with small ceramic capacitors that  
have low ESR and equivalent series inductance (ESL) and are thus  
comfortably able to meet tight output voltage ripple specifications.  
X5R or X7R dielectrics are recommended with a voltage rating of  
6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended,  
due to their poor temperature and dc bias characteristics. When  
choosing output capacitors, it is also important to account for the  
loss of capacitance due to output voltage dc bias. If ceramic output  
capacitors are used, the capacitor rms ripple current rating  
should always meet the application requirements. The rms ripple  
current is calculated as  
ILOAD (MAX)  
VOUT ×(VIN −VOUT  
VIN × fSW × L  
)
ΔIL =  
≈
(7)  
3
VOUT ×(VIN −VOUT  
VIN × fSW × 0.3× ILOAD (MAX)  
)
LIDEAL  
=
where fSW is the switching frequency.  
Finally, it is important that the inductor be capable of handling  
the maximum peak inductor current, IPK, determined by the  
following equation:  
I
PK = ILOAD(MAX) + ΔIL/2  
(8)  
VOUT × (VIN _ MAX − VOUT  
L × fSW × VIN _ MAX  
)
1
2 3  
The dc current rating of the inductor should be at least equal  
to the maximum load current plus half the ripple current to  
prevent core saturation. Table 5 shows some typical surface  
mount inductors that work well in ADP2102 applications.  
Irms(COUT)  
=
×
(10)  
At nominal load currents, the converter operates in forced  
continuous conduction mode, and the overall output voltage ripple  
is the sum of the voltage spike caused by the output capacitor ESR  
plus the voltage ripple caused by charging and discharging the  
output capacitor.  
INPUT CAPACITOR SELECTION  
The input capacitor must be able to support the maximum  
input operating voltage and the maximum rms input current.  
The rms input current flowing through the input capacitor is,  
at maximum, IOUT/2. Select an input capacitor capable of with-  
standing the rms input current for the maximum load current  
in the application to be used.  
ΔVOUT = ΔIL × (ESR + 1/ (8 × COUT × fSW))  
(11)  
The largest voltage ripple occurs at the highest input voltage,  
VIN. At light load currents, the converter operates in power save  
mode, and the output voltage ripple is dependent on the output  
capacitor value. The ADP2102 control loop is stable with a ceramic  
output capacitor of 2.2 μF. For better transient performance, a 10 μF  
ceramic capacitor is recommended at the output. Table 6 lists input  
and output MLCC capacitors recommended for ADP2102  
applications.  
VOUT × (VIN − VOUT  
)
Irms = IOUTMAX  
×
(9)  
VIN  
The input capacitor reduces input voltage ripple caused by the  
switch currents on the PVIN pin. Place the input capacitor as  
close as possible to the PVIN pin.  
Page 16 of 24  
 
ADP2102  
Table 5. Recommended Inductor Selection  
Manufacturer  
FDK Corporation  
TDK  
Murata  
Coilcraft, Inc.  
Taiyo Yuden  
Series  
Value (μH)  
DCR (Ω)  
0.08  
0.08  
0.13  
0.11  
Current Rating (mA)  
Size (L × W × H) (mm)  
MIPF2520D  
2.2  
2.2  
2.2  
2.2  
2.2  
1300  
1300  
1000  
1500  
1100  
2.5 × 2.0 × 1.0  
2.5 × 2.0 × 1.0  
2.5 × 2.0 × 1.1  
2.9 × 2.9 × 1.5  
3.0 × 3.0 × 1.0  
MLP2520S2R2L  
LQM2HPN2R2MJ0  
LPS3015-222ML  
NR3010T2R2M  
0.10  
Table 6. Recommended Input and Output Capacitor Selection  
Capacitor  
Murata  
Taiyo Yuden  
TDK  
Vishay  
2.2 ꢀF 6.3 V  
X5R 0603  
GRM188R60J225K  
JMK107BJ225KA  
C1608X5R0J225M  
4.7 ꢀF 6.3 V  
X5R 0603  
10 ꢀF 6.3 V  
X5R 0603  
0.01 ꢀF 25 V  
X7R 0402  
1 pF 50 V  
X7R 0402  
GRM188R60J475K  
JMK107BJ475KA  
JMK107BJ106MA  
TMK105BJ103KV-F  
C1608X5R0J475M  
C2012X5R0J106M  
C1005X7R1E103K  
GRM188R60J106M  
GRM155R71E103KA01D  
GJM1554C1H1R0JB01C  
VJ0402A1R2CXACW1BC  
VJ0402A6R8KXAA  
6.8 pF 25 V  
X7R 0402  
TYPICAL APPLICATIONS CIRCUITS  
V
IN  
INPUT VOLTAGE = 2.7V TO 5.5V  
ADP2102-FXD  
1
2
8
7
MODE  
EN  
AVIN  
PVIN  
V
OUT  
3
4
6
FB/OUT  
AGND  
LX  
L1  
2.2µH  
OUTPUT VOLTAGE = 0.8V TO 1.875V  
5
PGND  
C
C
OUT  
2.2µF  
IN  
2.2µF  
GND  
Figure 47. ADP2102-FXD (0 mA ≤ ILOAD ≤ 300 mA)  
V
IN  
INPUT VOLTAGE = 2.7V TO 5.5V  
ADP2102-FXD  
1
2
8
7
MODE  
EN  
AVIN  
PVIN  
V
OUT  
L1  
3
4
6
5
FB/OUT  
AGND  
LX  
2.2µH  
OUTPUT VOLTAGE = 0.8V TO 1.875V  
PGND  
C
C
C
OUT  
4.7µF  
IN  
2.2µF  
BP  
0.01µF  
GND  
Figure 48. ADP2102-FXD (0 mA ≤ ILOAD ≤ 600 mA)  
Rev. B | Page 17 of 24  
 
 
 
 
ADP2102  
V
IN  
INPUT VOLTAGE = 2.7V TO 5.5V  
ADP2102-ADJ  
1
2
8
7
MODE  
EN  
AVIN  
PVIN  
V
OUT  
L1  
3
4
6
5
FB/OUT  
AGND  
LX  
2.2µH  
OUTPUT VOLTAGE = 0.8V TO 3.3V  
PGND  
C
C
OUT  
4.7µF  
IN  
2.2µF  
GND  
C
FF  
*
R1  
R2  
NOTE  
*C IS NEEDED FOR ADJUSTABLE V  
> 1.875V ONLY.  
FF OUT  
SEE TABLE 7 FOR ADJUSTABLE V CONFIGURATIONS.  
OUT  
Figure 49. ADP2102-ADJ (0 mA ≤ ILOAD ≤ 300 mA)  
V
IN  
INPUT VOLTAGE = 2.7V TO 5.5V  
ADP2102-ADJ  
1
2
8
7
MODE  
EN  
AVIN  
PVIN  
V
OUT  
L1  
3
4
6
5
FB/OUT  
AGND  
LX  
2.2µH  
OUTPUT VOLTAGE = 0.8V TO 3.3V  
PGND  
C
C
C
OUT  
4.7µF  
IN  
2.2µF  
BP  
0.01µF  
GND  
C
FF  
*
R1  
R2  
NOTE  
*C IS NEEDED FOR ADJUSTABLE V  
> 1.875V ONLY.  
FF OUT  
SEE TABLE 7 FOR ADJUSTABLE V CONFIGURATIONS.  
OUT  
Figure 50. ADP2102-ADJ (0 mA ≤ ILOAD ≤ 600 mA)  
Rev. B | Page 18 of 24  
ADP2102  
Table 7. ADP2102-ADJ Configurations for VOUT  
SETTING THE OUTPUT VOLTAGE  
VOUT  
(V)  
R1  
(kΩ)  
R2  
(kΩ)  
CFF  
(pF)  
L
(μH)  
CIN  
COUT  
(μF)  
The output voltage of the ADP2102-ADJ is externally set by  
a resistive voltage divider from the output voltage to FB. The ratio  
of the resistive voltage divider sets the output voltage, and the  
absolute value of those resistors sets the divider string current. For  
lower divider string currents, the small 10 nA (50 nA maximum)  
FB bias current should be taken into account when calculating  
resistor values. The FB bias current can be ignored for a higher  
divider string current, but doing so degrades the efficiency at very  
light loads.  
(μF)  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
0.8  
1.0  
1.2  
1.25  
1.375  
1.5  
1.8  
1.875  
2.0  
1
20  
80.6  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
None  
None  
None  
None  
None  
None  
None  
None  
15  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
4.7  
49.9  
56.2  
71.5  
88.7  
124  
133  
150  
215  
274  
316  
For the ADP2102-ADJ, the equation for output voltage selection is  
2.5  
3.0  
3.3  
10  
8.2  
6.8  
V
OUT = VFB (1 + R1/R2)  
(12)  
where:  
VOUT is the output voltage.  
VFB is the feedback voltage, 0.8 V.  
R1 is the feedback resistor from VOUT to FB.  
R2 is the feedback resistor from FB to GND.  
EFFICIENCY CONSIDERATIONS  
Efficiency is defined as the ratio of output power to input power.  
The high efficiency of the ADP2102 has two distinct advantages.  
First, only a small amount of power is lost in the dc-to-dc converter  
package that reduces thermal constraints. In addition, high effi-  
ciency delivers the maximum output power for the given input  
power, extending battery life in portable applications.  
For any adjustable output voltage greater than 1.875 V, a feed-  
forward capacitor must be added across R1 for better transient  
performance and stability. The formula for calculation of C1 is  
CFF = 1/(2π × R1 × fCO/2)  
(13)  
For example, in a 5 V to 3.3 V application, if a 4.7 μF capacitor  
is used at the output, a 6.8 pF feed-forward capacitor is recom-  
Following are the four major sources of power loss in dc-to-dc  
converters like the ADP2102:  
mended. The output capacitor value dictates the loop crossover  
frequency, fCO. For an output capacitor of 4.7 μF, the loop crossover  
frequency is 150 kHz.  
•
•
•
•
Power switch conduction losses  
Inductor losses  
Switching losses  
The high frequency zero created by CFF and R1 can be very  
important for transient load applications. Capacitor CFF provides  
phase lead and functions as a speed-up capacitor to output  
voltage changes, so it tends to short out R1 and improve the high  
frequency response. This zero tends to produce a positive-going  
bump in the phase plot. Ideally, the peak of this bump is centered  
over the crossover frequency of the loop. The R1 and CFF zero is  
located at  
Transition losses  
Power Switch Conduction Losses  
Power switch conduction losses are caused by the flow of output  
current through the P-channel power switch and the N-channel  
synchronous rectifier, which have internal resistances (RDS(ON)  
associated with them. The amount of power loss can be approxi-  
mated by  
)
2
fZ = 1/(2π × R1 × CFF)  
(14)  
P
SW_COND = (RDS (ON)_P × D + RDS (ON)_N × (1 − D)) × IOUT (15)  
The ADP2102-xx (where xx represents the fixed output voltage)  
includes the resistive voltage divider internally, reducing the  
external circuitry required. For improved load regulation, connect  
the FB/OUT to the output voltage as close as possible to the load.  
where D = VOUT/VIN.  
The internal resistance of the power switches increases with  
temperature but decreases with higher input voltage. Figure 24  
in the Typical Performance Characteristics section shows the  
change in RDS (ON) vs. input voltage, and Figure 25 shows the change  
in RDS (ON) vs. temperature for both power devices.  
For more information about the ADP2102-ADJ configurations  
for VOUT, see Table 7.  
Rev. B | Page 19 of 24  
 
 
ADP2102  
Inductor Losses  
The junction temperature of the die is the sum of the ambient  
temperature of the environment and the temperature rise of the  
package due to power dissipation, shown in the following equation:  
Inductor conduction losses are caused by the flow of current  
through the inductor, which has an internal resistance (DCR)  
associated with it. Larger sized inductors have smaller DCR,  
which may decrease inductor conduction losses.  
TJ = TA + TR  
where:  
(19)  
Inductor core losses are related to the magnetic permeability  
of the core material. Because the ADP2102 is a high switching  
frequency dc-to-dc converter, shielded ferrite core material is  
recommended for its low core losses and low EMI.  
TJ is the junction temperature.  
TA is the ambient temperature.  
TR is the rise in temperature of the package due to power  
dissipation in it.  
The total amount of inductor power loss can be calculated by  
The rise in temperature of the package is directly proportional  
to the power dissipation in the package. The proportionality  
constant for this relationship is defined as the thermal resistance  
from the junction of the die to the ambient temperature, as shown  
in the following equation:  
PL = DCR × IOUT2 + Core Losses  
(16)  
Switching Losses  
Switching losses are associated with the current drawn by the  
driver to turn on and turn off the power devices at the switching  
frequency. Each time a power device gate is turned on and  
turned off, the driver transfers a charge ΔQ from the input  
supply to the gate and then from the gate to ground.  
TR = θJA × PD  
(20)  
where:  
TR is the rise in temperature of the package.  
θJA is the thermal resistance from the junction of the die to the  
ambient temperature of the package.  
The amount of power loss can be calculated by  
P
SW = (CGATE_P + CGATE_N) × VIN2 × fSW  
(17)  
PD is the power dissipation in the package.  
where:  
DESIGN EXAMPLE  
C
C
GATE_P is the gate capacitance of the internal high-side switch.  
GATE_N is the gate capacitance of the internal low-side switch.  
The calculations in this section provide only a rough estimate  
and are no substitute for bench evaluation.  
f
SW is the switching frequency.  
Consider an application where the ADP2102 is used to step  
down from 3.6 V to 1.8 V with an input voltage range of 2.7 V  
to 4.2 V.  
Transition Losses  
Transition losses occur because the P-channel switch cannot  
turn on or turn off instantaneously. In the middle of an LX node  
transition, the power switch provides all the inductor current.  
The source to drain voltage of the power switch is half the input  
voltage, resulting in power loss. Transition losses increase with  
load current and input voltage and occur twice for each  
switching cycle.  
V
OUT = 1.8 V @ 600 mA  
Pulsed Load = 300 mA  
VIN = 2.7 V to 4.2 V (3.6 V typical)  
fSW = 3 MHz (typical)  
TA = 85°C  
The amount of power loss can be calculated by  
Inductor  
P
TRAN = VIN/2 × IOUT × (tR + tF) × fSW  
(18)  
ILOAD (MAX)  
VOUT × (VIN − VOUT  
VIN × fSW × L  
)
where:  
ΔIL =  
≈
= 0.6/3 = 200 mA  
=
3
tR is the rise time of the LX node.  
tF is the fall time of the LX node.  
1.8×(1 − 1.8/4.2)  
(3 × 106 × 0.3 × 0.6)  
VOUT × (1− VOUT /VINMAX  
fSW × 0.3 × ILOAD (MAX)  
)
L =  
=
THERMAL CONSIDERATIONS  
In most applications, the ADP2102 does not dissipate a lot of  
heat, due to its high efficiency. However, in applications with  
maximum loads at high ambient temperature, low supply voltage,  
and high duty cycle, the heat dissipated in the package is great  
enough that it may cause the junction temperature of the die to  
exceed the maximum junction temperature of 125°C. Once the  
junction temperature exceeds 150°C, the converter goes into  
thermal shutdown. It recovers only after the junction temperature  
has decreased to below 135°C to prevent any permanent damage.  
Therefore, thermal analysis for the chosen application solution is  
very important to guarantee reliable performance over all  
conditions.  
1.90 μH  
Choose a 2.2 μH inductor for this application.  
PK = ILOAD(MAX) + ΔIL/2 = 0.6 + 0.2/2 = 0.7 A  
PL = IOUTMAX2 × DCR =  
(0.6 A)2 × 0.08 Ω (FDK MIPF2520D) = 29 mW  
I
Rev. B | Page 20 of 24  
 
ADP2102  
Output Capacitor  
Input Capacitor  
For transient applications, assume a droop of 0.1 V. Typically,  
it takes two to three cycles for the output to settle from a load  
transient because the capacitor alone supplies the load current  
until the loop responds.  
Assume an input ripple of 27 mV based on 1% of VIN_MIN.  
For ceramic capacitors, the typical ESR is from 5 mΩ to 15 mꢀ.  
1
CIN =  
=
(ΔVIN /IOUT − ESR)× 4 × fSW  
Under these conditions, a minimum required output  
capacitance is calculated as follows:  
1
= 2.2 μF  
6
(0.027/0.6−0.005)×4×3×10  
3 × 0.3  
0.1 × 3 ×106  
ΔI  
LOAD  
× f  
COUT_MIN = 3 ×  
=
= 3 μF  
V
DROOP  
SW  
Irms = IOUT/2 = 0.3 A rms  
CIN = Irms2 × ESR = (0.3)2 × 0.005 = 450 μW  
Choose a 4.7 μF capacitor for this application.  
P
For an instantaneous step decrease in load current, the output  
capacitor required to limit the output voltage overshoot (VOS)  
during a full load to no load transient must be determined. This  
transient requires the excess energy stored in the output inductor  
to be absorbed by the output capacitor with a limited overshoot  
in the output voltage.  
Losses  
2
P
SW_COND = (RDS (ON)_P × D + RDS (ON)_N × (1 − D)) × IOUT =  
(0.310 × 0.5 + 0.145 × 0.5) × (0.6)2 = 82 mW  
P
TRAN = (VIN/2) × IOUT × (tR + tF) × fSW  
=
(3.6/2) × 0.6 × (5 ns + 5 ns) × 3 × 106 = 32.4 mW  
P
SW = (CGATE_P + CGATE_N) × VIN2 × fSW = (200 pF) ×  
Assuming an overshoot of 50 mV for a full load transient,  
(3.6)2 × 3 × 106 = 7.8 mW  
2.2 μH × (0.6)2  
(1.85)2 − (1.8)2  
2
L × IOUT  
PL = DCR × IOUT2 = 0.08 × (0.6)2 = 28.8 mW  
COUT  
=
=
= 4.33 μF  
(VOUT + VOS )2 − VOUT  
2
P
LOSS = PSW_COND + PTRAN + PSW + PL =  
Choose a 4.7 μF capacitor for this application.  
82 mW + 32.4 mW + 7.8 mW + 28.8 mW = 151 mW  
VOUT ×(VIN _ MAX −VOUT  
L × fSW ×VIN _ MAX  
1.8 × (4.2 − 1.8)  
)
1
2 3  
T
JMAX = TA + θJA  
LOSS = 85°C + 54°C/W × 151 mW = 93.15°C  
PLOSS is well below the junction temperature maximum of 125°C.  
Irms  
=
×
×
=
P
1
2 3  
= 45 mA rms  
2.2 × 10−6 × 3 ×106 × 4.2  
P
COUT = Irms2 × ESR = (0.045)2 × 0.005 = 10.12 μW  
Rev. B | Page 21 of 24  
ADP2102  
CIRCUIT BOARD LAYOUT RECOMMENDATIONS  
Good circuit board layout is essential in obtaining the best  
performance from the ADP2102. Poor circuit layout degrades  
the output ripple and regulation, as well as the EMI and  
electromagnetic compatibility performance.  
•
Ensure that the high current loops are as short and as wide  
as possible. Make the high current path from CIN through L,  
COUT, and the PGND plane back to CIN as short as possible.  
To accomplish this, ensure that the input and output capacitors  
share a common PGND plane. In addition, make the high  
current path from the PGND pin through L and COUT back  
to the PGND plane as short as possible. To do this, ensure  
that the PGND pin of the ADP2102 is tied to the PGND  
plane as close as possible to the input and output capacitors.  
Place the feedback resistor divider network as close as possible  
to the FB pin to prevent noise pickup. Try to minimize the  
length of trace connecting the top of the feedback resistor  
divider to the output while keeping away from the high  
current traces and the switch node (LX) that can lead to  
noise pickup. To reduce noise pickup, place an analog ground  
plane on either side of the FB trace and make it as small as  
possible to reduce the parasitic capacitance pickup.  
Figure 52 and Figure 53 show the ideal circuit board layout for  
the typical applications circuit shown in Figure 48. Use this  
layout to achieve the highest performance. Refer to the following  
guidelines for optimum layout:  
•
Use separate analog and power ground planes. Connect the  
ground reference of sensitive analog circuitry, such as output  
voltage divider components, to analog ground. In addition,  
connect the ground references of power components, such as  
input and output capacitors, to power ground. Connect both  
ground planes to the exposed pad of the ADP2102.  
•
•
•
Place the input capacitor as close to the PVIN pin as possible  
and connect the other end to the closest power ground plane.  
For low noise and better transient performance, a filter is  
recommended between PVIN and AVIN. Place the 0.1 ꢁF,  
10 ꢀ low-pass input filter between the AVIN pin and the  
PVIN pin, as close to AVIN as possible; or the AVIN pin can  
be bypassed with a ≥1 pF capacitor to the nearest GND plane.  
RECOMMENDED LAYOUT  
VIN  
PGND  
MODE  
9 mm  
CIN  
CBP  
EN  
VOUT  
COUT  
FB/OUT  
8 mm  
INDUCTOR  
L1  
ADP2102  
AGND  
Figure 51. Recommended PCB Layout of the ADP2102-FXD  
Rev. B | Page 22 of 24  
 
ADP2102  
VIN  
PGND  
MODE  
CIN  
CBP  
EN  
VOUT  
COUT  
FB/OUT  
L1  
ADP2102  
INDUCTOR  
AGND  
Figure 52. Recommended Layout of the Top Layer of the ADP2102-FXD Application Board  
VIN  
MODE  
PGND  
EN  
VOUT  
AGND  
FB/OUT  
Figure 53. Recommended Layout of the Bottom Layer of the ADP2102-FXD Application Board  
Rev. B | Page 23 of 24  
 
 
ADP2102  
OUTLINE DIMENSIONS  
3.25  
3.00 SQ  
2.75  
0.60 MAX  
5
0.50  
BSC  
0.60 MAX  
8
2.95  
2.75 SQ  
2.55  
1.60  
1.45  
1.30  
EXPOSED  
PAD  
TOP  
VIEW  
PIN 1  
INDICATOR  
(BOTTOM VIEW)  
4
1
PIN 1  
INDICATOR  
0.50  
0.40  
0.30  
1.89  
1.74  
1.59  
12° MAX  
0.70 MAX  
0.65TYP  
0.90 MAX  
0.85 NOM  
0.05 MAX  
0.01 NOM  
0.30  
0.23  
0.18  
SEATING  
PLANE  
0.20 REF  
Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]  
3 mm × 3 mm Body, Very Thin, Dual Lead  
(CP-8-2)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Output  
Temperature  
Output  
Voltage  
Package  
Description  
Package  
Option  
Model  
Current (mA) Range3  
Branding  
L5T  
L5U  
L5V  
L5W  
L5X  
L5Y  
L5Z  
L60  
L6K  
L6L  
ADP2102YCPZ-0.8-R71  
ADP2102YCPZ-1.0-R71  
ADP2102YCPZ-1.2-R71  
ADP2102YCPZ-1.25R71  
ADP2102YCPZ-1.37R71  
ADP2102YCPZ-1.5-R71  
ADP2102YCPZ-1.8-R71  
ADP2102YCPZ-1.87R71  
ADP2102YCPZ-1-R71  
ADP2102YCPZ-2-R71  
ADP2102YCPZ-3-R71  
ADP2102YCPZ-4-R71  
ADP2102-0.8-EVALZ1  
ADP2102-1.0-EVALZ1  
ADP2102-1.2-EVALZ1  
ADP2102-1.25-EVALZ1  
ADP2102-1.375-EVALZ1  
ADP2102-1.5-EVALZ1  
ADP2102-1.8-EVALZ1  
ADP2102-1.875EVALZ1  
ADP2102-1-EVALZ1  
ADP2102-2-EVALZ1  
ADP2102-3-EVALZ1  
ADP2102-4-EVALZ1  
600  
600  
600  
600  
600  
600  
600  
600  
600  
600  
600  
600  
−40°C to +85°C 0.8 V  
−40°C to +85°C 1.0 V  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
8-Lead LFCSP_VD  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
Evaluation Board  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
CP-8-2  
−40°C to +85°C 1.2 V  
−40°C to +85°C 1.25 V  
−40°C to +85°C 1.375 V  
−40°C to +85°C 1.5 V  
−40°C to +85°C 1.8 V  
−40°C to +85°C 1.875 V  
−40°C to +85°C 0.8 V to 1.2 V  
−40°C to +85°C 1.2 V to 1.5 V  
−40°C to +85°C 1.5 V to 1.875 V  
−40°C to +85°C 2.5 V to 3.3 V2  
Fixed Output 0.8 V  
L6M  
L6N  
Fixed Output 1.0 V  
Fixed Output 1.2 V  
Fixed Output 1.25 V  
Fixed Output 1.375 V  
Fixed Output 1.5 V  
Fixed Output 1.8 V  
Fixed Output 1.875 V  
Adjustable Output 0.8 V to 1.2 V  
Adjustable Output 1.2 V to 1.5 V  
Adjustable Output 1.5 V to1.875 V Evaluation Board  
Adjustable Output 2.5 V to 3.3 V Evaluation Board  
1 Z = RoHS Compliant Part.  
2 2.5 V to 3.3 V adjustable output voltage option is from 4.5 V < VIN < 5.5 V only.  
3 Operating junction temperature range: −40°C to +125°C.  
©2007 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D06631-0-9/07(B)  
Rev. B | Page 24 of 24  
 
 
 
 
 
 
 

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