ADP3405ARU-REEL7_技术文档

a

GSM Power Management System

ADP3405

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Handles all GSM Baseband Power Management

Functions

VBAT

Four LDOs Optimized for Specific GSM Subsystems

Charges Li-Mn Coin Cell for Real-Time Clock

Charge Pump and Logic Level Translators for 3 V and 5 V

GSM SIM Modules

ADP3405

DIGITAL

VCC

LDO

Narrow Body 4.4 mm 28-Lead TSSOP Package

RESET

APPLICATIONS

GSM/DCS/PCS Handsets

TeleMatic Systems

ICO/Iridium Terminals

PWRONKEY

RTC LDO

VRTC

ROWX

POWER-UP

SEQUENCING

AND

PROTECTION

LOGIC

XTAL OSC

LDO

PWRONIN

ANALOGON

RESCAP

VTCXO

VCCA

GENERAL DESCRIPTION

ANALOG

LDO

CHRON

The ADP3405 is a multifunction power management system IC

optimized for GSM cell phones. The wide input voltage range of

3.0 V to 7.0 V makes the ADP3405 ideal for both single cell Li-Ion

and three cell NiMH designs. The current consumption of the

ADP3405 has been optimized for maximum battery life, featuring

a ground current of only 150 µA when the phone is in standby

(digital LDO, and SIM card supply active). An undervoltage lock-

out (UVLO) prevents the startup when there is not enough energy

in the battery. All four integrated LDOs are optimized to power

one of the critical sub-blocks of the phone. Their novel anyCAP^®

architecture requires only very small output capacitors for stability,

and the LDOs are insensitive to the capacitors’ equivalent series

resistance (ESR). This makes them stable with any capacitor,

including ceramic (MLCC) types for space-restricted applications.

SIMBAT

CAP+

CAP؊

CHARGE

VSIM

PUMP

SIMPROG

SIMON

BUFFER

REFOUT

DGND

REF

SIMGND

+

RESETIN

CLKIN

LOGIC LEVEL

TRANSLATION

AGND

DATAIO

CLK RST

I/O

A step-up converter is implemented to supply both the SIM

module and the level translation circuitry to adapt logic signals

for 3 V and 5 V SIM modules. Sophisticated controls are avail-

able for power-up during battery charging, keypad interface, and

charging of an auxiliary backup battery for the real-time clock.

These allow an easy interface between ADP3405, GSM proces-

sor, charger, and keypad. Furthermore, a reset circuit and a

thermal shutdown function have been implemented to support

reliable system design.

anyCAP is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site:www.analog.com

(–20؇C ≤T_A≤+85؇C, VBAT = 3 V to 7 V, C_VBAT= C_SIMBAT= C_VSIM= 10 ␮F, C_VCC= C_VCCA= 2.2 ␮F,

_VRTC= 0.1 ␮F, C_VTCXO= 0.22 ␮F, C_VCAP= 0.1 ␮F, min. loads applied on all outputs, unless

otherwise noted.)

C

ADP3405–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS¹

Parameter

Symbol

Conditions

Min

Typ Max

Unit

SHUTDOWN SUPPLY CURRENT

VBAT = Low (UVLO Low)

VBAT = High (UVLO High)

I_BAT

VBAT = 2.7 V

VBAT = 3.6 V, VRTC On

3

12

20

30

µA

OPERATING GROUND CURRENT

VCC and VRTC On

VCC, VRTC and VSIM On

All LDOs and VSIM On

I_GND

Minimum Loads, VBAT = 3.6 V

Maximum Loads, VBAT = 3.6 V

100 140

150 240

260 400

15

µA

mA

All LDOs and VSIM On

UVLO CHARACTERISTICS

UVLO On Threshold

UVLO Hysteresis

VBAT_UVLO

3.2

200

3.3

V

mV

INPUT CHARACTERISTICS

Input High Voltage

PWRONIN and ANALOGON

PWRONKEY

Input Low Voltage

V_IH

V_IL

2

V

0.7 ꢀ VBAT

PWRONIN and ANALOGON

PWRONKEY

0.4

V

0.3 ꢀ VBAT

PWRONKEY INPUT PULL-UP

RESISTANCE TO VBAT

15

20

25

kΩ

CHRON CHARACTERISTICS

CHRON Threshold

CHRON Hysteresis Resistance

V_T

R_IN

I_B

2.38

108

2.48 2.58

125 138

0.5

V

kΩ

µA

2.38 < CHRON < V_T

CHRON > V_T

CHRON Input Bias Current

ROWX CHARACTERISTICS

ROWX Output Low Voltage

V_OL

I_IH

PWRONKEY = Low

0.4

1

V

I

_OL= 200 µA

ROWX Output High Leakage

Current

PWRONKEY = High

V(ROWX) = 5 V

µA

SHUTDOWN

Thermal Shutdown Threshold²

Thermal Shutdown Hysteresis

Junction Temperature

160

35

ºC

DIGITAL LDO (VCC)

Output Voltage

Line Regulation

VCC

DVCC

Line, Load, Temp

2.710

2.2

2.765 2.820

2

15

V

mV

3 V < VBAT < 7 V, Min Load

50 µA < I_LOAD< 100 mA,

VBAT = 3.6 V

Load Regulation

Output Capacitor³

Dropout Voltage

C_O

V_DO

µF

mV

V_O= V_INITIAL– 100 mV

I_LOAD= 100 mA

215

ANALOG LDO (VCCA)

Output Voltage

VCCA

Line, Load, Temp

2.710

2.765 2.820

V

Line Regulation

Load Regulation

DVCCA

3 V < VBAT < 7 V, Min Load

200 µA < I_LOAD< 130 mA,

VBAT = 3.6 V

2

15

mV

Output Capacitor³

Dropout Voltage

C_O

V_DO

2.2

65

µF

mV

V_O= V_INITIAL– 100 mV

I_LOAD= 130 mA

f = 217 Hz (t = 4.6 ms)

VBAT = 3.6 V

f = 10 Hz to 100 kHz

I_LOAD= 130 mA, VBAT = 3.6 V

215

Ripple Rejection

DVBAT/

DVCCA

V_NOISE

70

75

dB

Output Noise Voltage

µV rms

–2–

REV. 0

ADP3405

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

CRYSTAL OSCILLATOR LDO (VTCXO)

Output Voltage

Line Regulation

VTCXO

∆VTCXO

Line, Load, Temp

2.710

2.765 2.820

2

1

V

mV

3 V < VBAT < 7 V, Min Load

100 µA < I_LOAD< 5 mA,

VBAT = 3.6 V

Load Regulation

Output Capacitor³

Dropout Voltage

C_O

V_DO

0.22

65

µF

mV

V_O= V_INITIAL– 100 mV

150

I

_LOAD= 5 mA

Ripple Rejection

∆VBAT/

∆VTCXO

V_NOISE

f = 217 Hz (t = 4.6 ms),

VBAT = 3.6 V

f = 10 Hz to 100 kHz

72

80

dB

Output Noise Voltage

µV rms

I_LOAD= 5 mA, VBAT = 3.6 V

VOLTAGE REFERENCE (REFOUT)

Output Voltage

Line Regulation

V_REFOUT

∆V_REFOUT

Line, Load, Temp

3 V < VBAT < 7 V, Min Load

1.192

1.210 1.228

2

V

mV

Load Regulation

Ripple Rejection

∆V_REFOUT

0 µA < I_LOAD< 50 µA,

VBAT = 3.6 V

f = 217 Hz (t = 4.6 ms),

0.5

75

mV

dB

∆VBAT/

∆V_REFOUT

C_O

65

VBAT = 3.6 V

Maximum Capacitive Load

Output Noise Voltage

100

pF

µV rms

V_NOISE

f = 10 Hz to 100 kHz

VBAT = 3.6 V

40

REAL-TIME CLOCK LDO/

BATTERY CHARGER (VRTC)

Maximum Output Voltage

Current Limit

Off Reverse Leakage Current

Dropout Voltage

VRTC

I_MAX

I_L

I_LOAD≤ 10 µA

2.810

2.850 2.890

V

3.050 V < VBAT < 7 V

2.0 V < VBAT < UVLO

V_O= V_INITIAL– 10 mV

I_LOAD= 10 µA

175

1

µA

mV

V_DO

170

SIM CHARGE PUMP (VSIM)

Output Voltage for 5 V SIM Modules

VSIM

0 mA ≤ I_LOAD≤ 10 mA

SIMPROG = High

0 mA ≤ I_LOAD≤ 6 mA

SIMPROG = Low

4.70

2.82

5.00

3.00

5.30

3.18

V

Output Voltage for 3 V SIM Modules

GSM/SIM LOGIC TRANSLATION

(GSM INTERFACE)

Input High Voltage (SIMPROG, SIMON, V_IH

RESETIN, CLKIN)

VCC – 0.6

V

Input Low Voltage (SIMPROG, SIMON,

RESETIN, CLKIN)

DATAIO

V_IL

0.6

V_OL(I/O) = 0.4 V,

0.230

0.335

I

_OL(I/O) = 1 mA

_OL(I/O) = 0.4 V,

I_OL(I/O ) = 0 mA

I_IH, I_OH10 µA

V_IL= 0 V

V

V_IH, V_OH

I_IL

V_OL

=

VCC – 0.4

16

V

mA

V

kΩ

–0.9

0.420

24

V_IL(I/O) = 0.4 V

DATAIO Pull-Up Resistance to VCC

R_IN

20

REV. 0

–3–

ADP3405

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SIM INTERFACE

VSIM = 5 V

RST

CLK

I/O

V_OL

V_OH

V_OL

V_OH

V_IL

V_IH, V_OH

I_IL

V_OL

I = +200 µA

I = –20 µA

I = +200 µA

I = –20 µA

0.6

0.5

0.4

V

mA

V

VSIM – 0.7

0.7 ꢀ VSIM

VSIM – 0.4

I_IH, I_OH

V_IL= 0 V

=

20 µA

–0.9

0.4

I_OL= +1 mA

DATAIO ≤ 0.23 V

VSIM = 3 V

RST

CLK

I/O

V_OL

V_OH

V_OL

V_OH

V_IL

I = +200 µA

I = –20 µA

I = +20 µA

I = –20 µA

0.2 ꢀ VSIM

0.4

V

0.8 ꢀ VSIM

0.7 ꢀ VSIM

VSIM – 0.4

I/O

V_IH, V_OH

I_IL

I_IH, I_OH

V_IL= 0 V

=

20 µA

–0.9

0.4

mA

V

I/O

V_OL

I_OL= 1 mA

DATAIO ≤ 0.23 V

I/O Pull-Up Resistance to VSIM

Max Frequency (CLK)

Prop Delay (CLK)

Output Rise/Fall Times (CLK)

Output Rise/Fall Times (I/O, RST)

Duty Cycle (CLK)

R_IN

f_MAX

t_D

t_R, t_F

D

8

5

10

12

kΩ

MHz

ns

µs

%

C_L= 30 pF

30

9

50

18

1

C_L= 30 pF

D CLKIN = 50%

f = 5 MHz

47

53

RESET GENERATOR (RESET)

Output High Voltage

Output Low Voltage

Delay Time Per Unit Capacitance

Applied to RESCAP Pin

V_OH

V_OL

t_D

I_OH= –15 µA

I_OL= –15 µA

VCC – 0.3

1.0

V

ms/nF

0.3

NOTES

¹All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods .

²This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125 °C. Operation beyond 125°C

could cause permanent damage to the device.

³Required for stability.

Specifications subject to change without notice.

–4–

REV. 0

ADP3405

ABSOLUTE MAXIMUM RATINGS*

PIN FUNCTION DESCRIPTIONS

Voltage on Any Pin with Respect

Mnemonic

Function

to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V

Voltage on Any Pin May Not Exceed VBAT,

with the Following Exceptions: VRTC, VSIM,

CAP+, PWRONIN, I/O, CLK, RST

Storage Temperature Range . . . . . . . . . . . . –65

Operating Temperature Range . . . . . . . . . . . –20

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125

1

2

3

RESCAP

DGND

VTCXO

Reset Delay Timing Cap

Digital Ground

Crystal Oscillator Low Dropout

Regulator

Main Reset

Reference Output

Analog Low Dropout Regulator

Analog Ground

Battery Input Voltage

Digital Low Dropout Regulator

Power-On/-Off Key

°

C to +150

°C

°C to +85°C

4

5

6

7

8

9

10

11

12

RESET

REFOUT

VCCA

AGND

VBAT

VCC

PWRONKEY

ANALOGON

PWRONIN

°C

θ_JA, Thermal Impedance (TSSOP-28) . . 4-Layer Board 68

°

C/W

θ_JA, Thermal Impedance (TSSOP-28) . . 6-Layer Board 62

°C/W

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

*This is a stress rating only, operation beyond these limits can cause the device to

be permanently damaged.

VTCXO Enable

Power-On/-Off Signal from

Microprocessor

PIN CONFIGURATION

13

14

15

ROWX

CHRON

VRTC

Microprocessor Keyboard Output

Charger On/Off Input

Real-Time Clock Supply/Coin

Cell Battery Charger

Negative Side of Boost Capacitor

Battery Input for the SIM

Charge Pump

Non-Level-Shifted Bidirectional

Data I/O

Non-Level-Shifted SIM Reset

Non-Level-Shifted Clock

Charge Pump Ground

Level-Shifted Bidirectional SIM

Data Input/Output

Level-Shifted SIM Reset

VSIM Programming:

Low = 3 V, High = 5 V

VSIM Enable

Level-Shifted SIM Clock

SIM Supply

RESCAP

DGND

CAP+

VSIM

1

2

28

27

3

VTCXO

RESET

26 CLK

SIMON

4

16

17

CAP–

SIMBAT

25

5

REFOUT

VCCA

AGND

VBAT

VCC

24 SIMPROG

23 RST

6

7

I/O

22

18

DATAIO

ADP3405

8

SIMGND

21

(Not To Scale)

9

CLKIN

20

19

20

21

22

RESETIN

CLKIN

SIMGND

I/O

10

11

12

13

14

RESETIN

19

PWRONKEY

ANALOGON

PWRONIN

ROWX

DATAIO

18

SIMBAT

17

CAP–

VRTC

16

15

CHRON

23

24

RST

SIMPROG

TSSOP-28

25

26

27

28

SIMON

CLK

VSIM

CAP+

ORDERING GUIDE

Positive Side of Boost Capacitor

Temperature

Range

Package

Description

Package

Option

Model

ADP3405ARU –20°C to +85°C 28-Lead TSSOP RU-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADP3405 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

ADP3405

Table I. LDO Control Logic

Inputs

Outputs

UVLO

CHRON

PWRONKEY

PWRONIN

ANALOGON

VRTC

VCC VCCA REFOUT VTCXO

L

X

H

X

L

X

L

X

L

X

L

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

H

L

H

L

H

X = Don’t care

Bold denotes the active control signal.

Table II. VSIM Control Logic

Inputs

Outputs

VSIM

VCC

RESET

SIMON

SIMPROG

Off

On

L

H

X

L

H

X

L

Off

3 V

5 V

H

X = Don’t care

VBAT

ADP3405

DIGITAL LDO

VBAT

VCC

2.45V

OUT

PG

VREF

EN

20k⍀

ADJ

UVLO

GND

UVLO

DGND

POWER GOOD

PWRONKEY

ROWX

OVER

TEMP

RTC LDO

VRTC

2.45V

OUT

VBAT

EN

GND

PWRONIN

RESCAP

RESET

GENERATOR

XTAL OSC LDO

VBAT

VTCXO

2.765V

CHARGER

VREF

EN

OUT

CHRON

ON

THRESHOLD

GND

ANALOGON

SIMBAT

CAP+

ANALOG LDO

VBAT

EN

CHARGE

PUMP

3V/5V

CAP–

VCCA

2.765V

VREF

EN

OUT

SIMPROG

SIMON

GND

EN GND

SIMGND

RESETIN

EN

LOGIC

LEVEL

TRANSLATION

REF

BUFFER

CLKIN

REFOUT

AGND

DATAIO

+

1.210V

I/O CLK RST

VSIM

Figure 1. Functional Block Diagram

–6–

REV. 0

ADP3405

300

250

200

150

100

50

350

300

250

PWRONIN, SIMON, AND ANALOGON

+85؇C

PWRONIN AND SIMON

200

150

100

50

+25؇C

PWRONIN

؊20؇C

0

3

4

5

6

7

0.5

1.0

1.5

2.0

2.5

3

VRTC – V

VBAT – V

TPC 1. Ground Current vs. Battery Voltage

TPC 4. RTC I/V Characteristic

140

120

MLCC CAPS

VBAT 100mV/DIV

3.2

3.0

100

VCC

VCCA

80

VCC 10mV/DIV

60

40

20

0

VCCA 10mV/DIV

VTCXO 10mV/DIV

0

20

40

60

80

100

120

140

LOAD CURRENT – mA

TIME – 100␮s/DIV

TPC 2. VCC, VCCA Dropout Voltage vs. Load Current

TPC 5. Line Transient Response, Maximum Loads

70

60

50

40

30

20

MLCC CAPS

VBAT (100mV/DIV)

3.2

3.0

VCC (10mV/DIV)

VCCA (10mV/DIV)

VTCXO (10mV/DIV)

10

0

1

2

3

4

5

TIME – 100␮s/DIV

LOAD CURRENT – mA

TPC 3. VTCXO Dropout Voltage vs. Load Current

TPC 6. Line Transient Response, Minimum Loads

REV. 0

–7–

ADP3405

MLCC CAPS

I = 100mA

I

LOAD

PWRONIN AND ANALOGON (2V/DIV)

VCCA (100mV/DIV)

I = 200␮A

VCC

REFOUT (100mV/DIV)

VCC (100mV/DIV)

VTCXO (100mV/DIV)

TIME – 200␮s/DIV

TIME – 50␮s/DIV

TPC 7. VCC Load Step

TPC 10. Turn-On Transients, Maximum Loads

80

MLCC CAPS

I = 130mA

70

60

50

40

30

20

10

0

VTCXO

I

VCCA

LOAD

I = 50␮A

REFOUT

MLCC OUTPUT CAPS

VBAT = 3.2V, FULL LOADS

VCC

VCCA

4

10

100

1k

10k

100k

TIME – 100␮s/DIV

FREQUENCY – Hz

TPC 8. VCCA Load Step

TPC 11. Ripple Rejection vs. Frequency

80

70

60

50

40

30

20

10

0

REFOUT

PWRONIN AND ANALOGON (2V/DIV)

VCCA (100mV/DIV)

VCCA

VTCXO (100mV/DIV)

VCC (100mV/DIV)

VCC

VTCXO

FREQUENCY = 217Hz

MAX LOADS

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

TIME – 50␮s/DIV

VBAT – V

TPC 9. Turn-On Transients, Minimum Loads

TPC 12. Ripple Rejection vs. Battery Voltage

–8–

REV. 0

ADP3405

These functions have traditionally been done as either a discrete

implementation or a custom ASIC design. ADP3405 combines

the benefits of both worlds by providing an integrated standard

product solution where every block is optimized to operate in a

GSM environment while maintaining a cost-competitive solution.

600

500

FULL LOAD

MLCC CAPS

VCCA

TCXO

400

300

200

100

0

Figure 2 shows the external circuitry associated with the ADP3405.

Only a few support components, mainly decoupling capacitors,

are required.

Input Voltage

REF

The input voltage range for ADP3405 is 3 V to 7 V and optimized

for a single Li-Ion cell or three NiMH/NiCd cells. The thermal

impedance (θ_JA) of the ADP3405 is 62°C/W for 6-layer boards.

The charging voltage for a high capacity NiMH cell can be as high

as 5.5 V. Power dissipation should be calculated at maximum

ambient temperatures and battery voltage in order not to exceed

10

100

1k

10k

100k

FREQUENCY – Hz

TPC 13. Output Noise Density

THEORY OF OPERATION

The ADP3405 is a power management chip optimized for use with

the AD20msp425 GSM baseband chipsets in handset applications.

Figure 1 shows a functional block diagram of the ADP3405.

the 125°C maximum allowable junction temperature. Figure 3

shows the maximum total LDO output current as a function of

ambient temperature and battery voltage.

However, high battery voltages normally occur only when the

battery is being charged and the handset is not in conversation

mode. In this mode there is a relatively light load on the LDOs.

A fully charged Li-Ion battery is 4.25 V, where the LDOs deliver

The ADP3405 contains several blocks:

• Four Low Dropout Regulators (Digital, Analog, Crystal

Oscillator, Real-Time Clock)

• Reset Generator

the maximum 240 mA up to the max 85°C ambient temperature.

• Buffered Precision Reference

• SIM Interface Logic Level Translation (3 V/5 V)

• SIM Voltage Supply

• Power-On/-Off Logic

• Undervoltage Lockout

ANALOG GND

1

2

28

27

26

25

RESCAP

DGND

CAP+

VSIM

100nF

DIGITAL AND

SIM GND

10␮F

3

VTCXO

RESET

REFOUT

CLK

CLK TO SIM CARD

0.22␮F

4

SIMON

GSM

PROCESSOR

5

SIMPROG 24

10⍀

2.2␮F

100nF

ADP3405

6

23

VCCA

RST

RST TO SIM CARD

I/O TO SIM CARD

7

AGND

I/O 22

8

21

20

VBAT

SIMGND

CLKIN

10␮F

9

VCC

SIM PINS

OF

2.2␮F

1 LI-ION

10

11

12

13

14

RESETIN 19

PWRONKEY

ANALOGON

PWRONIN

ROWX

OR

GSM PROCESSOR

3 NIMH

18

DATAIO

GSM

100nF

17

16

15

SIMBAT

CAP–

PROCESSOR

CHARGER

INPUT

CHRON

VRTC

BACK-UP

COIN CELL

R1

100nF

R2

TSSOP-28

10␮F

Figure 2. Typical Application Circuit

REV. 0

–9–

ADP3405

RTC LDO (VRTC)

300

6-LAYER BOARD

JA

The RTC LDO charges a rechargable coin cell to run the real-

time clock module. It has been targeted to charge Manganese

Lithium batteries such as the ML series (ML621/ML1220)

from Sanyo. The ML621 has a small physical size (6.8 mm

diameter) and a nominal capacity of 2.5 mAh, which yields

about 250 hours of backup time.

␪

= 62؇C/W

VBAT = 5V

250

200

150

100

50

VBAT = 5.5V

VBAT = 6V

VBAT = 7V

Figure 5 shows the use of VRTC with the Enhanced GSM

Processor which is a part of the AD20msp425 chipset.

ENHANCED

ADP3405

GSM PROCESSOR

(AD20msp425)

0

VRTC

؊20

0

20

40

60

80 85

AMBIENT TEMPERATURE – ؇C

COIN

CELL

RTC

MODULE

Figure 3. Total LDO Load Current vs. Temperature and VBAT

Low Dropout Regulators (LDOs)

PWRONIN

PWRON

The ADP3405 high-performance LDOs are optimized for

their given functions by balancing quiescent current, dropout

voltage, line/load regulation, ripple rejection, and output

noise. 2.2 µF tantalum or MLCC ceramic capacitors are

recommended for use with the digital and analog LDOs, and

0.22 µF for the TCXO LDO.

Figure 5. Connecting VRTC and PWRONIN to the

AD20msp425 Chipset

Digital LDO (VCC)

The ADP3405 supplies current both for charging the coin cell and

for the RTC module when the digital supply is off. The nominal

charging voltage of 2.85 V ensures charging down to a main

battery voltage of 3.0 V. The inherent current limit of VRTC

ensures long cell life while the precise output voltage regulation

charges the cell to more than 90% of its capacity. In addition, it

features a very low quiescent current (10 µA) since this LDO is

running all the time, even when the handset is switched off. It also

has reverse current protection with low leakage which is needed

when the main battery is removed and the coin cell supplies the

RTC module.

The digital LDO (VCC) supplies all the digital circuitry in the

handset (baseband processor, baseband converter, external

memory, display, etc.). The LDO has been optimized for very

low quiescent current (30 µA maximum) at light loads as this

LDO is on at all times. This is due to both the structure of GSM

and a new clocking scheme used in the AD20msp425. Figure 4

shows how the digital current varies as a function of time.

~2ms

0.5s TO 2s

The RTC module has a built-in alarm which, when it expires,

will pull PWRONIN high, allowing an alarm function even if

the handset is switched off.

~50mA

Reference Output (REFOUT)

~200␮A

The reference output is a low-noise, high-precision reference

with a guaranteed accuracy of 1.5% over temperature. The

reference can be fed to the baseband converter, such as the

AD6425, improving the absolute accuracy of the converters

from 5% to 1.5%. This significantly reduces calibration time

needed for the baseband converter during production.

TIME

MICROPROCESSOR

START

MICROPROCESSOR

STOP

Figure 4. Digital Power as a Function of Time

Analog LDO (VCCA)

SIM Interface

This LDO has the same features as the digital LDO. It has further-

more been optimized for good low frequency ripple rejection for use

with analog sections in order to reject the ripple coming from the RF

power amplifier. VCCA is rated to 130 mA load which is sufficient

to supply the complete analog section of a baseband converter such

as the AD6421/AD6425, including a 32 Ω earpiece. The analog

LDO and the TCXO LDO can be controlled by ANALOGON.

The SIM interface generates the needed SIM voltage—either 3 V

or 5 V, dependent on SIM type, and also performs the needed

logic level translation. Quiescent current is low, as the SIM card

will be powered all the time. Note that DATAIO and I/O have

integrated pull-up resistors as shown in Figure 6. See Table II for

the control logic of the charge pump output, VSIM.

TCXO LDO (VTCXO)

The TCXO LDO is intended as a supply for the temperature-

compensated crystal oscillator, which needs its own ultralow noise

supply. The output current is rated to 5 mA for the TCXO LDO.

–10–

REV. 0

ADP3405

RESET

ADP3405

ADP3405 contains reset circuitry that is active both at power-up

and at power-down. RESET is held low at power-up. An inter-

nal power-good signal starts the reset delay. The delay is set by

an external capacitor on RESCAP:

VCC

VSIM

LEVEL

SHIFT

RESETIN

CLKIN

RST

CLK

VCC

VSIM

ms

nF

t_RESET= 1.0

×C_RESCAP

LEVEL

SHIFT

A 100 nF capacitor will produce a 100 ms reset time. At power-off,

RESET will be kept low to prevent any spurious microprocessor

starts. The current capability of RESET is low (a few hundred nA)

when VCC is off, to minimize power consumption. Therefore,

RESET should only be used to drive a single CMOS input. When

VCC is on, RESET will drive about 15 µA.

DATAIO

I/O

Figure 6. Schematic for Level Translators

Power-On/-Off

ADP3405 handles all issues regarding power-on/-off of the hand-

set. It is possible to turn on the ADP3405 in three different ways:

Overtemperature Protection

The maximum die temperature for ADP3405 is 125°C. If the die

temperature exceeds 160°C, the ADP3405 will disable all the

LDOs except the RTC LDO, which has very limited current capa-

bilities. The LDOs will not be re-enabled before the die tempera-

• Pulling PWRONKEY low

• Pulling PWRONIN high

• CHRON exceeds threshold

ture is below 125°C, regardless of the state of PWRONKEY,

PWRONIN, and CHRON. This ensures that the handset will

always power-off before the ADP3405 exceeds its absolute maxi-

mum thermal ratings.

Pulling PWRONKEY key low is the normal way of turning on the

handset. This will turn on all the LDOs as long as PWRONKEY is

held low. The microprocessor then starts and pulls PWRONIN

high after which PWRONKEY can be released. PWRONIN going

high will also turn on the handset. This is the case when the alarm

in the RTC module expires.

APPLICATIONS INFORMATION

Input Capacitor Selection

For the input voltage, VBAT, of the ADP3405, a local bypass

capacitor is recommended. Use a 5 µF to 10 µF, low ESR capaci-

tor. Multilayer ceramic chip capacitors provide the best combina-

tion of low ESR and small size, but may not be cost-effective. A

lower cost alternative may be to use a 5 µF to 10 µF tantalum

capacitor with a small (1 µF to 2 µF) ceramic in parallel.

An external charger can also turn on the phone. The turn-on

threshold and hysteresis can be programmed via external resistors

to allow full flexibility with any external charger and battery chem-

istry. These resistors are referred to as R1 and R2 in Figure 2.

Undervoltage Lockout (UVLO)

LDO Capacitor Selection

The UVLO function in the ADP3405 prevents startup when the

initial voltage of the main battery is below the 3.0 V threshold.

If the battery is this low with no load, there will be little or no

capacity left. When the battery is greater than 3.0 V, as with the

insertion of a fresh battery, the UVLO comparator trips, the

RTC LDO is enabled, and the threshold is reduced to 2.9 V.

This allows the handset to start normally until the battery volt-

age decays to 2.9 V open circuit. Once the 3.0 V threshold is

exceeded, the RTC LDO is enabled. If, however, the backup

coin cell is not connected, or is damaged or discharged below

1.5 V, the RTC LDO will not start on its own. In this situation,

the RTC LDO will be started by enabling the VCC LDO.

The performance of any LDO is a function of the output capaci-

tor. The digital and analog LDOs require a 2.2 µF capacitor and

the TCXO LDO requires a 0.22 µF capacitor. Larger values

may be used, but the overshoot at startup will increase slightly.

If a larger output capacitor is desired, be sure to check that the

overshoot and settling time are acceptable for the application.

All the LDOs are stable with a wide range of capacitor types and

ESR due to Analog Devices’ anyCAP technology. The ADP3405

is stable with extremely low ESR capacitors (ESR ~ 0), such as

multilayer ceramic capacitors, but care should be taken in their

selection. Note that the capacitance of some capacitor types shows

wide variations over temperature or with dc voltage. A good quality

dielectric, X7R or better, is recommended.

Once the system is started, i.e., the phone is turned on and the

VCC LDO is up and running, the UVLO function is entirely

disabled. The ADP3405 is then allowed to run down to very low

battery voltages, typically around 2 V. The battery voltage is

normally monitored by the microprocessor and usually shuts the

phone off at around 3.0 V.

The RTC LDO has a rechargeable coin cell or an electric double-

layer capacitor as a load, but an additional 0.1 µF ceramic capaci-

tor is recommended for stability and best performance.

Charge Pump Capacitor Selection

For the input (SIMBAT) and output (VSIM) of the SIM charge

pump, use 10 µF low ESR capacitors. The use of low ESR capaci-

tors improves the noise and efficiency of the SIM charge pump.

Multilayer ceramic chip capacitors provide the best combination of

low ESR and small size but may not be cost-effective. A lower cost

alternative may be to use a 10 µF tantalum capacitor with a small

(1 µF to 2 µF) ceramic capacitor in parallel.

If the phone is off, i.e., the VCC LDO is off, and the battery

voltage drops below 2.9 V, the UVLO circuit disables startup

and the RTC LDO. This is implemented with very low quies-

cent current, typically 3 µA, to protect the main battery against

any damage. NiMH batteries can reverse polarity if the 3-cell

battery voltage drops below 3.0 V and a current of more than

about 40 µA continues to flow. Lithium ion batteries will lose

their capacity, although the built-in safety circuits normally

present in these cells will most likely prevent any damage.

REV. 0

–11–

ADP3405

For the lowest ripple and best efficiency, use a 0.1 µF, ceramic

capacitor for the charge pump flying capacitor (CAP+ and CAP–).

A good quality dielectric, such as X7R is recommended.

Example: R1 = 10 kΩ and R2 = 30.2 kΩ gives a charger thresh-

old (not counting the drop in the power Schottky diode) of

3.5 V 160 mV with a 200 mV 30 mV hysteresis.

Setting the Charger Turn-On Threshold

Charger Diode Selection

The ADP3405 can be turned on when the charger input exceeds

a programmable threshold voltage. The charger’s threshold and

hysteresis are set by selecting the values for R1 and R2 shown in

Figure 2.

The diode shown in Figure 2 is used to prevent the battery from

discharging into the charger turn-on setting resistors, R1 and R2.

A Schottky diode is recommended to minimize the voltage differ-

ence from the charger to the battery and the power dissipation.

Choose a diode with a current rating high enough to handle both

the battery charging current and the current the ADP3405 will

draw if powered up during charging. The battery charging current

is dependent on the battery chemistry and the charger circuit.

The ADP3405 current will be dependent on the loading.

The turn-on threshold for the charger is calculated using:













R2 + R_HYS

V_CHR

=

× R1 +1 ×V









T

R2 × R









HYS

Where V_Tis the CHRON threshold voltage and R_HYSis the

CHRON hysteresis resistance.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed

circuit boards:

The hysteresis is determined using:

1. Split the battery connection to the VBAT and SIMBAT

pins of the ADP3405. Use separate traces for each connection

and locate the input capacitors as close to the pins as possible.

V_T

R_HYS

V_HYS

=

× R1

Combining the above equations and solving for R1 and R2 gives

the following formulas:

2. SIM input and output capacitors should be returned to the

SIMGND and kept as close as possible to the ADP3405 to

minimize noise. Traces to the SIM charge pump capacitor

should be kept as short as possible to minimize noise.

R_HYS

V_T

R1 =

×V_HYS

3. VCCA and VTCXO capacitors should be returned to AGND.

4. VCC and VRTC capacitors should be returned to DGND.

R1× R_HYS

R2 =





V_CHR

V_T

−1 × R_HYS− R1

5. Split the ground connections. Use separate traces or planes

for the analog, digital, and power grounds, and tie them

together at a single point, preferably close to the battery return.









OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Thin Shrink Small Outline (TSSOP)

(RU-28)

0.386 (9.80)

0.378 (9.60)

28

15

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

0.246 (6.25)

1

14

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433 (1.10)

MAX

8؇

0؇

0.0256 (0.65) 0.0118 (0.30)

BSC

0.028 (0.70)

0.020 (0.50)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

0.0075 (0.19)

–12–

REV. 0


型号：	ADP3405ARU-REEL7
厂家：	Rochester Electronics
描述：	1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28, 4.40 MM, TSSOP-28 光电二极管
文件：	总13页 (文件大小：828K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP3405ARU-REEL7 [ROCHESTER]

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