AM79C940B-25JC-G_技术文档

REI Datasheet

AM79C940B

Media Access Controller for Ethernet (MACE)

The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to

provide ﬂexibility in customized LAN design. The MACE device is speciﬁcally designed to address

applications where multiple I/O peripherals are present, and a centralized or system speciﬁc DMA is

required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or

I/O processor system, and is similar to many existing peripheral devices such as SCSI and serial link

controllers.

Quality Overview

Rochester Electronics

Manufactured Components

•

ISO-9001

AS9120 certiﬁcation

Qualiﬁed Manufacturers List (QML) MIL-PRF-38535

Rochester branded components are

manufactured using either die/wafers

purchased from the original suppliers

or Rochester wafers recreated from the

original IP. All recreations are done with

the approval of the OCM.

•

Class Q Military

Class V Space Level

•

Qualiﬁed Suppliers List of Distributors (QSLD)

•

Rochester is a critical supplier to DLA and

meets all industry and DLA standards.

Parts are tested using original factory

test programs or Rochester developed

test solutions to guarantee product

meets or exceeds the OCM data sheet.

RochesterElectronics, LLCiscommittedtosupplying

products that satisfy customer expectations for

quality and are equal to those originally supplied by

industry manufacturers.

The original manufacturer’s datasheet accompanying this document reﬂects the performance

and speciﬁcations of the Rochester manufactured version of this device. Rochester Electronics

guarantees the performance of its semiconductor products to the original OEM speciﬁcations.

‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be

based on product characterization, design, simulation, or sample testing.

To learn more, please visit www.rocelec.com

FINAL

Am79C940

Media Access Controller for Ethernet (MACE™)

DISTINCTIVE CHARACTERISTICS

■ Integrated Controller with Manchester

encoder/decoder and 10BASE-T transceiver

and AUI port

■ Arbitrary byte alignment and little/big endian

memory interface supported

■ Internal/external loopback capabilities

■ Supports IEEE 802.3/ANSI 8802-3 and Ethernet

■ External Address Detection Interface (EADI)

for external hardware address filtering in

bridge/router applications

standards

■ 84-pin PLCC and 100-pin PQFP Packages

■ 80-pin Thin Quad Flat Pack (TQFP) package

available for space critical applications such as

PCMCIA

■ JTAG Boundary Scan (IEEE 1149.1) test access

port interface for board level production test

■ Integrated Manchester Encoder/Decoder

■ Modular architecture allows easy tuning to

■ Digital Attachment Interface (DAI) allows

by-passing of differential Attachment Unit

Interface (AUI)

specific applications

■ High speed, 16-bit synchronous host system

interface with 2 or 3 cycles/transfer

■ Supports the following types of network

■ Individual transmit (136 byte) and receive (128

byte) FlFOs provide increase of system latency

and support the following features:

interface:

— AUI to external 10BASE2, 10BASE5 or

10BASE-F MAU

— Automatic retransmission with no FIFO

reload

— DAI port to external 10BASE2, 10BASE5,

10BASE-T, 10BASE-F MAU

— Automatic receive stripping and transmit

padding (individually programmable)

— General Purpose Serial Interface (GPSI) to

external encoding/decoding scheme

— Automatic runt packet rejection

— Internal 10BASE-T transceiver with

— Automatic deletion of collision frames

automatic selection of 10BASE-T or AUI port

— Automatic retransmission with no FIFO

reload

■ Sleep mode allows reduced power consump-

tion for critical battery powered applications

■ Direct slave access to all on board

configuration/status registers and transmit/

receive FlFOs

■ 5 MHz-25 MHz system clock speed

■ Support for operation in industrial temperature

range (–40°C to +85°C) available in all three

packages

■ Direct FIFO read/write access for simple

interface to DMA controllers or l/O processors

GENERAL DESCRIPTION

The Media Access Controller for Ethernet (MACE) chip

is a CMOS VLSI device designed to provide flexibility

in customized LAN design. The MACE device is specif-

ically designed to address applications where multiple

I/O peripherals are present, and a centralized or sys-

tem specific DMA is required. The high speed, 16-bit

synchronous system interface is optimized for an exter-

nal DMA or I/O processor system, and is similar to

many existing peripheral devices, such as SCSI and

serial link controllers.

The MACE device is a slave register based peripheral.

All transfers to and from the system are performed

using simple memory or I/O read and write commands.

In conjunction with a user defined DMA engine, the

MACE chip provides an IEEE 802.3 interface tailored

to a specific application. Its superior modular architec-

ture and versatile system interface allow the MACE

device to be configured as a stand-alone device or

as a connectivity cell incorporated into a larger,

integrated system.

Publication# 16235 Rev: E Amendment/0

Issue Date: May 2000

The MACE device provides a complete Ethernet node

solution with an integrated 10BASE-T transceiver, and

supports up to 25-MHz system clocks. The MACE

device embodies the Media Access Control (MAC)

and Physical Signaling (PLS) sub-layers of the IEEE

802.3 standard, and provides an IEEE defined Attach-

ment Unit Interface (AUI) for coupling to an external

Medium Attachment Unit (MAU). The MACE device is

compliant with 10BASE2, 10BASE5, 10BASE-T, and

10BASE-F transceivers.

The Am79C940 MACE chip is offered in a Plastic

Leadless Chip Carrier (84-pin PLCC), a Plastic Quad

Flat Package (100-pin PQFP), and a Thin Quad Flat

Package (TQFP 80-pin). There are several small func-

tional and physical differences between the 80-pin

TQFP and the 84-pin PLCC and 100-pin PQFP config-

urations. Because of the smaller number of pins in the

TQFP configuration versus the PLCC configuration,

four pins are not bonded out. Though the die is identical

in all three package configurations, the removal of

these four pins does cause some functionality differ-

ences between the TQFP and the PLCC and PQFP

configurations. Depending on the application, the

removal of these pins will or will not have an effect.

(See section: “Pins Removed for TQFP Package and

Their Effects.)

Additional features also enhance over-all system

design. The individual transmit and receive FIFOs

optimize system overhead, providing substantial

latency during packet transmission and reception, and

minimizing intervention during normal network error

recovery. The integrated Manchester encoder/decoder

eliminates the need for an external Serial Interface

Adapter (SIA) in the node system. If support for an

external encoding/decoding scheme is desired, the

General Purpose Serial Interface (GPSI) allows direct

access to/from the MAC. In addition, the Digital Attach-

ment Interface (DAI), which is a simplified electrical

attachment specification, allows implementation of

MAUs that do not require DC isolation between the

MAU and DTE. The DAI port can also be used to

indicate transmit, receive, or collision status by

connecting LEDs to the port. The MACE device also

provides an External Address Detection Interface

(EADI) to allow external hardware address filtering in

internet working applications.

With the rise of embedded networking applications op-

erating in harsh environments where temperatures

may exceed the normal commercial temperature (0°C

to +70°C) window, an industrial temperature (-40°C to

+85°C) version is available in all three packages; 84-

pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus-

trial temperature version of the MACE Ethernet control-

ler is characterized across the industrial temperature

range (-40°C to +85°C) within the published power

supply specification (4.75 V to 5.25 V; i.e., 5% V_CC).

Thus, conformance of MACE performance over this

temperature range is guaranteed by the design and

characterization monitor.

2

Am79C940

CONNECTION DIAGRAMS

PL 084

PLCC PACKAGE

11 10 9

12

8

7

6

5

4

3 2 1 84 83 82 81 80 79 78 77 76 75

SRDCLK

EAM/R

SRD

SF/BD

RESET

SLEEP

DV_DD

INTR

TC

DBUS0

DV_SS

DBUS1

DBUS2

DBUS3

DBUS4

DV_SS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

74 XTAL2

73 AV_SS

72 XTAL1

71 AV_DD

70 TXD+

69 TXP+

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

68

TXD-

67

TXP-

66

AV_DD

Am79C940JC

MACE

65

RXD+

64

RXD-

63

DV_DD

62

TDI

61

DV_SS

60

TCK

59

TMS

58

TDO

57

LNKST

56

RXPOL

55

CS

RW/

54

35

39

43 44

48

49

52 53

50 51

33

37 38

41 42

45 46 47

36

40

34

16235D-2

Am79C940

7

CONNECTION DIAGRAMS

PQR100

PQFP PACKAGE

NC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

AV_SS

NC

XTAL2

AV_SS

XTAL1

AV_DD

TXD+

TXP+

TXD

NC

SRDCLK

EAM/R

SRD

SF/BD

RESET

SLEEP

DV_DD

INTR

TC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

TXP

AV_DD

RXD+

RXD

DBUS0

DV_SS

MACE

Am79C940KC

DBUS1

DBUS2

DBUS3

DBUS4

DV_SS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

NC

DV_DD

TDI

DV_SS

TCK

TMS

TDO

LNKST

RXPOL

CS

R/W

NC

DBUS10

NC

16235D-3

8

Am79C940

CONNECTION DIAGRAMS

PQT080

TQFP PACKAGE

80 79 78 77 76 757473 72 717069 68 67 65 64 63 62 61

66

SRDCLK

EAM/R

SF/BD

1

2

3

4

60

59

58

57

XTAL2

AV_SS

XTAL1

AV^DD

RESET

SLEEP

DV

DD

5

6

56

55

TXD+

TXP+

INTR

TC

7

8

9

10

11

12

13

54

53

52

51

50

49

48

TXD-

TXP-

AV_DD

DBUS0

DV_SS

DBUS1

DBUS2

DBUS3

RXD+

RXD-

DV_DD

TDI

MACE

Am79C940VC

DV_SS

TCK

TMS

TD0

LNKST

CS

DBUS4

DV_SS

14

15

16

17

18

19

20

47

46

45

44

43

42

41

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

R/W

21 22 23 24 25 262728 29 303132 33 34 36 37 38 39 40

35

16235D-4

Notes: Four pin functions available on the PLCC and PQFP packages are not available with the TQFP package.

(See full data sheet for description of pins not included with the 80-pin TQFP package. In particular, see section

“Pin Functions not available with the 80-pin TQFP package.”)

Am79C940

9

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

AM79C940

V

C

\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and Formed in a Tray

OPTIONAL PROCESSING

Blank

=

Standard Processing

TEMPERATURE RANGE

C

I

=

Commercial (0° to +70°C)

Industrial (-40°C to +85°C)

PACKAGE TYPE (per Prod. Nomenclature/16-038)

J

K

V

=

84-Pin Plastic Leaded Chip Carrier (PL 084)

100-Pin Plastic Quad Flat Pack (PQR100)

80-Pin Thin Quad Flat Package (PQT080)

SPEED

Not Applicable

DEVICE NUMBER/DESCRIPTION (include revision letter)

Am79C940

Media Access Controller for Ethernet

Valid Combinations

The Valid Combinations table lists configurations planned to

be supported in volume for this device. Consult the local AMD

sales office to confirm availability of specific valid

JC, KC,

KC\W, VC,

VC\W

AM79C940

combinations and to check on newly released combinations.

JI, KI,

AM79C940

KI\W, VI,

VI\W

Note:

Currently the silicon revision level of the MACE Ethernet controller is revision C0. This is designated by the marking on the package

as Am79C940Bxx, where “xx” indicate package type and temperature range.

10

Am79C940

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature . . . . . . . . . . . . -65°C to +150°C

Commercial (C) Devices

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .

Under Bias . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (T_A) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Supply Voltage to AVSS

or DVss (AVDD, DVDD). . . . . . . . . . .-0.3 V to +6.0 V

Ambient Temperature (T_A) . . . . . . . . .–40°C to +85°C

V_CCSupply Voltages

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to Absolute Max-

imum Ratings for extended periods may affect device reliabil-

ity. Programming conditions may differ.

. . . . . . . . . . . . . . . . . . . . . . (AVDD, DVDD) 5 V 5%

All inputs within the range: . . AVDD – 0.5 V ≤ Vin ≤

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS + 0.5 V, or

. . . . . . . . . . . . . . . . . . . . . . . . . DV_DD– 0.5 V ≤ Vin ≤

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DV_SS+ 0.5 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

DC CHARACTERISTICS (Unless otherwise noted, parametric values are the same

between Commercial devices and Industrial devices.)

Parameter

Symbol

Parameter Description

Input LOW Voltage

Test Conditions

Min

Max

Unit

V

V_IL

0.8

V_IH

Input HIGH Voltage

2.0

V

XTAL1 Input LOW Voltage

(External Clock Signal)

XTAL1 Input HIGH Voltage

(External Clock Signal)

Output LOW Voltage

V_SS= 0.0 V

V_ILX

V_IHX

–0.5

0.8

V

V_SS= 0.0 V

V_DD–

0.8

V_DD+

0.5

V_OL

V_OH

I_OL= 3.2 mA

0.45

V

Output HIGH Voltage

I_OH= -0.4 mA (Note 1)

2.4

V

_DD= 5 V, V_IN= 0 V

(Note 2)

_DD= 5 V, V_IN= 0 V

(Note 2)

_DD= 5 V, V_IN= 2.7 V

I_IL1

I_IL2

Input Leakage Current

–10

10

µA

mV

V

–200

200

V

I_IH

–100

+500

(Note 3)

Input Current at DI+

and DI–

I_IAXD

I_IAXC

I_ILXN

I_IHXN

I_ILXS

I_IHXS

I_OZ

–1 V < V_IN< AV_DD+ 0.5 V

–500

Input Current at CI+

and CI–

–1 V < V_IN< AV_DD+ 0.5 V

XTAL1 Input LOW Current

during normal operation

XTAL1 Input HIGH Current

during normal operation

XTAL1 Input LOW Current

during Sleep

V_IN= 0 V

–92

(Note 9)

SLEEP = HIGH

V_IN= 5.5 V

92

(Note 10)

SLEEP = HIGH

V_IN= 0 V

<10

410

10

SLEEP = LOW

V_IN= 5.5 V

XTAL1 Input HIGH Current

during Sleep

SLEEP = LOW

0.4 V < V_OUT< V_DD

(Note 4)

Output Leakage Current

–10

630

–40

Differential Output Voltage

|(DO+)–(DO–)|

V_AOD

V_AODOFF

R_L= 78 Ω

1200

+40

Transmit Differential Output

Idle Voltage

R_L= 78 Ω (Note 5)

90

DC CHARACTERISTICS (Continued)

Parameter

Symbol

Parameter Description

Transmit Differential

Output Idle Current

DO Common Mode

Output Voltage

Test Conditions

R_L= 78 Ω

Min

Max

Unit

I_AODOFF

–1

+1

mA

V_AOCM

R_L= 78 Ω

2.5

–25

AVDD

25

V

DO Differential Output

Voltage Imbalance

V_OD

V_ATH

V_ASQ

I

R_L= 78 Ω (Note 6)

mV

V

Receive Data Differential

Input Threshold

–35

35

DI and CI Differential

Input Threshold Squelch

DI and CI Differential

Mode Input Voltage Range

DI and CI Input Bias

Voltage

–160

–275

1.5

V_IRDVD

V_ICM

I

_IN= 0 mA

AV_DD–3.0

AV_DD–0.8

–100

V

V_OPD

(Note 5)

mV

DI Undershoot Voltage at Zero

Differential on Transmit Return

to Zero (ETD)

SCLK = 25 MHz

I_DD

Power Supply Current

75

100

10

mA

µA

XTAL1 = 20 MHz

SLEEP Asserted, AWAKE = 0

RWAKE = 1 (Note 7)

I_DDSLEEP

SLEEP Asserted, AWAKE = 1

RWAKE = 0 (Note 7)

mA

SLEEP Asserted, AWAKE = 0

RWAKE = 1 (Note 7)

20

Twisted Pair Interface

I_IRXD

Input Current at RXD

AV_SS< V_IN< AV_DD

(Note 8)

–500

10

500

µA

RXD Differential Input

Resistance

R_RXD

KΩ

RXD , RXD– Open Circuit

Input Voltage (Bias)

Differential Mode Input

Voltage Range (RXD )

RXD Positive Squelch

Threshold (Peak)

V_TIVB

V_TIDV

I_IN= 0 mA

AV_DD–3.0

–3.1

300

AV_DD–1.5

+3.1

V

AV_DD= +5V

V

Sinusoid

V_TSQ+

V_TSQ–

V_THS+

V_THS–

V_LTSQ+

V_LTSQ–

V_LTHS+

520

mV

5 MHz ≤ f ≤10 MHz

Sinusoid

RXD Negative Squelch

Threshold (Peak)

–520

150

–300

293

5 MHz ≤ f ≤10 MHz

Sinusoid

RXD Post-Squelch

Positive Threshold (Peak)

RXD Post-Squelch

5 MHz ≤ f ≤10 MHz

Sinusoid

–293

180

–150

312

Negative Threshold) (Peak)

RXD Positive Squelch

Threshold (Peak)

5 MHz ≤ f ≤10 MHz

LRT = LOW

RXD Negative Squelch

Threshold (Peak)

–312

90

–180

156

RXD Post-Squelch Positive

Threshold (Peak)

91

DC CHARACTERISTICS (Continued)

Parameter

Symbol

V_LTHS–

V_RXDTH

V_TXH

Parameter Description

RXD Post-Squelch

Test Conditions

LRT = LOW

Min

–156

Max

–90

Unit

mV

V

Negative Threshold (Peak)

RXD Switching Threshold

(Note 4)

–35

35

TXD and TXD Output

HIGH Voltage

DV_SS= 0V

DV_DD–0.6

DV_DD

TXD and TXD Output

LOW Voltage

V_TXL

DV_DD= +5V

DV_SS

–40

DV_SS+ 0.6

V

TXD and TXD Differential

Output Voltage Imbalance

V_TXI

V_TXOFF

R_TX

+40

40

mV

Ω

TXD and TXD Idle Output

Voltage

DV_DD= +5V

(Note 8)

TXD Differential Driver Output

Impedance

40

TXD Differential Driver Output

Impedance

(Note 8)

80

Ω

Notes:

1. V_OHdoes not apply to open-drain output pins.

2. I_IL1and I_IL2applies to all input only pins except DI , CI , and XTAL1.

I_IL1= ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.

I_IL2= TC, TDI, TCK, TMS.

3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.

4. I_OZapplies to all three-state output pins and bi-directional pins.

5. Test not implemented to data sheet specification.

6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.

7. During the activation of SLEEP:

–The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR

and TDO.

–The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:

DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.

–The following input pin has its internal pull-up and TTL level translator disabled: TC.

–The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,

R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R.

–The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+

and DO.

–The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.

–AWAKE and RWAKE are reset to zero. I_DDSLEEP,with either AWAKE set or RWAKE set, will be much higher and its

value remains to be determined.

8. Parameter not tested.

9. For industrial temperature version, Max value is –150 µA.

10. For industrial temperature version, Max value is +150 µA.

92

AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same

between Commercial devices and Industrial devices.)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

Clock and Reset Timing

1

2

3

4

5

6

7

t_SCLK

t_SCLKL

t_SCLKH

t_SCLKR

t_SCLKF

t_RST

SCLK period

40

1000

SCLK LOW pulse width

SCLK HIGH pulse width

SCLK rise time

0.4*t_SCLK

0.6*t_SCLK

5

SCLK fall time

RESET pulse width

15*t_SCLK

99

t_BT

Network Bit Time (BT)=2*tX1 or tSTDC

101

Internal MENDEC Clock Timing

9

t_X1

XTAL1 period

49.995

20

50.005

11

12

13

14

t_X1H

t_X1L

t_X1R

t_X1F

XTAL1 HIGH pulse width

XTAL1 LOW pulse width

XTAL1 rise time

20

5

XTAL1 fall time

BIU TIMING (Note 1)

31

32

t_ADDS

t_ADDH

Address valid setup to SCLK↓

Address valid hold after SCLK↓

CS or FDS and TC, BE1–0,

9

2

1. 33

t_SLVS

t_SLVH

9

2

R/W setup to SCLK↓

CS or FDS and TC, BE1–0,

34

R/W hold after SCLK↓

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

t_DATD

t_DATH

t_DTVD

t_DTVH

t_EOFD

t_EOFH

t_CSIS

Data out valid delay from SCLK↓

Data out valid hold from SCLK↓

DTV valid delay from SCLK↓

DTV valid hold after SCLK↓

C_L= 100 pF (Note 2)

32

6

EOF valid delay from SCLK↓

EOF output valid hold after SCLK↓

CS inactive prior to SCLK↓

6

9

2

t_EOFS

t_EOFH

t_RDTD

t_RDTH

t_TDTD

t_TDTH

t_DATS

t_DATIH

EOF input valid setup to SCLK↓

EOF input valid hold after SCLK↓

RDTREQ valid delay from SCLK↓

RDTREQ input valid hold after SCLK↓

TDTREQ valid delay from SCLK↓

TDTREQ input valid hold after SCLK↓

Data in valid setup to SCLK↓

Data in valid setup after SCLK↓

C_L= 100 pF (Note 2)

32

6

9

2

Data output enable delay from SCLK↓ (Note

50

t_DATE

t_DATD

0

3)

Data output disable delay from SCLK↓ (Note

3, 4)

51

25

Notes:

1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge

of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ↑).

2. Tested with C_Lset at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay

vs. Load Chart.

3. Guaranteed by design–not tested.

4. t_DATDis defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.

93

AC CHARACTERISTICS (continued)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

AUI Timing

53

54

55

56

57

58

t_DOTD

t_DOTR

XTAL1 (externally driven) to DO ουτπυτ

DO rise time (10% to 90%)

DO fall time (10% to 90%)

DO rise and fall mismatch

DO End of Transmit Delimiter

DI pulse width to reject

100

5.0

1

2.5

t_DOTF

t_DOETM

t_DOETD

t_PWRDI

200

375

15

|input| > |_VASQ

|

DI pulse width to turn on internal DI carrier

sense

59

60

61

t_PWODI

t_PWMDI

t_PWKDI

|input| > |_VASQ

|

45

DI pulse width to maintain internal DI carrier

sense on

|

136

DI pulse width to turn internal DI carrier

sense off

|input| > |_VASQ

200

62

63

t_PWRCI

t_PWOCI

CI pulse width to reject

|

10

90

CI pulse width to turn on internal SQE sense |input| > |_VASQ

26

CI pulse width to maintain internal SQE

|input| > |_VASQ

64

t_PWMCI

|

sense on

65

66

67

79

80

t_PWKCI

t_SQED

t_SQEL

t_CLSHI

t_TXH

CI pulse width to turn internal SQE sense off |input| > |_VASQ

|

160

CI SQE Test delay from O inactive

CI SQE Test length

|input| > |_VASQ

CLSN high time

t_STDC+ 30

32*t_STDC

TXEN or DO hold time from CLSN↑

|input| > |_VASQ

|

96*t_STDC

DAI Port Timing

70

72

80

t_TXEND

t_TXDD

t_TXH

STDCLK↑ delay to TXEN↓

C_L= 50 pF

70

STDCLK↑ delay to TXDAT change

TXEN or TXDAT hold time from CLSN↑

32*t_STDC

96*t_STDC

Mismatch in STDCLK ≠ to TXEN↓ and

TXDAT change

95

t_DOTF

15

96

97

t_TXDTR

t_TXDTF

TXDAT rise time

See Note 1

5

TXDAT fall time

5

98

t_TXDTM

TXDAT rise and fall mismatch

TXEN End of Transmit Delimiter

First RXDAT↓ delay to RXCRS↑

Last RXDAT ≠ delay to RXCRS↓

RXCRS↑ delay to CLSN↑ (TXEN = 0)

1

99

t_TXENETD

t_FRXDD

250

350

100

120

100

101

102

t_LRXDD

t_CRSCLSD

94

AC CHARACTERISTICS (continued)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

GPSI Clock Timing

17

t_STDC

STDCLK period

99

45

101

18

t_STDCL

t_STDCH

t_STDCR

t_STDCF

t_SRDC

STDCLK low pulse width

STDCLK high pulse width

STDCLK rise time

See Note 1

19

20

See Note 1

5

21

STDCLK fall time

22

SRDCLK period

85

38

115

23

t_SRDCH

t_SRDCL

t_SRDCR

t_SRDCF

SRDCLK HIGH pulse width

SRDCLK LOW pulse width

SRDCLK rise time

24

25

See Note 1

5

26

SRDCLK fall time

GPSI Timing

70

71

72

73

74

75

t_TXEND

t_TXENH

t_TXDD

t_TXDH

t_RXDR

t_RXDF

STDCLK↑ delay to TXEN↑

(C_L= 50 pF)

70

TXEN hold time from STDCLK↑

5

STDCLK↑ delay to TXDAT+ change (C_L= 50 pF)

TXDAT+ hold time from STDCLK↑ (C_L= 50 pF)

RXDAT rise time

RXDAT fall time

See Note 1

8

RXDAT hold time (SRDCLK↑ to

76

77

t_RXDH

t_RXDS

25

0

RXDAT change)

RXDAT setup time (RXDAT stable

to SRDCLK↑)

78

79

t_CRSL

t_CLSHI

RXCRS low time

CLSN high time

t_STDC+ 20

t_STDC+ 30

TXEN or TXDAT hold time from

CLSN↑

80

t_TXH

32*t_STDC

0

96*t_STDC

81

t_CRSH

RXCRS hold time from SRDCLK↑

EADI Feature Timing

85

86

t_DSFBDR

t_DSFBDF

SRDCLK↓ delay to SF/BD↑

20

EAM/R invalid setup prior to

SRDCLK↓ after SFD

87

t_EAMRIS

–150

0

EAM setup to SRDCLK↓ at bit 6 of

Source Address byte 1 (match

packet)

88

t_EAMS

89

90

t

_EAMRL

EAM/R low time

200

100

SF/BD high hold from last

SRDCLK↓

t_SFBDHIH

EAR setup SRDCLK↓ at bit 6 of

message byte 64

91

t_EARS

0

(reject normal packet)

Note:

1. Not tested but data available upon request.

95

AC CHARACTERISTICS (continued)

Parameter

No.

Parameter Description

Test Conditions

Min

Max

Symbol

IEEE 1149.1 Timing

109

t_TCLK

TCK Period, 50% duty cycle (+5%)

100

110

111

112

113

114

115

t_su1

t_su2

t_hd1

t_hd2

t_d1

TMS setup to TCK↑

8

5

TDI setup to TCK↑

TMS hold time from TCK↑

TDI hold time from TCK↑

TCK↓ delay to TDO

5

10

30

35

t_d2

TCK↓ delay to SYSTEM OUTPUT

10BASE–T Transmit Timing

Min

Max

350

5.5

1

125

126

127

128

129

130

131

132

133

134

135

136

t_TETD

t_TR

Transmit Start of Idle

250

Transmitter Rise Time

(10% to 90%)

(90% to 10%)

t_TF

Transmitter Fall Time

t_TM

Transmitter Rise and Fall Time Mismatch

XMT# Asserted Delay

t_XMTON

t_XMTOFF

t_PERLP

t_PWLP

t_PWPLP

t_JA

100

TBD

24

XMT# De-asserted Delay

Idle Signal Period

TBD

8

Idle Link Pulse Width

(Note 1)

75

120

55

Predistortion Idle Link Pulse Width

Transmit Jabber Activation Time

Transmit Jabber Reset Time

45

20

150

750

t_JR

250

1.0

t_JREC

Transmit Jabber RecoveryTime(Minimum

TimeGapBetweenTransmittedPacketsto

Prevent Jabber Activation)

10BASE–T Receive Timing

RXD Pulse Width Not to Turn Off Internal VIN > VTHS

140

141

t_PWNRD

136

200

–

Carrier Sense

(min)

RXD Pulse Width to Turn Off VIN> VTHS

(min)

t_PWROFF

142

143

144

t_RETD

t_RCVON

t_RCVOFF

Receive Start of Idle

200

t_RON– 50

TBD

RCV# Asserted Delay

RCV# De-asserted Delay

t_RON– 100

TBD

Note:

1. Not tested but data available upon request.

96


型号：	AM79C940B-25JC-G
厂家：	Rochester Electronics
描述：	LAN Controller, CMOS 局域网
文件：	总14页 (文件大小：528K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM79C940B-25JC-G [ROCHESTER]

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