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CD74HC112EE4 [ROCHESTER]

J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16;
CD74HC112EE4
型号： CD74HC112EE4
厂家： Rochester Electronics    Rochester Electronics
描述：

J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16

光电二极管 逻辑集成电路 触发器
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CD54HC112, CD74HC112,  
CD54HCT112, CD74HCT112  
Data sheet acquired from Harris Semiconductor  
SCHS141H  
Dual J-K Flip-Flop with Set and Reset  
Negative-Edge Trigger  
March 1998 - Revised October 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The ’HC112 and ’HCT112 utilize silicon-gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC112  
,
CD74  
HCT11  
2)  
• Asynchronous Set and Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Set, Reset, and  
Clock inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Set and Reset  
are accomplished asynchronously by low-level inputs.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Fanout (Over Temperature Range)  
The HCT logic family is functionally as well as pin-  
compatible with the standard LS logic family.  
/Sub-  
ject  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
.
(Dual  
J-K  
Flip-  
Flop  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC112F3A  
CD54HCT112F3A  
CD74HC112E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
with  
• HC Types  
Setand  
Reset  
Nega-  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC112MT  
CD74HC112M96  
CD74HC112NSR  
CD74HC112PW  
CD74HC112PWR  
CD74HC112PWT  
CD74HCT112E  
16 Ld SOIC  
at V  
= 5V  
CC  
16 Ld SOIC  
• HCT Types  
16 Ld SOP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
Pinout  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CD54HC112, CD54HCT112 (CERDIP)  
CD74HC112 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT112 (PDIP)  
TOP VIEW  
1CP  
1K  
1
2
3
4
5
6
7
8
16 V  
CC  
15 1R  
14 2R  
13 2CP  
12 2K  
11 2J  
10 2S  
1J  
1S  
1Q  
1Q  
2Q  
9
2Q  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112  
Functional Diagram  
4
1S  
3
2
5
6
1J  
1Q  
1Q  
F/F 1  
1K  
1
1CP  
1R  
15  
10  
2S  
11  
12  
9
7
2J  
2Q  
2Q  
F/F 2  
2K  
13  
14  
2CP  
2R  
GND = 8  
= 16  
V
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
S
L
R
H
L
CP  
X
X
X
↓
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
H
L
L
H (Note 1)  
H (Note 1)  
H
H
H
H
H
H
H
No Change  
↓
H
L
L
H
L
L
↓
H
H
H
H
H
X
H
↓
H
X
Toggle  
No Change  
H
H= High Level (Steady State)  
L= Low Level (Steady State)  
X= Don’t Care  
↓
= High-to-Low Transition  
NOTE:  
1. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.  
2
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 2):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W  
D (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W  
Maximum Junction Temperature (Hermetic Package or Die) . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
I
I
CC  
o
DC Drain Current, per Output, I  
O
o
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
o
DC Output Diode Current, I  
OK  
For V < -0.5V or V > V  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
o
DC Output Source or Sink Current per Output Pin, I  
O
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time, t , t  
r
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
0.02  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
-
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
4
-
40  
-
80  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
V
V
or  
IH  
-0.02  
4.5  
4.4  
4.4  
4.4  
OH  
V
IL  
CMOS Loads  
High Level Output  
Voltage  
-4  
4.5  
3.98  
-
-
3.84  
-
3.7  
-
V
TTL Loads  
Low Level Output  
Voltage CMOS Loads  
V
V
V
or  
IH  
0.02  
4
4.5  
4.5  
-
-
-
-
0.1  
-
-
0.1  
-
-
0.1  
0.4  
V
V
OL  
IL  
Low Level Output  
Voltage  
0.26  
0.33  
TTL Loads  
Input Leakage  
Current  
I
V
and  
GND  
-
5.5  
5.5  
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
4
-
-
40  
-
-
80  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 3)  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
3. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
1S, 2S  
UNIT LOADS  
0.5  
0.6  
0.65  
1
1K, 2K  
1R, 2R  
1J, 2J, 1CP, 2CP  
NOTE: Unit Load is ∆I  
CC  
tions table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical Specifica-  
o
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
Pulse Width CP  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
t
-
2
80  
16  
14  
-
-
-
-
-
-
100  
20  
-
-
-
120  
24  
-
-
-
ns  
ns  
ns  
W
4.5  
6
17  
20  
4
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
Pulse Width R, S  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
100  
20  
17  
100  
20  
17  
0
MAX  
MIN  
120  
24  
20  
120  
24  
20  
0
MAX  
UNITS  
ns  
t
-
-
-
-
-
2
4.5  
6
80  
16  
14  
80  
16  
14  
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W
ns  
ns  
Setup Time J, K, to CP  
Hold Time J, K, to CP  
Removal Time R to CP, S to CP  
CP Frequency  
t
2
ns  
SU  
4.5  
6
ns  
ns  
t
2
ns  
H
4.5  
6
0
0
0
ns  
0
0
0
ns  
t
2
80  
16  
14  
6
100  
20  
17  
5
120  
24  
20  
4
ns  
REM  
4.5  
6
ns  
ns  
f
2
MHz  
MHz  
MHz  
MAX  
4.5  
6
30  
35  
25  
29  
20  
23  
HCT TYPES  
Pulse Width CP  
t
-
-
-
-
-
-
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
16  
18  
16  
3
-
-
-
-
-
-
-
-
-
-
-
-
20  
23  
20  
3
-
-
-
-
-
-
24  
27  
24  
3
-
-
-
-
-
-
ns  
ns  
SU  
Pulse Width R, S  
t
W
Setup Time J, K, to CP  
Hold Time J, K, to CP  
Removal Time R to CP, S to CP  
CP Frequency  
t
ns  
H
t
f
ns  
REM  
t
20  
30  
25  
25  
30  
20  
ns  
W
MHz  
MAX  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
MIN TYP MAX  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
CP to Q, Q  
t
t
t
, t  
C = 50pF  
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175  
35  
-
-
-
-
-
-
-
-
-
-
-
-
-
220  
44  
-
-
-
-
-
-
-
-
-
-
-
-
-
265  
53  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH PHL  
L
C = 50pF  
L
C = 15pF  
14  
-
L
C = 50pF  
6
30  
155  
31  
-
37  
195  
39  
-
45  
235  
47  
-
L
Propagation Delay,  
S to Q, Q  
, t  
PLH PHL  
C = 50pF  
2
-
L
C = 50pF  
4.5  
5
-
L
C = 15pF  
13  
-
L
C = 50pF  
6
26  
180  
36  
-
33  
225  
45  
-
40  
270  
54  
-
L
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
C = 50pF  
2
-
L
C = 50pF  
4.5  
5
-
L
C = 15pF  
15  
-
L
C = 50pF  
6
31  
38  
46  
L
5
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
95  
19  
16  
10  
-
MIN  
MAX  
110  
22  
19  
10  
-
UNITS  
ns  
Output Transition Time  
t
, t  
TLH THL  
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
-
-
75  
15  
13  
10  
-
-
-
-
-
-
-
-
-
-
-
-
-
L
C = 50pF  
ns  
L
C = 50pF  
L
-
ns  
Input Capacitance  
CP Frequency  
C
-
-
-
pF  
I
f
C
= 15pF  
-
5
60  
12  
MHz  
pF  
MAX  
L
Power Dissipation Capacitance  
(Notes 4, 5)  
C
5
-
-
-
PD  
HCT TYPES  
Propagation Delay,  
CP to Q, Q  
t
t
t
, t  
C = 50pF  
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
14  
-
35  
-
-
-
-
-
-
-
-
-
-
-
44  
-
-
-
-
-
-
-
-
-
-
-
53  
-
ns  
ns  
PLH PHL  
L
C
= 15pF  
L
Propagation Delay,  
S to Q, Q  
, t  
PLH PHL  
C = 50pF  
4.5  
5
32  
-
40  
-
48  
-
ns  
L
C
= 15pF  
13  
-
ns  
L
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
C = 50pF  
4.5  
5
37  
-
46  
-
56  
-
ns  
L
C
= 15pF  
14  
-
ns  
L
Output Transition Time  
Input Capacitance  
CP Frequency  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
15  
10  
-
19  
10  
-
22  
10  
-
ns  
C
-
-
pF  
MHz  
pF  
I
f
CL = 15pF  
-
5
60  
20  
MAX  
Power Dissipation Capacitance  
(Notes 4, 5)  
C
5
-
-
-
PD  
NOTES:  
4. C  
is used to determine the dynamic power consumption, per flip-flop.  
2
PD  
5. P = C  
V
f + Σ C f where f = input frequency, f = output frequency, C = output load capacitance, V  
= supply voltage.  
D
PD CC  
i
L o  
i
o
L
CC  
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
f
t C  
f
L
CL  
r
L
3V  
V
CC  
90%  
10%  
2.7V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
0.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
6
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112  
Test Circuits and Waveforms (Continued)  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
PACKAGING INFORMATION  
Orderable Device  
5962-8970201EA  
CD54HC112F3A  
CD54HCT112F3A  
CD74HC112E  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
CDIP  
CDIP  
CDIP  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
J
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
1
TBD  
TBD  
TBD  
A42  
N / A for Pkg Type  
5962-8970201EA  
CD54HCT112F3A  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
1
A42  
N / A for Pkg Type  
8408801EA  
CD54HC112F3A  
1
A42  
N / A for Pkg Type  
5962-8970201EA  
CD54HCT112F3A  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
N / A for Pkg Type  
CD74HC112E  
CD74HC112E  
HC112M  
HC112M  
HC112M  
HC112M  
HC112M  
HC112M  
HC112M  
HC112M  
HC112M  
HJ112  
CD74HC112EE4  
CD74HC112M96  
CD74HC112M96E4  
CD74HC112M96G4  
CD74HC112MT  
N
25  
Pb-Free  
(RoHS)  
N / A for Pkg Type  
D
2500  
2500  
2500  
250  
250  
250  
2000  
2000  
2000  
90  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
CD74HC112MTE4  
CD74HC112MTG4  
CD74HC112NSR  
CD74HC112NSRE4  
CD74HC112NSRG4  
CD74HC112PW  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
NS  
NS  
NS  
PW  
PW  
PW  
Green (RoHS  
& no Sb/Br)  
SO  
Green (RoHS  
& no Sb/Br)  
SO  
Green (RoHS  
& no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
Green (RoHS  
& no Sb/Br)  
CD74HC112PWE4  
CD74HC112PWG4  
90  
Green (RoHS  
& no Sb/Br)  
HJ112  
90  
Green (RoHS  
& no Sb/Br)  
HJ112  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
CD74HC112PWR  
CD74HC112PWRE4  
CD74HC112PWRG4  
CD74HC112PWT  
CD74HC112PWTE4  
CD74HC112PWTG4  
CD74HCT112E  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PDIP  
PW  
16  
16  
16  
16  
16  
16  
16  
16  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
N / A for Pkg Type  
HJ112  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PW  
PW  
PW  
PW  
PW  
N
2000  
2000  
250  
250  
250  
25  
Green (RoHS  
& no Sb/Br)  
HJ112  
Green (RoHS  
& no Sb/Br)  
HJ112  
Green (RoHS  
& no Sb/Br)  
HJ112  
Green (RoHS  
& no Sb/Br)  
HJ112  
Green (RoHS  
& no Sb/Br)  
HJ112  
Pb-Free  
(RoHS)  
CD74HCT112E  
CD74HCT112E  
CD74HCT112EE4  
PDIP  
N
25  
Pb-Free  
(RoHS)  
N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF CD54HC112, CD54HCT112, CD74HC112, CD74HCT112 :  
Catalog: CD74HC112, CD74HCT112  
•
Military: CD54HC112, CD54HCT112  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Military - QML certified for Military and Defense Applications  
•
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CD74HC112M96  
CD74HC112NSR  
CD74HC112PWR  
CD74HC112PWT  
SOIC  
SO  
D
16  
16  
16  
16  
2500  
2000  
2000  
250  
330.0  
330.0  
330.0  
330.0  
16.4  
16.4  
12.4  
12.4  
6.5  
8.2  
6.9  
6.9  
10.3  
10.5  
5.6  
2.1  
2.5  
1.6  
1.6  
8.0  
12.0  
8.0  
16.0  
16.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
NS  
PW  
PW  
TSSOP  
TSSOP  
5.6  
8.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CD74HC112M96  
CD74HC112NSR  
CD74HC112PWR  
CD74HC112PWT  
SOIC  
SO  
D
16  
16  
16  
16  
2500  
2000  
2000  
250  
333.2  
367.0  
367.0  
367.0  
345.9  
367.0  
367.0  
367.0  
28.6  
38.0  
35.0  
35.0  
NS  
PW  
PW  
TSSOP  
TSSOP  
Pack Materials-Page 2  
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