CLC420AJE-TR13 [ROCHESTER]
Operational Amplifier, 1 Func, 2000uV Offset-Max, PDSO8, PLASTIC, SOIC-8;
| 型号： | CLC420AJE-TR13 |
| 厂家： | 
Rochester Electronics |
| 描述： | Operational Amplifier, 1 Func, 2000uV Offset-Max, PDSO8, PLASTIC, SOIC-8 放大器 光电二极管 |
| 文件： | 总12页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 15, 2009
CLC420
High Speed, Voltage Feedback Op Amp
General Description
Applications
The CLC420 is an operational amplifier designed for applica-
tions requiring matched inputs, integration or transimpedance
amplification. Utilizing voltage feedback architecture, the
CLC420 offers a 300MHz bandwidth, a 1100V/µs slew rate
and a 4mA supply current (power consumption of 40mW,±5V
supplies).
Active filters/integrators
■
■
■
■
Differential amplifiers
Pin diode receivers
Log amplifiers
D/A converters
■
Photo multiplier amplifiers
Applications such as differential amplifiers will benefit from
70dB common mode rejection ratio and an input offset current
■
of 0.2µA. With its unity-gain stability, 2pA/
current noise
Non-Inverting Frequency Response
and 3µA of input bias current, the CLC420 is designed to meet
the needs of filter applications and log amplifiers. The low in-
put offset current and current noise, combined with a settling
time of 18ns to 0.01% make the CLC420 ideal for D/A con-
verters, pin diode receivers and photo multipliers amplifiers.
All applications will find 70dB power supply rejection ratio at-
tractive.
Features
300MHz small signal bandwidth
■
■
■
■
■
■
■
1100V/µs slew rate
Unity-gain stability
Low distortion, -60dBc at 20MHz
0.01% settling in 18ns
1275219
0.2µA input offset current
2pA
current noise
Connection Diagram
1275218
Pinout
DIP & SOIC
1275220
2nd and 3rd Harmonic Distortion
© 2009 National Semiconductor Corporation
12752
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Ordering Information
Package
Temperature Range
Part Number
Package Marking
NSC Drawing
Industrial
8-pin plastic DIP
−40°C to +85°C
−40°C to +85°C
CLC420AJP
CLC420AJE
CLC420AJP
CLC420AJE
CLC420AJE
N08E
M08A
8-pin plastic SOIC
CLC420AJE-TR13
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2
Differential Input Voltage
Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Solder Duration (+300°C)
10V
+150°C
−40°C to +85°C
−65°C to +150°C
10 sec
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC
IOUT
)
±7V
70mA
Operating Ratings
Thermal Resistance
(is short circuit protected to ground,
but maximum reliability will be
maintained if IOUT does not exceed
70mA, except A8D, B8D which should
not exceed 35mA over the military
temperature range)..
Package
(θJC
65°C/W
60°C/W
)
(θJA)
120°C/W
140°C/W
MDIP
SOIC
Common Mode Input Voltage
±VCC
Electrical Characteristics
AV = +1, VCC = ±5V, RL = 100Ω, Rf = 0Ω; unless specified
Symbol
Ambient Temperature
Frequency Domain Response
Parameter
Conditions
CLC420AJ
Typ
Max/Min (Note 2)
Units
+25°C
−40°C
+25°C
+85°C
SSBW
LSBW
SSBWI
LSBWI
-3dB Bandwidth
VOUT <0.4VPP
VOUT<5VPP
300
40
>200
>20
>65
>30
>200
>25
>65
>35
>130
MHz
MHz
MHz
MHz
>20
>45
>30
VOUT <0.4VPP
VOUT <5VPP
VOUT< 0.4VPP
100
60
AV =−1, Rf = 500Ω
AV = −1, Rf = 500Ω
Gain Flatness
Peaking
GFPL
GFPH
GFR
0.1MHz to 100MHz
>100MHz
0
<1
<5
<0.6
<3
<0.6
<3
dB
dB
dB
dB
Peaking
0
Rolloff
0.1MHz to 100MHz
0.1MHz to 30MHz
0.2
0.2
<1
<1
<2
GFRI
<1.4
<1.4
<1.6
Rolloff, AV = −1, Rf = 500Ω
Linear Phase Deviation
LPD
0.1MHz to 100MHz
0.9
<1.8
<1.8
<2.5
deg
Time Domain Response
TRS
TRL
TRSI
Rise and Fall Time
0.4V Step
5V Step
1.2
1.4
3.5
<2
<2
<3
ns
ns
ns
<25
<5.5
<20
<5.5
<20
<7.8
Rise and Fall Time,
0.4V Step
AV = −1, Rf = 500Ω
TRLI
TSS
TSP
OS
5V Step
2V Step
2V Step
0.4V Step
5V Step
5V Step
6
12
<10
<18
<9.5
<18
<10
<18
ns
ns
Settling Time to ±0.1%
±0.01%
18
<25
<25
<25
ns
Overshoot
8
<35
<25
<25
%
SR
Slew Rate, AV = +2
1100
750
>600
>430
>750
>500
>600
>430
V/µs
V/µs
SRI
Slew Rate, AV = −1, Rf = 500Ω
Distortion And Noise Response
HD2
HD3
HD2
2nd Harmonic Distortion
3rd Harmonic Distortion
2nd Harmonic Distortion
2VPP, 20MHz
2VPP, 20MHz
−50
−53
−51
<−40
<−45
<−40
<−40
<−45
<−40
<−40
<−40
<−40
dBc
dBc
dBc
AV = −1 2VPP, 20MHz, Rf =
500Ω
HD3
3rd harmonic distortion
−51
<−40
<−40
<−35
dBc
AV = −1, Rf = 500Ω
2VPP, 20MHz, Rf = 500Ω
Input Referred Noise
Voltage
VN
1MHz to 200MHz
1MHz to 200MHz
4.2
2
<5.3
<2.9
<5.3
<2.6
<6
nV/
pA/
ICN
Current
<2.3
3
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Symbol
Parameter
Conditions
Typ
Max/Min (Note 2)
Units
Static DC Performance
VIO
Input Offset Voltage (Note 3)
Average Temperature Coefficient
Input Bias Current (Note 3)
Average Temperature Coefficient
Input Offset Current (Note 3)
Average Temperature Coefficient
Open Loop Gain (Note 3)
1
8
<3.2
<2
-
<3.5
mV
µV/°C
µA
DVIO
IB
<15
<20
<120
<2.6
<20
>52
>55
>60
<5
<15
<10
<60
<2
3
<10
-
DIB
45
0.2
2
nA/°C
µA
IIO
<1
-
DIIO
AOL
PSRR
CMRR
ICC
<10
>56
>60
>65
<5
nA/°C
µA
65
70
80
4
>56
>60
>65
<5
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current (Note 3)
dB
dB
No Load, Quiescent
mA
Miscellaneous Performance
RIND
CIND
RINC
CINC
RO
Differential Mode Input
Common Mode Input
Resistance
Capacitance
Resistance
Capacitance
At DC
2
1
>0.5
<2
>1
<2
>1
<2
MΩ
pF
1
>0.25
<2
>0.5
<2
>0.5
<2
MΩ
pF
1
Output Impedence
0.02
±3.6
±2.9
±3.2
±60
<0.3
±2.8
±2.5
±2.5
±30
<0.2
±3
<0.2
±3
Ω
V
V
VO
Output Voltage Range
Output Voltage Range
Common Mode Input Range
Output Current
No Load
VOL
CMIR
IO
±2.5
±2.8
±50
±2.5
±2.8
±50
RL = 100Ω
For Rated Performance
V
mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25°C.
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4
Typical Performance Characteristics
Non-Inverting Frequency Response
Inverting Frequency Response
1275202
1275201
Frequency Response for Various RLS
Open Loop Gain and Phase
1275203
1275204
Bandwidth vs. Gain, Transimpedance Configuration
2nd and 3rd Harmonic Distortion
1275206
1275205
5
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2-Tone, 3rd Order Intermodulation Intercept
Equivalent Input Noise
1275207
1275208
PSRR, CMRR, and Closed Loop RO
Pulse Response
1275210
1275209
Settling Time
Long-Term Settling Time
1275211
1275212
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6
Settling Time vs. Capacitive Load
Settling Time vs. Gain
1275213
1275214
IB and IOS vs. Common-Mode Voltage
1275215
7
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Application Division
1275216
FIGURE 1. Recommended Non-Inverting Gain Circuit
1275217
FIGURE 2. Recommended Inverting Gain Circuit
Description
order amplifier poles contribute to higher closed loop band-
width. At low gains use the frequency response performance
plots given in the data sheet.
The CLC420 is a high speed, slew boosted, voltage feedback
amplifier with unity-gain stability. These features along with
matched inputs, low input bias and noise currents, and ex-
cellent CMRR render the CLC420 very attractive for active
filters, differential amplifiers, log amplifiers, and tran-
simpedance amplifiers.
Another point to remember is that the closed loop bandwidth
is determined by the noise gain, not the signal gain of the
circuit. Noise gain is the reciprocal of the attenuation in the
feedback network enclosing the op amp. For example, a
CLC420 setup as a non-inverting amplifier with a closed loop
gain of +1 (a noise gain of 1) has a 300MHz bandwidth. When
used as an inverting amplifier with a gain of −1 (a noise gain
of 2), the bandwidth is less, typically only 100MHz.
DC accuracy
Unlike current feedback amplifiers, voltage-feedback ampli-
fiers have matched inputs. This means that the non inverting
and inverting input bias current are well matched and track
over temperature, etc. As a result, by matching the resistance
looking out of the two inputs, these errors can be reduced to
a small offset current term.
Full-power bandwidth, and slew-rate
The CLC420 combines exceptional full power bandwidths
(40MHz, V0 = 5Vpp, AV = +1) and slew rates (1100V/µs, AV =
+1) with low (40mW) power consumption. These attractive
results are achieved by using slew boosting circuitry to keep
the slew rates high while consuming very little power.
Gain bandwidth product
Since the CLC420 is a voltage feedback op amp, closed loop
bandwidth is approximately equal to the gain bandwidth prod-
uct (typically 100MHz) divided by the noise gain of the circuit
(for noise gains greater than 5). At lower noise gains, higher
In non slew boosted amplifiers, full power bandwidth can be
easily determined from slew rate measurements, but in slew
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8
boosting amplifiers, such as the CLC420, you can't. For this
reason we provide data for both.
A 5kΩ feedback resistor value has been determined to pro-
vide best dynamic range based on the response of the pho-
todiode and the range of incident optical powers, etc. From
the “Transimpedance BW vs. Rf and Ci” plot, using Ci= 5pF it
is determined from the two curves labeled Ci = 5pF, that Cf =
1.5pF provides optimal compensation (no more than 0.5dB
frequency response peaking) and a −3dB bandwidth of ap-
proximately 27MHz.
Slew rate is also different for inverting and non-inverting con-
figurations. This occurs because common-mode signal volt-
ages are present in non-inverting circuits but absent in
inverting circuits. Once again data is provided for both.
Transimpedance amplifier circuits
Low inverting, input current noise (2pA/
) makes the
Printed circuit layout
CLC420 ideal for high sensitivity transimpedance amplifier
circuits for applications such as pin diode optical receivers,
and detectors in receiver IFs. However, feedback resistors
4kΩ or greater are required if feedback resistor noise current
is going to be less than the input current noise contribution of
the op amp.
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. The amplifier is sensitive to stray
capacitance to ground at the output and inverting input: Node
connections should be small with minimal coupling to the
ground plane.
With feedback resistors this large, shunt capacitance on the
inverting input of the op amp (from the pin diode, etc.) will
unacceptably degrade phase margin causing frequency re-
sponse peaking or oscillations a small valued capacitor shunt-
ing the feedback resistor solves this problem (Note: This
approach does not work for a current-feedback op amp con-
figured for transimpedance applications). To determine the
value of this capacitor, refer to the “Transimpedance BW vs.
Rf and Ci” plot.
Parasitic or load capacitance directly on the output (pin 6) will
introduce additional phase shift in the loop degrading the loop
phase margin and leading to frequency response peaking. A
small series resistor before this capacitance, if present, ef-
fectively decouples this effect. The graphs on the preceding
page, “ Settling Time vs. CL”, illustrates the required resistor
value and resulting performance vs. capacitance.
Evaluation PC boards (part no. 730013 for through-hole and
CLC730027 for SOIC) are available for the CLC420.
For example, let's assume an optical transimpedance receiv-
er is being developed. Total capacitance from the inverting
input to ground, including the photodiode and strays is 5pF.
9
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin MDIP
NS Package Number N08E
8-Pin SOIC
NS Package Number M08A
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Notes
11
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