CY29772AXIT [ROCHESTER]
200 MHz, OTHER CLOCK GENERATOR, PQFP52, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-52;
| 型号： | CY29772AXIT |
| 厂家： | 
Rochester Electronics |
| 描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP52, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-52 时钟 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：868K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29772
2.5V or 3.3V, 200-MHz, 12-Output
Zero Delay Buffer
Features
Description
• Output frequency range: 8.33 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 125 MHz
• 2.5V or 3.3V operation
The CY29772 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed
clock-distribution applications.
The CY29772 features one on-chip crystal oscillator and two
LVCMOS reference clock inputs and provides 12 outputs parti-
tioned in three banks of four outputs each. Each bank divides
the VCO output per SEL(A:C) settings, see Functional Table.
These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1,
3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces,
giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider, see Frequency Table.
• Split 2.5V/3.3V outputs
• ±2% max. Output duty cycle variation
• 7 ps RMS typical Cycle-to-cycle jitter
• 6 ps RMS typical Period jitter
• 12 clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: crystal or LVCMOS
• 300 ps max. output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9772 and MPC972
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.0-mm TQFP package
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
Sync
D
D
Q
Q
QA0
Frz
0
1
Phase
Detector
VCO
TCLK0
TCLK1
TCLK_SEL
0
1
QA1
52 51 50 49 48 47 46 45 44 43 42 41 40
LPF
QA2
VSS
QB0
VDDQB
QB1
AVSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
1
39
38
37
36
35
34
33
32
31
30
29
28
27
QA3
FB_IN
2
3
4
5
6
7
8
9
10
11
12
13
Sync
Frz
QB0
QB1
VSS
QB2
VDDQB
QB2
QB3
FB_SEL2
CY29772
QB3
FB_IN
VSS
FB_OUT
VDD
TCLK1
XIN
XOUT
AVDD
MR#/OE
Sync
Frz
D
D
Q
Q
QC0
QC1
Power-On
Reset
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
FB_SEL0
14 15 16 17 18 19 20 21 22 23 24 25 26
Sync
Frz
2
QC2
SELA(0,1)
QC3
2
2
SELB(0,1)
SELC(0,1)
0
1
Sync
Frz
FB_OUT
D
D
Q
Q
/4, /6, /8, /10
Sync Pulse
/2
Sync
Frz
2
SYNC
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
12
SDATA
INV_CLK
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 38-07572 Rev. *A
Revised September 1, 2005
CY29772
Pin Description[1]
Pin
Name
I/O
I
O
I, PU
I, PU
O
Type
Analog
Analog
Description
11
12
9
XIN
Crystal oscillator input.
Crystal oscillator output.
XOUT
TCLK0
TCLK1
LVCMOS LVCMOS/LVTTL reference clock input.
LVCMOS LVCMOS/LVTTL reference clock input.
LVCMOS Clock output bank A.
LVCMOS Clock output bank B.
LVCMOS Clock output bank C.
10
44, 46, 48, 50 QA(3:0)
32, 34, 36, 38 QB(3:0)
16, 18, 21, 23 QC(3:0)
O
O
29
31
FB_OUT
FB_IN
O
I, PU
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
LVCMOS Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference clock.
See Table 1.
25
6
SYNC
O
LVCMOS Synchronous pulse output. This output is used for system synchro-
nization.
PLL_EN
I, PU
LVCMOS PLL enable/bypass input. When Low, PLL is disabled/bypassed.
and the input clock connects to the output dividers.
2
8
7
52
MR#/OE
TCLK_SEL
REF_SEL
VCO_SEL
INV_CLK
FB_SEL(2:0)
SELA(1,0)
SELB(1,0)
SELC(1,0)
SCLK
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
I, PU
LVCMOS Master reset and Output enable/disable input. See Table 2.
LVCMOS LVCMOS Clock reference select input. See Table 2.
LVCMOS LVCMOS/LVPECL Reference select input. See Table 2.
LVCMOS VCO Operating frequency select input. See Table 2.
LVCMOS QC(2,3) Phase selection input. See Table 2.
LVCMOS Feedback divider select input. See Table 6.
LVCMOS Frequency select input, Bank A. See Table 3.
LVCMOS Frequency select input, Bank B. See Table 4.
LVCMOS Frequency select input, Bank C. See Table 5.
LVCMOS Serial Clock input.
14
5, 26, 27
42, 43
40, 41
19, 20
3
I, PU
4
SDATA
I, PU
LVCMOS Serial Data input.
45, 49
33, 37
22, 17
13
28
1
VDDQA
VDDQB
VDDQC
AVDD
VDD
AVSS
Supply
Supply
Supply
Supply
Supply
Supply
Supply
VDD
VDD
VDD
VDD
VDD
Ground
Ground
2.5V or 3.3V Power supply for bank A output clocks.[2,3]
2.5V or 3.3V Power supply for bank B output clocks.[2,3]
2.5V or 3.3V Power supply for bank C output clocks.[2,3]
2.5V or 3.3V Power supply for PLL.[2,3]
2.5V or 3.3V Power supply for core and inputs.[2,3]
Analog Ground.
15, 24, 30, 35, VSS
Common Ground.
39, 47, 51
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
Document #: 38-07572 Rev. *A
Page 2 of 12
CY29772
Table 1. Frequency Table
Feedback Output
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
Divider
VCO
÷4
÷6
÷8
÷10
÷12
÷16
÷20
÷24
÷32
÷40
Input Clock * 4
Input Clock * 6
Input Clock * 8
Input Clock * 10
Input Clock * 12
Input Clock * 16
Input Clock * 20
Input Clock * 24
Input Clock * 32
Input Clock * 40
50 MHz to 125 MHz
50 MHz to 95 MHz
33.3 MHz to 83.3 MHz
25 MHz to 62.5 MHz
20 MHz to 50 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
10 MHz to 25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
5 MHz to 12.5 MHz
33.3 MHz to 63.3 MHz
25 MHz to 47.5 MHz
20 MHz to 38 MHz
16.6 MHz to 31.6 MHz
12.5 MHz to 23.75 MHz
10 MHz to 19 MHz
8.3 MHz to 15.8 MHz
6.25 MHz to 11.8 MHz
5 MHz to 9.5MHz
Table 2. Function Table (Configuration Controls)
Control
REF_SEL
TCLK_SEL
VCO_SEL
PLL_EN
Default
0
1
Crystal oscillator
TCLK1
1
1
1
1
TCLK0, TCLK1
TCLK0
VCO÷2 (low input frequency range)
Bypass mode, PLL disabled. The input clock connects to the PLLenabled. TheVCOoutputconnects
VCO÷1 (high input frequency range)
output dividers
to the output dividers
INV_CLK
MR#/OE
1
1
QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 are inverted (180° phase
shift) with respect to QC0 and QC1
Outputsdisabled(three-state)andresetofthedevice. During Outputs enabled
reset/output disable the PLL feedback loop is open and the
VCO running at its minimum frequency. The device is reset
by the internal power-on reset (POR) circuitry during
power-up.
Table 3. Function Table (Bank A)
Table 5. Function Table (Bank C)
VCO_SEL
SELA1
SELA0
QA(0:3)
÷8
÷12
÷16
÷24
÷4
÷6
÷8
÷12
VCO_SEL
SELC1
SELC0
QC(0:3)
÷4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷8
÷12
³16
÷2
÷4
÷6
÷8
Table 4. Function Table (Bank B)
VCO_SEL
SELB1
SELB0
QB(0:3)
÷8
÷12
÷16
÷20
÷4
÷6
÷8
÷10
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Document #: 38-07572 Rev. *A
Page 3 of 12
CY29772
Table 6. Function Table (FB_OUT)
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷12
÷16
÷20
÷16
÷24
÷32
÷40
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Document #: 38-07572 Rev. *A
Page 4 of 12
CY29772
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
VOUT
VTT
LU
RPS
TS
TA
TJ
ØJC
ØJA
ESDH
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch-up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to VSS
Relative to VSS
Min.
–0.3
2.375
–0.3
–0.3
–
200
–
–65
–40
–
Max.
5.5
3.465
VDD + 0.3
VDD + 0.3
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
VDD ÷ 2
Functional
–
150
+150
+85
+150
23
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
–
–
2000
°C/W
°C/W
V
Functional
55
–
Manufacturing test
10
ppm
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
VIL Input Voltage, Low
Min.
–
1.7
–
1.8
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
5
Max.
0.7
VDD+0.3
0.6
–
–100
100
10
8
Unit
V
V
V
V
µA
µA
mA
mA
mA
pF
Ω
LVCMOS
LVCMOS
VIH
Input Voltage, High
VOL
VOH
IIL
Output Voltage, Low[4]
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
IOL = 15 mA
IOH = –15 mA
VIL = VSS
VIL = VDD
AVDD only
All VDD pins except AVDD
Outputs loaded @ 100 MHz
IIH
IDDA
IDDQ
IDD
CIN
ZOUT
–
135
4
–
–
22
14
18
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)
Parameter Description Condition
VIL Input Voltage, Low
Min.
–
2.0
–
–
2.4
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
5
Max.
0.8
VDD + 0.3
0.55
0.30
–
–100
100
10
Unit
V
V
LVCMOS
LVCMOS
VIH
VOL
Input Voltage, High
Output Voltage, Low[4]
IOL = 24 mA
OL = 12 mA
IOH = –24 mA
VIL = VSS
VIL = VDD
V
I
VOH
IIL
IIH
Output Voltage, High[4]
Input Current, Low[5]
Input Current, High[5]
PLL Supply Current
V
µA
µA
mA
mA
mA
pF
Ω
IDDA
IDDQ
IDD
CIN
AVDD only
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
All VDD pins except AVDD
Outputs loaded @ 100 MHz
–
225
4
8
–
–
18
–
12
ZOUT
15
Notes:
4. Driving one 50Ω parallel-terminated transmission line to a termination voltage of V . Alternatively, each output drives up to two 50Ω series-terminated transmis-
TT
sion lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07572 Rev. *A
Page 5 of 12
CY29772
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) [6]
Parameter
fVCO
fXTAL
fin
Description
VCO Frequency
Condition
Min.
200
10
50
33.3
25
Typ.
Max.
380
25
95
Unit
MHz
MHz
MHz
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Crystal Frequency Range
Input Frequency
See Table 7
÷4 Feedback
÷6 Feedback
÷8 Feedback
63.3
47.5
38
31.6
23.75
19
15.8
11.8
9.5
200
75
1.0
190
95
63.3
47.5
38
31.6
23.75
19
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode (PLL_EN = 0)
20
16.6
12.5
10
8.3
6.25
5
0
25
–
100
50
33.3
25
20
16.6
12.5
10
8.3
–
47.5
45
0.1
–125
frefDC
tr, tf
fMAX
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
%
ns
MHz
0.7V to 1.7V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
–
–
–
–
–
–
–
–
–
–
15.8
20
52.5
55
1.0
125
fSCLK
DC
Serial Clock Frequency
Output Duty Cycle
MHz
%
fMAX < 100 MHz
f
MAX > 100 MHz
tr, tf
t(φ)
Output Rise/Fall times
0.6V to 1.8V
TCLK to FB_IN
ns
ps
Propagation Delay
(static phase offset)
tsk(O)
Output-to-Output Skew
Skew within Bank A
Skew within Bank B
Skew within Bank C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
75
100
150
400
10
10
–
–
–
–
–
ps
tsk(B)
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
ps
ns
ns
tPLZ, HZ
tPZL, ZH
BW
PLL Closed Loop Bandwidth
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
1.3–2.0
0.7–1.3
0.9–1.3
0.6–1.1
0.6–0.9
0.4–0.6
0.6–0.9
MHz
(–3 dB)
–
–
Note:
6. AC characteristics apply for parallel output termination of 50Ω to V . Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
TT
by characterization and are not 100% tested.
Document #: 38-07572 Rev. *A
Page 6 of 12
CY29772
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) (continued)[6]
Parameter
tJIT(CC)
Description
Cycle-to-Cycle Jitter
Condition
Min.
Typ.
7
Max.
30
Unit
ps
Same frequency (125 MHz)
–
RMS (1σ)
Same frequency
Multiple frequencies
–
–
–
–
–
6
150
435
30
tJIT(PER)
Period Jitter
Same frequency (125 MHz)
ps
RMS (1σ)
Same frequency
Multiple frequencies
–
–
–
–
45
–
–
75
235
150
1
tJIT(φ)
tLOCK
I/O Phase Jitter
Maximum PLL Lock Time
ps
ms
–
AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [6]
Parameter
fVCO
fXTAL
fin
Description
VCO Frequency
Crystal Frequency Range
Input Frequency
Condition
Min.
200
10
50
33.3
25
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
500
25
125
83.3
62.5
50
41.6
31.25
25
20.8
15.625
12.5
200
75
Unit
MHz
MHz
MHz
See Table 7
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode (PLL_EN = 0)
20
16.6
12.5
10
8.3
6.25
5
0
25
–
100
50
33.3
25
20
16.6
12.5
10
8.3
–
48
45
0.1
–125
frefDC
tr, tf
fMAX
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
%
ns
MHz
0.8V to 2.0V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
1.0
200
125
83.3
62.5
50
41.6
31.25
25
20.8
20
52
55
1.0
fMAX
Maximum Output Frequency
(continued)
MHz
fSCLK
DC
Serial Clock Frequency
Output Duty Cycle
MHz
%
f
f
MAX < 100 MHz
MAX > 100 MHz
0.55V to 2.4V
tr, tf
t(φ)
Output Rise/Fall times
Propagation Delay (static phase
ns
ps
TCLK to FB_IN, same VDD
125
offset)
tsk(O)
Output-to-Output Skew
Skew within Bank A
Skew within Bank B
–
–
–
–
75
100
ps
Document #: 38-07572 Rev. *A
Page 7 of 12
CY29772
AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)[6]
Parameter
Description
Condition
Skew within Bank C
Min.
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
1.3–2.0
0.7–1.3
0.9–1.3
0.6–1.1
0.6–0.9
0.–0.6
0.6–0.9
7
Max.
Unit
150
325
8
8
–
–
–
–
–
tsk(B)
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
ps
ns
ns
tPLZ, HZ
tPZL, ZH
BW
PLL Closed-Loop Bandwidth
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
MHz
(–3 dB)
–
–
30
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
Same frequency (125 MHz)
ps
ps
RMS (1σ)
Same frequency
Multiple frequencies
–
–
–
–
–
6
100
375
30
tJIT(PER)
Same frequency (125 MHz)
RMS (1σ)
Same frequency
Multiple frequencies
I/O same VDD
–
–
–
–
45
–
–
75
225
150
1
tJIT(φ)
tLOCK
I/O Phase Jitter
Maximum PLL Lock Time
ps
ms
–
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. Figure 1 illus-
trates various waveforms for the SYNC output. Note that the
SYNC output is defined for all possible combinations of the QA
and QC outputs even though under some relationships the
lower frequency clock could be used as a synchronizing
signal.
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The CY29772 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
Document #: 38-07572 Rev. *A
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CY29772
VCO
1:1 Mode
2:1 Mode
QA
QC
SYNC
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
4:1 Mode
QA
QC
SYNC
QC
QA
SYNC
4:3 Mode
6:1 Mode
QA
QC
SYNC
QA
QC
SYNC
Figure 1.
data. An output is frozen when a logic ‘0’ is programmed and
enabled when a logic ‘1’ is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Power Management
The individual output enable/freeze control of the CY29772
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
‘0’ state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
Document #: 38-07572 Rev. *A
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CY29772
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2.
Table 7. Suggested Oscillator Crystal Parameters
Parameter Description
Frequency Tolerance
Conditions
Min.
Typ.
–
–
–
20
40
Max.
Unit
PPM
PPM
PPM/Yr
pF
T
–
–
–
–
–
±1100
± 100
5
–
80
C
S
T
Frequency Temperature Stability
Aging
Load Capacitance
(T –10° to +60°C)
(First three years @ 25°C)
The crystal’s rated load
A
T
A
C
L
R
Effective Series Resistance (ESR)
Ohm
ESR
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 4. LVCMOS Propagation Delay t(φ), Static Phase Offset
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (DC)
Document #: 38-07572 Rev. *A
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CY29772
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Figure 6. Output-to-Output Skew, tsk(O)
Ordering Information
Part Number
Package Type
Product Flow
CY29772AI
CY29772AIT
Lead-free
52-pin TQFP
52-pin TQFP – Tape and Reel
Industrial, –40°C to +85°C
Industrial,–40°C to 85°C
CY29772AXI
CY29772AXIT
52-pin TQFP
52-pin TQFP – Tape and Reel
Industrial, –40°C to +85°C
Industrial,–40°C to 85°C
Package Drawing and Dimension
52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07572 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY29772
Document History Page
Document Title:CY29772 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Document Number: 38-07572
Orig. of
REV.
ECN No. Issue Date
Change
Description of Change
**
129007
09/03/03
RGL
New Data Sheet
Added Lead-free devices
*A
395853
See ECN
RGL
Added Jitter typical specs in the features section
Document #: 38-07572 Rev. *A
Page 12 of 12
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