CY62157CV30LL-70BAIT [ROCHESTER]
512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48;
| 型号： | CY62157CV30LL-70BAIT |
| 厂家： | 
Rochester Electronics |
| 描述： | 512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157CV25/30/33
512K x 16 Static RAM
(MoBL™) in portable applications such as cellular telephones.
The devices also have an automatic power-down feature that
significantly reduces power consumption by 80% when
addresses are not toggling. The device can also be put into
standby mode reducing power consumption by more than 99%
when deselected (CE1 HIGH or CE2 LOW or both BLE and
BHE are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE1
HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE1 LOW and CE2
HIGH and WE LOW).
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62157CV25: 2.2V–2.7V
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18).
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)
• Low standby power
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip
Enable 2 (CE2) HIGH while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description[1]
The CY62157CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life™
The CY62157CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
A
A
A
A
A
10
9
8
7
6
512K × 16
5
4
3
2
RAM Array
2048 × 4096
I/O –I/O
0
7
I/O –I/O
8
15
A
A
1
0
COLUMN DECODER
BHE
WE
CE2
CE1
OE
BLE
Power-down
Circuit
CE2
CE1
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised September 24,
CY62157CV25/30/33
Product Portfolio
Power Dissipation
Operating (ICC) mA
f = 1 MHz f = fmax
Typ.[2] Max.
Standby (ISB2
)
VCC Range
Typ.[2]
Speed
µA
Product
Range
Min.
Max.
Typ.[2]
7
Max. Typ.[2] Max.
CY62157CV25
Industrial
Industrial
Industrial
Industrial
Automotive
Industrial
Industrial
Automotive
2.2V
2.5V
2.7V
55 ns
70 ns
55 ns
70 ns
70 ns
55 ns
70 ns
70 ns
1.5
1.5
1.5
1.5
3
3
3
3
15
12
15
12
6
25
5.5
7
CY62157CV30
2.7V
3.0V
3.0V
3.3V
3.3V
3.6V
8
8
25
25
70
30
30
80
5.5
8
CY62157CV33
1.5
1.5
3
3
7
15
12
10
10
10
5.5
Pin Configurations[2, 3, 4]
FBGA (Top View)
1
2
3
4
5
6
CE
A
A
A
OE
BLE
2
0
1
2
A
B
C
A
A
4
I/O BHE
8
CE
I/O
I/O
0
3
1
A
A
6
I/O I/O
I/O
2
5
9
10
1
V
A
V
I/O
I/O
3
A
CC
D
E
F
SS
7
11
17
V
SS
A
V
CC
I/O
DNU
I/O
16
12
4
A
A
15
I/O
I/O
5
I/O
I/O
14
13
14
6
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
A
NC
10
11
8
18
Pin Definitions
Name
Definition
Input
A0-A18. Address Inputs
I/O0-I/O15. Data lines. Used as input or output lines depending on operation
Input/Output
Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control CE1. Chip Enable 1, Active LOW.
Input/Control CE2. Chip Enable 2, Active HIGH.
Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
Ground
Vss. Ground for the device
Power Supply Vcc. Power supply for the device
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
3. NC pins are not connected on the die.
4. E3 (DNU) can be left as NC or V to ensure proper application.
SS
Document #: 38-05014 Rev. *E
Page 2 of 12
CY62157CV25/30/33
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current ................................................... > 200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Tempera-
Device
Range
ture[TA][6]
VCC
Supply Voltage to Ground Potential...–0.5V to Vccmax + 0.5V
CY62157CV25 Industrial
CY62157CV30 Industrial
–40°C to +85°C 2.2V – 2.7V
–40°C to +85°C 2.7V – 3.3V
DC Voltage Applied to Outputs
in High-Z State[5] ....................................–0.5V to VCC + 0.3V
DC Input Voltage[5].................................–0.5V to VCC + 0.3V
Automotive –40°C to +125°C 2.7V – 3.3V
CY62157CV33 Industrial
–40°C to +85°C 3.0V – 3.6V
Output Current into Outputs (LOW) .............................20 mA
Automotive –40°C to +125°C 3.0V – 3.6V
Electrical Characteristics Over the Operating Range
CY62157CV25-55
CY62157CV25-70
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
IOH = –0.1 mA
VCC = 2.2V
VCC = 2.2V
2.0
1.8
2.0
1.8
V
V
V
VOL
VIH
IOL = 0.1 mA
0.4
0.4
VCC
+
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.6 –0.3
0.6
+1
+1
V
Input Leakage Current
GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage Current GND < VO < VCC
,
–1
Output Disabled
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC VCC = 2.7V
7
15
3
5.5
1.5
12
3
mA
IOUT = 0 mA
f = 1 MHz
1.5
CMOS Levels
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE and BLE)
6
25
6
25
µA
ISB2
Automatic CE
CE1 > VCC – 0.2V or CE2 < 0.2V
Power-Down Current— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs f = 0, VCC = 2.7V
Electrical Characteristics Over the Operating Range
CY62157CV30-55
CY62157CV30-70
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
IOH = –1.0 mA
IOL = 2.1 mA
VCC = 2.7V
VCC = 2.7V
2.4
2.2
2.4
2.2
V
V
V
VOL
VIH
0.4
0.4
VCC
+
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
0.8
+1
V
Input Leakage Current
GND < VI < VCC Industrial
Automotive
+1
–1
–10
–1
µA
µA
µA
µA
mA
+10
+1
IOZ
ICC
Output Leakage Current GND < VO < VCC, Industrial
–1
+1
Output Disabled
Automotive
–10
+10
12
VCC Operating Supply
Current
f = fMAX = 1/tRC VCC = 3.3V
OUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
I
f = 1 MHz
1.5
3
Notes:
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
6. T is the “Instant-On” case temperature.
A
Document #: 38-05014 Rev. *E
Page 3 of 12
CY62157CV25/30/33
Electrical Characteristics Over the Operating Range (continued)
CY62157CV30-55
CY62157CV30-70
Parameter
ISB1
Description
Automatic CE
Power-Down Current— or CE2 < 0.2V
Test Conditions
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
CE1 > VCC –0.2V Industrial
8
25
8
8
25
70
µA
µA
Automotive
CMOS Inputs
VIN > VCC – 0.2V
or VIN < 0.2V,
f = fmax (Address
and Data Only),
f = 0 (OE, WE,
BHE and BLE)
ISB2
Automatic CE
Power-Down Current— or CE2 < 0.2V
CMOS Inputs IN > VCC – 0.2V
CE1 > VCC –0.2V Industrial
8
25
8
8
25
70
µA
µA
Automotive
V
or VIN < 0.2V,
f = 0, VCC = 3.3V
Electrical Characteristics Over the Operating Range
CY62157CV33-55 CY62157CV33-70
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
Parameter
VOH
Description
Test Conditions
VCC = 3.0V
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
2.4
2.4
V
V
V
VOL
VCC = 3.0V
0.4
0.4
VIH
2.2
VCC
+
2.2
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
0.8
+1
V
Input Leakage
Current
GND < VI < VCC
Industrial
+1
–1
–10
–1
µA
Automotive
+10 µA
+1 µA
IOZ
ICC
Output Leakage
Current
GND < VO < VCC, Output Industrial
Disabled
–1
+1
Automotive
–10
+10 µA
12 mA
3
VCC Operating Supply f = fMAX = 1/tRC
Current
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
f = 1 MHz
1.5
ISB1
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < Industrial
10
30
10
10
30
80
µA
µA
0.2V
Automotive
VIN > VCC – 0.2V or VIN
<
0.2V,
f = fmax (Address and Data
Only),
f = 0 (OE,WE,BHE,and
BLE)
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < Industrial
10
30
10
10
30
80
µA
µA
0.2V
Automotive
VIN > VCC – 0.2V or VIN
<
0.2V, f = 0, VCC = 3.6V
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
ΘJA
Thermal Resistance
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
°C/W
(Junction to Ambient)[7]
ΘJC
Thermal Resistance
(Junction to Case)[7]
16
°C/W
Note:
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05014 Rev. *E
Page 4 of 12
CY62157CV25/30/33
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = VCC(typ.)
Max.
Unit
pF
CIN
6
8
V
COUT
pF
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
V
Typ
OUTPUT
CC
90%
10%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
2.5V
16.6
15.4
8.0
3.0V
3.3V
1.216
1.374
0.645
1.75
Unit
R1
R2
1.105
1.550
0.645
1.75
ΚΩ
ΚΩ
ΚΩ
V
RTH
VTH
1.20
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
Min. Typ.[2] Max. Unit
VCC for Data Retention
Data Retention Current
1.5
V
VCC = 1.5V, CE1 > VCC – 0.2V or
CE2 < 0.2V,
IN > VCC – 0.2V or VIN < 0.2V
Industrial
4
4
20
60
µA
µA
Automotive
V
[8]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[8]
tR
Operation Recovery Time
tRC
Data Retention Waveform[9]
DATA RETENTION MODE
> 1.5 V
V
V
V
CC
V
CC(min.)
CC(min.)
DR
t
t
R
CDR
CE or
1
BHE.BLE
or
CE
2
Notes:
8. Full Device AC operation requires linear V ramp from V to V
> 100 µs or stable at V >100 µs.
CC(min.)
CC
DR
CC(min.)
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05014 Rev. *E
Page 5 of 12
CY62157CV25/30/33
Switching Characteristics Over the Operating Range [10]
55 ns
70 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[11]
OE HIGH to High-Z[11, 12]
CE1 LOW and CE2 HIGH to Low-Z[11]
CE1 HIGH or CE2 LOW to High-Z[11, 12]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[13]
10
10
55
25
70
35
5
10
0
5
10
0
20
20
25
25
tPD
55
55
70
70
tDBE
[11]
tLZBE
tHZBE
Write Cycle[14]
tWC
5
5
BHE/BLE HIGH to High-Z[11, 12]
20
25
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
tBW
45
50
25
0
50
60
30
0
BHE/BLE Pulse Width
tSD
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[11, 12]
WE HIGH to Low-Z[11]
tHD
tHZWE
tLZWE
20
25
5
5
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I /I and 30-pF load capacitance.
OL OH
11. At any given temperature and voltage condition, t
any given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
12. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
13. When both byte enables are toggled together this value is 10 ns.
14. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , CE = V . All signals must be ACTIVE to initiate a
1
IL
IL
2
IH
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
15. Device is continuously selected. OE, CE = V , BHE and/or BLE = V , CE = V .
IH
1
IL
IL
2
16. WE is HIGH for Read cycle.
Document #: 38-05014 Rev. *E
Page 6 of 12
CY62157CV25/30/33
Switching Waveforms (continued)
[16, 17]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZBE
BHE/BLE
t
LZBE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
VALID
NOTE 20
t
HZOE
Notes:
17. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
18. Data I/O is high-impedance if OE = V
.
IH
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
1
2
20. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05014 Rev. *E
Page 7 of 12
CY62157CV25/30/33
Switching Waveforms (continued)
[14, 18, 19]
Write Cycle No. 2 (CE1 or CE2 Controlled)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATAIN
DATA I/O
NOTE 20
t
HZOE
[19]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 20
DATAI/O
DATAIN VALID
t
LZWE
t
HZWE
Document #: 38-05014 Rev. *E
Page 8 of 12
CY62157CV25/30/33
Switching Waveforms (continued)
[19]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE1
CE
2
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DATA I/O
VALID
DATAIN
NOTE 20
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
High Z
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
)
X
L
X
X
X
X
High Z
)
X
X
X
X
H
H
High Z
)
L
H
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
H
L
H
L
Data Out (I/OO–I/O7); Read
I/O8–I/O15 in High Z
)
L
H
H
L
L
H
Data Out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
Active (ICC)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Output Disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
High Z
Output Disabled
Output Disabled
Write
)
High Z
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
)
L
H
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Document #: 38-05014 Rev. *E
Page 9 of 12
CY62157CV25/30/33
Typical DC and AC Characteristics
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.)
A
CC
CC(typ.)
Operating Current vs. Supply Voltage
14.0
12.0
10.0
14.0
12.0
10.0
14.0
12.0
10.0
MoBL
MoBL
MoBL
(f = fmax, 55ns)
(f = fmax, 55ns)
(f = fmax, 70ns)
8.0
6.0
4.0
8.0
6.0
4.0
(f = fmax, 55ns)
(f = fmax, 70ns)
8.0
6.0
4.0
(f = fmax, 70ns)
2.0
0.0
2.0
0.0
2.0
0.0
(f = 1 MHz)
(f = 1 MHz)
(f = 1 MHz)
3.0
2.7
3.3
2.7
2.2
2.5
3.3
3.0
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
10.0
MoBL
10.0
8.0
MoBL
MoBL
8.0
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.6
3.0
2.2
3.3
2.7
3.0
2.5
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
60
60
MoBL
MoBL
MoBL
50
40
30
50
40
30
50
40
30
20
20
20
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
2.7
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Document #: 38-05014 Rev. *E
Page 10 of 12
CY62157CV25/30/33
Ordering Information
Speed (ns)
Ordering Code
Package Name
Package Type
48-ball Fine-pitch BGA
Operating Range
55
CY62157CV25LL-55BAI
CY62157CV30LL-55BAI
CY62157CV33LL-55BAI
CY62157CV25LL-70BAI
CY62157CV30LL-70BAI
CY62157CV30LL-70BAE
CY62157CV33LL-70BAI
CY62157CV33LL-70BAE
BA48F
Industrial
70
Industrial
Industrial
Automotive
Industrial
Automotive
Package Diagram
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA BA48F
51-85128-*C
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05014 Rev. *E
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157CV25/30/33
Document History Page
Document Title: CY62157CV25/30/33 512K x 16 Static Ram
Document Number: 38-05014
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106184
107241
05/10/01 HRT/MGN New data sheet – Advance Information
*A
07/24/01
MGN
Made corrections to Advance Information
Added 55 ns bin
*B
*C
*D
*E
109621
114218
238448
269729
03/11/02
MGN
Changed from Advance Information to Final
05/01/02 GUG/MGN Improved Typical and Max ICC values
See ECN
See ECN
AJU
SYT
Added Automotive Product information
Added Automotive Product information for CY62157CV30 – 70 ns
Added IIX and IOZ values for Automotive range of CY62157CV33 – 70 ns
Document #: 38-05014 Rev. *E
Page 12 of 12
相关型号：
CY62157CV33LL-55BAIT
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
CY62157CV33LL-70BAI
512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
ROCHESTER
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