CY62256NL-70SNXC [ROCHESTER]
32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28;
| 型号： | CY62256NL-70SNXC |
| 厂家： | 
Rochester Electronics |
| 描述： | 32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28 静态存储器 光电二极管 |
| 文件： | 总15页 (文件大小：1260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62256N
256K (32K x 8) Static RAM
Features
Functional Description
■ Temperature Ranges
The CY62256N[1] is a high performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power down feature, reducing the power consumption
by 99.9 percent when deselected.
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
■ High Speed: 55 ns
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
■ Voltage Range: 4.5V to 5.5V Operation
■ Low Active Power
❐ 275 mW (max)
■ Low Standby Power (LL version)
❐ 82.5 μW (max)
■ Easy Memory Expansion with CE and OE Features
■ TTL-Compatible Inputs and Outputs
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Available in Pb-free and Non Pb-free 28-Pin (600-mil) PDIP,
28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin
Reverse TSOP-I Packages
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
INPUTBUFFER
A
A
A
10
9
8
A
7
6
5
A
32K x 8
ARRAY
A
A
A
A
4
3
2
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
Note
1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com
Cypress Semiconductor Corporation
Document #: 001-06511 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 03, 2009
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CY62256N
Product Portfolio
Power Dissipation
VCC Range (V)
Speed
(ns)
Operating, ICC
(mA)
Product
Standby, ISB2 (μA)
Min
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
CY62256NL
Commercial /
Industrial
4.5
5.0
5.5
70
25
50
2
50
CY62256NLL
CY62256NLL
CY62256NLL
CY62256NLL
Commercial
Industrial
70
55/70
55/70
55
25
25
25
25
50
50
50
50
0.1
0.1
0.1
0.1
5
10
10
15
Automotive-A
Automotive-E
Pin Configurations
Figure 1. 28-Pin DIP and Narrow SOIC
Figure 2. 28-Pin TSOP I and Reverse TSOP I
Table 1. Pin Definitions
Pin Number
1–10, 21, 23–26
11–13, 15–19,
27
Type
Input
Input/Output
Description
A0–A14. Address Inputs
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20
22
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input
data pins
14
28
Ground
Power Supply
GND. Ground for the device
CC. Power supply for the device
V
Note
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (T
A
= 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.
CC
Document #: 001-06511 Rev. *B
Page 2 of 14
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CY62256N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................. -55°C to +125°C
Operating Range
Range
Commercial
Industrial
Ambient Temperature (TA)[4]
VCC
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)............................................–0.5V to +7.0V
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
–40°C to +85°C
in High-Z State[3]....................................–0.5V to VCC + 0.5V
Automotive-A
Automotive-E
–40°C to +85°C
–40°C to +125°C
DC Input Voltage[3] ................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Electrical Characteristics Over the Operating Range
-55
-70
Parameter
Description
Test Conditions
Unit
Min Typ[2] Max Min Typ[2] Max
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min., IOH = −1.0 mA
2.4
2.2
2.4
V
V
V
VCC = Min., IOL = 2.1 mA
0.4
0.4
VCC
+0.5V
2.2
VCC
+0.5V
VIL
IIX
Input LOW Voltage
–0.5
–0.5
–0.5
0.8
–0.5
0.8
+0.5
+0.5
50
V
Input Leakage Current GND < VI < VCC
+0.5 –0.5
+0.5 –0.5
μA
μA
mA
IOZ
ICC
Output Leakage Current GND < VO < VCC, Output Disabled
VCC Operating Supply VCC = Max.,
Current
L-Commercial/
Industrial
25
IOUT = 0 mA,
f = fMAX = 1/tRC
LL-Commercial
LL - Industrial
LL - Auto-A
LL - Auto-E
L
25
25
25
50
50
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
25
25
25
50
50
50
ISB1
Automatic CE
Power down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
0.4
0.3
0.3
0.3
0.6
0.5
0.5
0.5
LL-Commercial
LL - Industrial
LL - Auto-A
LL - Auto-E
L
0.3
0.3
0.3
0.5
0.5
0.5
ISB2
Automatic CE
Max. VCC
,
2
50
5
Power down Current— CE > VCC − 0.3V
LL-Commercial
LL - Industrial
LL - Auto-A
LL - Auto-E
0.1
0.1
0.1
μA
CMOS Inputs
V
IN > VCC − 0.3V, or
0.1
0.1
0.1
10
10
15
10
10
μA
VIN < 0.3V, f = 0
μA
μA
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions[5]
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
CIN
6
8
pF
pF
COUT
Notes
3.
4.
V
(min.) = −2.0V for pulse durations of less than 20 ns.
IL
T
is the “Instant-On” case temperature.
A
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06511 Rev. *B
Page 3 of 14
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CY62256N
Thermal Resistance
Parameter
Description[5]
Test Conditions
DIP
SOIC
TSOP
RTSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 75.61
inch, 4-layer printed circuit board
76.56
93.89
93.89
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
43.12
36.07
24.64
24.64
°C/W
Figure 3. AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
5V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
R2
990Ω
R2
990Ω
100 pF
5 pF
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions[6]
Min
Typ[2]
Max
Unit
2.0
V
ICCDR
L
VCC = 2.0V, CE > VCC − 0.3V,
IN > VCC − 0.3V, or VIN < 0.3V
2
50
5
μA
μA
μA
μA
ns
ns
V
LL-Commercial
LL - Industrial/Auto-A
LL - Auto-E
0.1
0.1
0.1
10
10
[8]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[8]
tR
tRC
Figure 4. Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Note
6. No input may exceed V + 0.5V.
CC
Document #: 001-06511 Rev. *B
Page 4 of 14
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CY62256N
Switching Characteristics Over the Operating Range[7]
CY62256N-55
CY62256N-70
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
55
5
70
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
CE LOW to Power up
CE HIGH to Power down
55
70
tOHA
tACE
55
25
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
5
0
5
5
0
20
20
55
25
25
70
tPD
Write Cycle[10, 11]
tWC
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
40
25
0
50
30
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z[8, 9]
WE HIGH to Low-Z[8]
tHD
tHZWE
tLZWE
20
25
5
5
Switching Waveforms
Figure 5. Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 100-pF load capacitance.
I
OL OH
8. At any temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9.
t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE L
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for Read cycle.
Document #: 001-06511 Rev. *B
Page 5 of 14
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CY62256N
Switching Waveforms (continued)
Figure 6. Read Cycle No. 2[13, 14]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
Figure 7. Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
DATA I/O
17
NOTE
IN
t
HZOE
Figure 8. Write Cycle No. 2 (CE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Notes
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 001-06511 Rev. *B
Page 6 of 14
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CY62256N
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
Document #: 001-06511 Rev. *B
Page 7 of 14
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CY62256N
Typical DC and AC Characteristics
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
3.0
2.5
2.0
1.5
1.0
1.4
1.2
ICC
ICC
1.0
0.8
0.6
1.0
0.8
0.6
ISB
VIN = 5.0V
TA = 25°C
VCC = 5.0V
VIN = 5.0V
0.5
0.4
0.4
VCC = 5.0V
0.2
0.0
0.0
0.2
0.0
V
IN = 5.0V
ISB
–0.5
−55
25
105
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
TA = 25°C
V
CC = 5.0V
VCC = 5.0V
TA = 25°C
40
0.8
0.6
20
0
0.9
0.8
0.0
1.0
2.0
3.0
4.0
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
V
CC = 5.0V
60
TA = 25°C
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 001-06511 Rev. *B
Page 8 of 14
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CY62256N
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
CC = 5.0V
TA = 25°C
VIN = 5.0V
V
CC = 4.5V
1.0
0.5
10.0
5.0
TA = 25°C
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE
WE
OE
Inputs/Outputs
High-Z
Mode
Power
H
X
X
Deselect/Power down
Read
Standby (ISB)
L
L
L
H
L
L
X
H
Data Out
Data In
High-Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
Write
H
Output Disabled
Document #: 001-06511 Rev. *B
Page 9 of 14
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CY62256N
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62256NLL−55SNI
CY62256NLL−55SNXI
CY62256NLL−55ZI
55
51-85092 28-Pin (300-Mil) Narrow SOIC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
51-85071 28-Pin TSOP I
28-Pin TSOP I (Pb-Free)
Industrial
CY62256NLL−55ZXI
CY62256NLL−55ZXA
CY62256NLL−55SNXE
CY62256NLL−55ZXE
CY62256NLL−55ZRXE
CY62256NL−70PC
51-85071 28-Pin TSOP I (Pb-Free)
51-85092 28-Pin (300-Mil) Narrow SOIC (Pb-Free)
51-85071 28-Pin TSOP I (Pb-Free)
51-85074 28-Pin Reverse TSOP I (Pb-Free)
51-85017 28-Pin (600-Mil) Molded DIP
28-Pin (600-Mil) Molded DIP (Pb-Free)
28-Pin (600-Mil) Molded DIP
Automotive-A
Automotive-E
70
Commercial
CY62256NL−70PXC
CY62256NLL−70PC
CY62256NLL−70PXC
CY62256NL−70SNC
CY62256NL−70SNXC
CY62256NLL−70SNC
CY62256NLL−70SNXC
CY62256NLL−70ZC
CY62256NLL−70ZXC
CY62256NL–70SNI
CY62256NL–70SNXI
CY62256NLL−70SNI
CY62256NLL−70SNXI
CY62256NLL−70ZI
28-Pin (600-Mil) Molded DIP (Pb-Free)
51-85092 28-Pin (300-Mil) Narrow SOIC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
28-Pin (300-Mil) Narrow SOIC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
51-85071 28-Pin TSOP I
28-Pin TSOP I (Pb-Free)
51-85092 28-Pin (300-Mil) Narrow SOIC
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
28-Pin (300-Mil) Narrow SOIC
Industrial
28-Pin (300-Mil) Narrow SOIC (Pb-Free)
51-85071 28-Pin TSOP I
CY62256NLL−70ZXI
CY62256NLL−70ZRI
CY62256NLL−70ZRXI
CY62256NLL−70SNXA
28-Pin TSOP I (Pb-Free)
51-85074 28-Pin Reverse TSOP I
28-Pin Reverse TSOP I (Pb-Free)
51-85092 28-Pin (300-Mil) Narrow SOIC (Pb-Free)
Automotive-A
Do contact your local Cypress sales representative for availability of these parts
Document #: 001-06511 Rev. *B
Page 10 of 14
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CY62256N
Package Diagrams
Figure 10. 28-Pin (600-Mil) Molded DIP (51-85017)
51-85017-*C
Figure 11. 28-Pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
Document #: 001-06511 Rev. *B
Page 11 of 14
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CY62256N
Figure 12. 28-Pin TSOP I (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 001-06511 Rev. *B
Page 12 of 14
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CY62256N
Figure 13. 28-Pin TSOP I (8 x 13.4 mm) (51-85074)
51-85074-*F
Document #: 001-06511 Rev. *B
Page 13 of 14
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CY62256N
Document History Page
Document Title: CY62256N 256K (32K x 8) Static RAM
Document Number: 001- 06511
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
426504
488954
See ECN
NXR
New Data Sheet
*A
See ECN
NXR
Added Automotive product
Updated ordering Information table
*B
2715270 06/05/2009 VKN/AESA Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017)
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06511 Rev. *B
Revised June 03, 2009
Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
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