CY7C09389V-9AXC [ROCHESTER]
64KX18 DUAL-PORT SRAM, 9ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100;
| 型号： | CY7C09389V-9AXC |
| 厂家： | 
Rochester Electronics |
| 描述： | 64KX18 DUAL-PORT SRAM, 9ns, PQFP100, LEAD FREE, PLASTIC, MS-026, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：1325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
■ 3.3V low operating power:
❐ Active = 115 mA (typical)
❐ Standby = 10 A (typical)
Features
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ Fully synchronous interface for easier operation
■ Six flow through/pipelined devices:
■ Burst counters increment addresses internally:
❐ Shorten cycle times
❐ Minimize bus noise
❐ 16K x 16/18 organization (CY7C09269V/369V)
❐ 32K x 16/18 organization (CY7C09279V/379V)
❐ 64K x 16/18 organization (CY7C09289V/389V)
❐ Supported in flow through and pipelined modes
■ Three modes:
❐ Flow through
❐ Pipelined
❐ Burst
■ Dual chip enables easy depth expansion
■ Upper and lower byte controls for bus matching
■ Automatic power down
■ Pipelined output mode on both ports allows fast 100 MHz
operation
■ Commercial and industrial temperature ranges
■ Pb-Free 100-pin TQFP package available
■ 0.35 micron CMOS for optimum speed and power
■ High speed clock to data access: 6.5[1, 2], 7.5[2], 9, 12 ns (max)
Logic Block Diagram
R/WL
R/WR
UB
UB
R
L
CE
CE
CE
CE
0L
1L
0R
1R
1
1
0
0
0/1
0/1
LB
LB
L
R
OE
OE
L
R
1b 0b 1a 0a
0a 1a 0b 1b
0/1
b
a
a
b
0/1
FT/PipeL
FT/PipeR
8/9
8/9
8/9
8/9
[3]
[3]
I/O8/9L–I/O15/17L
I/O8/9R–I/O15/17R
I/O
Control
I/O
Control
[4]
[4]
I/O0L–I/O7/8L
I/O0R–I/O7/8R
14/15/16
A
0L–A
14/15/16 A0R–A[5]
[5]
13/14/15L
13/14/15R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
CLK
CLK
ADS
L
R
R
R
R
True Dual-Ported
ADS
L
RAM Array
CNTEN
CNTEN
CNTRST
L
CNTRST
L
Notes
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
8
15
9
17
4. I/O –I/O for x16 devices. I/O –I/O for x18 devices.
0
7
0
8
5. A –A for 16K; A –A for 32K; A –A for 64K devices.
0
13
0
14
0
15
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 22, 2010
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pinouts
Figure 1. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
A15L
NC
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
2
A10R
A11R
A12R
A13R
A14R
A15R
NC
3
4
5
[6]
[7]
6
[6]
[7]
7
8
NC
9
NC
LBL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LBR
UBL
UBR
CE0R
CE1R
CY7C09289V (64K x 16)
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
CE0L
CE1L
CNTRSTL
VCC
CNTRSTR
GND
R/WL
R/WR
OEL
OER
FT/PIPEL
FT/PIPER
[8]
GND
I/O15L
I/O14L
I/O13L
I/O12L
GND
[8]
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes
6. This pin is NC for CY7C09269V.
7. This pin is NC for CY7C09269V and CY7C09279V.
8. For CY7C09269V and CY7C09279V, pin #18 connected to V is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible
CC
to an IDT 5V x16 flow through device.
Document #: 38-06056 Rev. *D
Page 2 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pinouts (continued)
Figure 2. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
A8R
A10L
A11L
A12L
A13L
A14L
A15L
LBL
2
A9R
3
A10R
A11R
A12R
A13R
A14R
A15R
LBR
4
5
6
[9]
[10]
7
[9]
8
[10]
UBL
9
CE0L
CE1L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UBR
CE0R
CE1R
CY7C09389V (64K x 18)
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
CNTRSTL
R/WL
CNTRSTR
R/WR
OEL
VCC
GND
FT/PIPEL
I/O17L
I/O16L
GND
OER
FT/PIPER
I/O17R
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O16R
I/O15R
I/O14R
I/O13R
I/O11L
I/O10L
24
25
52
51
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09269V/79V/89V
CY7C09369V/79V/89V
CY7C09269V/79V/89V
CY7C09369V/79V/89V
CY7C09269V/79V/89V
CY7C09369V/79V/89V
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Specifications
[1, 2]
[2]
-6
-7
-9
67
9
-12
50
12
f
(MHz) (Pipelined)
100
6.5
83
MAX2
Max. Access Time (ns)
(Clock to Data, Pipelined)
7.5
Typical Operating Current
CC
175
25
155
25
135
20
115
20
I
(mA)
Typical Standby Current for
(mA)
I
SB1
(Both Ports TTL Level)
Typical Standby Current for
10
10
10
10
I
(A)
SB3
(Both Ports CMOS Level)
Notes
9. This pin is NC for CY7C09369V.
10. This pin is NC for CY7C09369V and CY7C09379V.
Document #: 38-06056 Rev. *D
Page 3 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Definitions
Left Port
A0L–A15L
ADSL
Right Port
Description
A0R–A15R
ADSR
Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices).
Address Strobe Input. Used as an address qualifier. This signal must be asserted LOW to access
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter
with the address present on the address pins.
CE0L, CE1L CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their
active states (CE0 VIL and CE1 VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBL
LBR
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower
byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both the LB and
OE signals must be asserted to drive output data on the lower byte of the data pins.
UBL
OEL
UBR
OER
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow Through/Pipelined Select Input. For flow through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
GND
NC
Ground Input.
No Connect.
Power Input.
VCC
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
Functional Description
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0 LOW and CE1 HIGH to reactivate
the outputs.
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory[11]. Registers on control, address, and data
lines allow for minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow through mode can also
be used to bypass the pipelined output register to eliminate
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads/writes one word from or into
each successive address location, until CNTEN is deasserted.
The counter can address the entire memory array and loop back
to the start. Counter Reset (CNTRST) is used to reset the burst
counter.
access latency. In flow through mode, data is available tCD1
18 ns after the address is clocked into the device. Pipelined
output or flow through mode is selected through the FT/Pipe pin.
=
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the LOW to HIGH
transition of the clock signal. The internal write pulse is self timed
to allow the shortest possible cycle times.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note
11. When writing simultaneously to the same location, the final value cannot be guaranteed.
Document #: 38-06056 Rev. *D
Page 4 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Maximum Ratings [12]
DC Input Voltage0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 1100V
(per MIL-STD-883, Method 3015)
Storage Temperature 65C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied 55C to +125C
Operating Range
Supply Voltage to Ground Potential 0.5V to +4.6V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
DC Voltage Applied to Outputs
in High Z State 0.5V to VCC+0.5V
3.3V 300 mV
3.3V 300 mV
–40°C to +85°C
Electrical Characteristics
Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-7[2]
-9
Parameter
Description
Unit
-12
-6[1, 2]
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
VOH
VOL
Output HIGH Voltage
(VCC = Min. lOH = –4.0 mA)
2.4
2.4
2.4
2.4
V
V
Output LOW Voltage
(VCC = Min. lOH = +4.0 mA)
0.4
0.8
0.4
0.8
0.4
0.8
0.4
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.0
2.0
2.0
2.0
V
V
0.8
10
Output Leakage Current
–10
10 –10
175 320
10 –10
155 275
275 390
10 –10
135 230
185 300
A
Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Com’l.
Indust.
115 180 mA
mA
ISB1
ISB2
ISB3
ISB4
Standby Current
Com’l.
Indust.
25 95
115 175
10 250
105 135
25
85
20
35
75
85
20
70 mA
mA
(Both Ports TTL Level)[13]
CEL & CER VIH, f = fMAX
85 120
Standby Current
Com’l.
Indust.
105 165
165 210
95 155
105 165
85 140 mA
mA
(One Port TTL Level)[13]
CEL | CER VIH, f = fMAX
Standby Current
Com’l.
Indust.
10 250
10 250
10 250
10 250
10 250 A
A
(Both Ports CMOS Level)[13]
CEL & CER VCC – 0.2V, f = 0
Standby Current
Com’l.
Indust.
95 125
125 170
85 115
95 125
75 100 mA
mA
(One Port CMOS Level)[13]
CEL | CER VIH, f = fMAX
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25C, f = 1 MHz, VCC = 3.3V
Max
10
Unit
pF
COUT
10
pF
Notes
12. The voltage on any input or I/O pin can not exceed the power pin during power up.
13. CE and CE are internal signals. To select either the left or right port, both CE and CE must be asserted to their active states (CE V and CE V ).
L
R
0
1
0
IL
1
IH
Document #: 38-06056 Rev. *D
Page 5 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Figure 3. AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250
R1 = 590
OUTPUT
C = 30 pF
OUTPUT
C = 30 pF
R1 = 590
OUTPUT
C = 5 pF
R2 = 435
R2 = 435
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for tCKLZ, tOLZ, and tOHZ
including scope and jig)
[14]
Figure 4. AC Test Loads (Applicable to -6 and -7 only)
ALL INPUTPULSES
Z = 50
R = 50
0
OUTPUT
3.0V
GND
90%
90%
10%
C
10%
3 ns
3 ns
V
TH
= 1.4V
(a) Load 1 (-6 and -7 only)
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note
14. Test Conditions: C = 10 pF.
Document #: 38-06056 Rev. *D
Page 6 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Characteristics
Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Parameter
Description
Unit
-6 [1, 2]
-7[2]
-9
-12
Min
Max
Min
Max
Min
Max
40
Min
Max
33
fMAX1
fMAX2
tCYC1
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
fMax Flow Through
53
45
83
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMax Pipelined
100
67
50
Clock Cycle Time - Flow Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow Through
Clock LOW Time - Flow Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
19
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
4
5
6
8
3
3
3
3
3
3
3
3
tF
Clock Fall Time
tSA
Address Set-Up Time
Address Hold Time
3.5
0
4
0
4
1
4
1
4
1
4
1
4
1
5
1
4
1
4
1
4
1
4
1
4
1
4
1
5
1
4
1
tHA
tSC
Chip Enable Setup Time
Chip Enable Hold Time
R/W Set-Up Time
3.5
0
4
tHC
0
tSW
3.5
0
4
tHW
tSD
R/W Hold Time
0
Input Data Setup Time
Input Data Hold Time
ADS Set-Up Time
3.5
0
4
tHD
0
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
3.5
0
4
0
ADS Hold Time
3.5
0
4.5
0
CNTEN Setup Time
CNTEN Hold Time
3.5
0
4
CNTRST Setup Time
CNTRST Hold Time
0
8
9
10
12
Output Enable to Data Valid
OE to Low Z
[15,16]
tOLZ
2
1
2
1
2
1
2
1
[15,16]
tOHZ
7
7
7
20
9
7
OE to High Z
tCD1
tCD2
tDC
Clock to Data Valid - Flow Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
15
6.5
18
7.5
25
12
2
2
2
2
2
2
2
2
2
2
2
2
[15,16]
tCKZ
9
9
9
9
[15,16]
tCKZ
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay
tCCS Clock to Clock Setup Time
30
9
35
10
40
15
40
15
ns
ns
Notes
15. Test conditions used are Load 2.
16. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06056 Rev. *D
Page 7 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms
Figure 5. Read Cycle for Flow Through Output (FT/PIPE = VIL) [17, 18, 19, 20]
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
ADDRESS
DATAOUT
tCKHZ
Qn+2
tDC
tDC
Qn
tCD1
Qn+1
tCKLZ
tOHZ
tOLZ
OE
tOE
Figure 6. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[17, 18, 19, 20]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes
17. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
18. ADS = V , CNTEN and CNTRST = V
.
IH
IL
19. The output is disabled (high impedance state) by CE =V or CE = V following the next rising edge of the clock.
0
IH
1
IL
20. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IL
Document #: 38-06056 Rev. *D
Page 8 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Figure 7. Bank Select Pipelined Read[21, 22]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE0(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
D0
D3
D1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE0(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
D4
D2
tCKLZ
tCKLZ
Figure 8. Left Port Write to Flow Through Right Port Read[23, 24, 25, 26]
CLK
L
t
t
HW
SW
R/WL
t
t
HA
SA
NO
MATCH
ADDRESS
MATCH
L
t
t
HD
SD
VALID
DATA
INL
t
CCS
CLK
R
t
CD1
t
t
t
t
SW
SA
HW
HA
R/WR
NO
MATCH
MATCH
ADDRESS
R
t
t
CWDD
CD1
DATA
VALID
VALID
OUTR
t
DC
t
DC
Notes
21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS = ADDRESS
.
(B2)
(B1)
22. UB, LB, OE and ADS = V ; CE
, CE
, R/W, CNTEN, and CNTRST = V .
IL
1(B1)
1(B2) IH
23. The same waveforms apply for a right port write to flow through left port read.
24. CE , UB, LB, and ADS = V ; CE , CNTEN, and CNTRST = V
.
IH
0
IL
1
25. OE = V for the Right Port, which is being read from. OE = V for the Left Port, which is being written to.
IL
IH
26. It t
maximum specified, then data from right port READ is not valid until the maximum specified for t
CD1 CWDD
. If t >maximum specified, then data is not valid until
CCS
CCS
CWDD
t
+ t
. t
does not apply in this case.
CCS
Document #: 38-06056 Rev. *D
Page 9 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Figure 9. Pipelined Read-to-Write-to-Read (OE = VIL)[20, 27, 28, 29]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DATAOUT
READ
NO OPERATION
WRITE
READ
Figure 10. Pipelined Read-to-Write-to-Read (OE Controlled)[20, 27, 28, 29]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tHW
tSW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes
27. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
28. CE and ADS = V ; CE , CNTEN, and CNTRST = V
.
IH
0
IL
1
29. During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
Document #: 38-06056 Rev. *D
Page 10 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Figure 11. Flow Through Read-to-Write-to-Read (OE = VIL)[18, 20, 28, 29]
tCYC1
tCL1
tCH1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DATAOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tDC
tCKLZ
NO
OPERATION
READ
WRITE
READ
Figure 12. Flow Through Read-to-Write-to-Read (OE Controlled)[18, 20, 27, 28, 29]
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
tDC
DATAOUT
OE
tOHZ
tCKLZ
READ
WRITE
READ
Document #: 38-06056 Rev. *D
Page 11 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Figure 13. Pipelined Read with Address Counter Advance[30]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DATAOUT
Qx-1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Figure 14. Flow Through Read with Address Counter Advance[30]
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tCD1
tSCN
tHCN
Qx
tDC
Qn
Qn+1
Qn+2
Qn+3
DATAOUT
READ
READ
WITH
COUNTER HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
Note
30. CE and OE = V ; CE , R/W and CNTRST = V .
IH
0
IL
1
Document #: 38-06056 Rev. *D
Page 12 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Figure 15. Write with Address Counter Advance (Flow Through or Pipelined Outputs)[31, 32]
tCYC2
tCL2
tCH2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes
31. CE , UB, LB, and R/W = V ; CE and CNTRST = V .
IH
0
IL
1
32. The “Internal Address” is equal to the “External Address” when ADS = V and equals the counter output when ADS = V
.
IL
IH
Document #: 38-06056 Rev. *D
Page 13 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Switching Waveforms (continued)
Figure 16. Counter Reset (Pipelined Outputs)[20, 27, 33, 34]
tCYC2
tCL2
tCH2
CLK
tSA tHA
An
An+1
ADDRESS
INTERNAL
ADDRESS
AX
0
1
An
An+1
tSW tHW
R/W
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSRST
tHRST
CNTRST
DATAIN
tSD tHD
D0
DATAOUT
Q0
Q1
Qn
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes
33. CE , UB, and LB = V ; CE = V .
IH
0
IL
1
34. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06056 Rev. *D
Page 14 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Read/Write and Enable Operation[35, 36, 37]
Inputs
Outputs
I/O0–I/O17
High-Z
Operation
OE
CLK
CE0
CE1
R/W
X
H
X
X
Deselected[38]
Deselected[38]
Write
X
X
L
X
L
L
L
L
X
L
High-Z
DIN
H
H
H
H
X
DOUT
High-Z
Read[35]
H
X
Outputs Disabled
Address Counter Control Operation[35, 39, 40, 41]
Previous
Address
Address
CLK
ADS
CNTEN CNTRST
I/O
Mode
Operation
X
X
X
X
X
H
L
H
H
Dout(0)
Dout(n)
Dout(n)
Reset
Counter Reset to Address 0
An
X
X
L
Load
Hold
Address Load into Counter
An
H
ExternalAddressBlocked—Counter
Disabled
X
X
An
An
H
H
L
L
H
H
Dout(n+1) Increment Counter Enabled—Internal Address
Generation
Dout(n+1) Increment Counter Enabled—Internal Address
Generation
Notes
35. “X” = “Don’t Care”, “H” = V , “L” = V
.
IL
IH
36. ADS, CNTEN, CNTRST = “Don’t Care”.
37. OE is an asynchronous input signal.
38. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
39. CE and OE = V ; CE and R/W = V
.
IH
0
IL
1
40. Data shown for flow through mode; pipelined mode output is delayed by one cycle.
41. Counter operation is independent of CE and CE .
0
1
Document #: 38-06056 Rev. *D
Page 15 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Ordering Information
16K x16 3.3V Synchronous Dual-Port SRAM
Package
Diagram
Speed (ns)
Ordering Code
Package Type
Operating Range
7.5[2]
9
CY7C09269V-7AXC
CY7C09269V-9AXC
CY7C09269V-12AXC
51-85048
51-85048
51-85048
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
Commercial
Commercial
Commercial
12
32K x16 3.3V Synchronous Dual-Port SRAM
Package
Diagram
Speed (ns)
Ordering Code
Package Type
Operating Range
7.5[2]
CY7C09279V-7AC
CY7C09279V-7AXC
CY7C09279V-12AXC
51-85048
100-Pin Thin Quad Flat Pack
Commercial
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
12
51-85048
Commercial
64K x16 3.3V Synchronous Dual-Port SRAM
Package
Diagram
Speed (ns)
Ordering Code
Package Type
Operating Range
9
CY7C09289V-9AC
CY7C09289V-9AXC
CY7C09289V-9AI
CY7C09289V-9AXI
CY7C09289V-12AXC
51-85048
51-85048
51-85048
100-Pin Thin Quad Flat Pack
Commercial
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack
Industrial
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
12
Commercial
Document #: 38-06056 Rev. *D
Page 16 of 19
[+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Ordering Information (Continued)
16K x18 3.3V Synchronous Dual-Port SRAM
Package
Diagram
Speed (ns)
Ordering Code
Package Type
Operating Range
9
CY7C09369V-9AXC
CY7C09369V-12AXC
51-85048
51-85048
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
Commercial
Commercial
12
32K x18 3.3V Synchronous Dual-Port SRAM
Package
Diagram
Speed (ns)
Ordering Code
Package Type
Operating Range
12
CY7C09379V-12AXC
51-85048
100-Pin Thin Quad Flat Pack (Pb-Free)
Commercial
64K x18 3.3V Synchronous Dual-Port SRAM
Package
Diagram
Speed (ns)
Ordering Code
Package Type
Operating Range
7.5[2]
9
CY7C09389V-7AXC
CY7C09389V-9AXC
CY7C09389V-9AI
51-85048
51-85048
51-85048
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Industrial
CY7C09389V-9AXI
CY7C09389V-12AXC
100-Pin Thin Quad Flat Pack (Pb-Free)
100-Pin Thin Quad Flat Pack (Pb-Free)
12
51-85048
Commercial
Document #: 38-06056 Rev. *D
Page 17 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Package Diagrams
Figure 17. 100-Pin Thin Plastic Quad Flat Pack (TQFP), 51-85048
51-85048 *D
Document #: 38-06056 Rev. *D
Page 18 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document History Page
Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
Document Number: 38-06056
Revision
ECN
Submission Orig. of
Description of Change
Date
Change
**
110215
122306
344354
2678221
2896210
12/18/01
12/27/02
See ECN
SZV
Change from Spec number: 38-00668 to 38-06056
Power up requirements added to Maximum Ratings Information
Added Pb-Free Part Ordering Information
*A
*B
*C
*D
RBI
PCX
03/25/2009 VKN/AESA Added CY7C09379V-12AXCT part. Updated 51-85048 to *C.
03/22/2010
RAME
Updated Ordering Information
Updated Package Diagrams
Sales, Solutions, and Legal Information
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closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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Document #: 38-06056 Rev. *D
Revised March 22, 2010
Page 19 of 19
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