CY7C1021B-15ZCT [ROCHESTER]
64KX16 STANDARD SRAM, 15ns, PDSO44, TSOP2-44;
| 型号： | CY7C1021B-15ZCT |
| 厂家： | 
Rochester Electronics |
| 描述： | 64KX16 STANDARD SRAM, 15ns, PDSO44, TSOP2-44 静态存储器 光电二极管 |
| 文件： | 总11页 (文件大小：988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021B
1-Mbit (64K x 16) Static RAM
automatic power-down feature that significantly reduces
power consumption when deselected.
Features
• Temperature Ranges
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
— tAA = 12 ns (Commercial & Industrial)
— tAA = 15 ns (Automotive)
• CMOS for optimum speed/power
• Low active power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
— 770 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
• Available in Pb-free and non Pb-free 44-pin TSOP II and
44-pin 400-mil-wide SOJ
Functional Description[1]
The CY7C1021B is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
The CY7C1021B is available in standard 44-pin TSOP Type II
and 44-pin 400-mil-wide SOJ packages.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
A4
A3
A2
A1
64K x 16
I/O1–I/O8
RAM Array
512 X 2048
I/O9–I/O16
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05145 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 28, 2006
CY7C1021B
Selection Guide
-12
12
-15
15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Com’l/Ind’l
Automotive
Com’l/Ind’l
Automotive
L Version
140
130
130
10
Maximum CMOS Standby Current (mA)
10
15
0.5
0.5
Pin Configurations
SOJ/TSOP II
Top View
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
OE
A
1
BHE
BLE
I/O
A
0
CE
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
I/O
I/O
2
3
15
14
13
9
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
V
V
CC
32
I/O
I/O
I/O
5
6
7
8
12
11
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
10
9
I/O
WE 17
NC
18
27
26
25
A
A
8
15
19
A
A
14
9
A
13
20
21
22
A
11
10
A
A
12
24
23
NC
NC
Pin Definitions
Pin Name SOJ, TSOP–Pin Number
I/O Type
Description
A0–A15
1–5,18–21, 24–27, 42–44
Input
Address Inputs used to select one of the address locations.
I/O1–I/O16
7–10, 13–16, 29–32,
35–38
Input/Output Bidirectional Data I/O lines. Used as input or output lines depending
on operation.
NC
22, 23, 28
17
No Connect No Connects. Not connected to the die.
WE
Input/Control Write Enable Input, active LOW. When selected LOW, a Write is
conducted. When deselected HIGH, a Read is conducted.
CE
BHE, BLE
OE
6
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When
HIGH, deselects the chip.
40, 39
41
Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9,
BLE controls I/O8–I/O1.
Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
VSS
VCC
12, 34
11, 33
Ground
Ground for the device. Should be connected to ground of the
system.
Power Supply Power Supply inputs to the device.
Document #: 38-05145 Rev. *C
Page 2 of 10
CY7C1021B
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[2] .... –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature (TA)[3]
0°C to +70°C
VCC
5V ± 10%
5V ± 10%
5V ± 10%
–40°C to +85°C
–40°C to +125°C
DC Voltage Applied to Outputs
in High Z State[2] ......................................–0.5V to VCC+0.5V
Automotive
DC Input Voltage[2]...................................–0.5V to VCC+0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
-12
-15
Test
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Leakage Current
Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max. Unit
2.4
2.4
V
VOL
VIH
VIL
IIX
0.4
6.0
0.8
+1
0.4
6.0
0.8
+1
V
2.2
–0.5
–1
2.2
–0.5
–1
V
V
GND < VI < VCC
Com’l/Ind’l
Auto
µA
µA
µA
µA
mA
mA
mA
mA
–4
+4
IOZ
Output Leakage Current
GND < VI < VCC
Output Disabled
,
Com’l/Ind’l
Auto
–1
+1
140
40
–1
+1
–4
+4
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA, Com’l/Ind’l
f = fMAX = 1/tRC
130
130
40
Auto
ISB1
Automatic CE
Power Down Current —TTL VIN > VIH or VIN < VIL, f =
Inputs
Max. VCC, CE > VIH
Com’l/Ind’l
Auto
50
fMAX
ISB2
Automatic CE
Power Down Current
—CMOS Inputs
Max. VCC, CE > VCC
0.3V, VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
–
Com’l/Ind’l
Auto
10
10
15
mA
mA
mA
L Version
0.5
0.5
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8
8
pF
pF
COUT
Thermal Resistance[4]
44-pin
TSOP-II
Parameter
Description
Test Conditions
44-pin SOJ
Unit
ΘJA
Thermal Resistance Test conditions follow standard test methods and
(Junction to Ambient) procedures for measuring thermal impedance,
64.32
76.89
14.28
°C/W
per EIA/JESD51.
ΘJC
Thermal Resistance
31.03
°C/W
(Junction to Case)
Notes:
2. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
3. T is the “Instant On” case temperature.
A
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05145 Rev. *C
Page 3 of 10
CY7C1021B
AC Test Loads and Waveforms
R 481Ω
R 481Ω
ALL INPUT PULSES
5V
5V
OUTPUT
3.0V
90%
10%
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
GND
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
(a)
167
30 pF
1.73V
OUTPUT
Equivalent to:
THÉVENIN
EQUIVALENT
Switching CharacteristicsOver the Operating Range[5]
7C1021B-12
7C1021B-15
Parameter
Read Cycle
Description
Min.
12
3
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
12
15
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
12
6
15
7
0
3
0
0
3
0
6
6
7
7
tPD
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[8]
tWC
0
0
6
7
Write Cycle Time
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
8
tHA
0
tSA
0
0
tSD
6
8
tHD
0
0
tLZWE
tHZWE
tBW
3
3
WE LOW to High Z[6, 7]
6
7
Byte Enable to End of Write
8
9
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZBE HZCE
HZWE
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05145 Rev. *C
Page 4 of 10
CY7C1021B
Switching Waveforms
Read Cycle No. 1[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes:
9. Device is continuously selected. OE, CE, BHE and/or BHE = V .
IL
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05145 Rev. *C
Page 5 of 10
CY7C1021B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
12. Data I/O is high impedance if OE or BHE and/or BLE= V
.
IH
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05145 Rev. *C
Page 6 of 10
CY7C1021B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High Z
I/O9–I/O16
Mode
Power
H
L
X
L
X
H
X
L
X
L
High Z
Power-Down
Read - All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
)
L
H
L
Read - Lower bits only
Read - Upper bits only
Write - All bits
)
H
L
)
L
X
L
L
Data In
Data In
High Z
)
L
H
L
Write - Lower bits only
Write - Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
)
High Z
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1021B-12VC
Package Type
12
51-85082
51-85087
51-85082
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin TSOP Type II
Commercial
CY7C1021B-12VXC
CY7C1021B-12ZC
CY7C1021B-12ZXC
CY7C1021B-12VI
CY7C1021B-12VXI
44-pin TSOP Type II (Pb-Free)
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-Free)
Industrial
Document #: 38-05145 Rev. *C
Page 7 of 10
CY7C1021B
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1021B-15VC
CY7C1021B-15VXC
CY7C1021B-15ZC
CY7C1021B-15ZXC
CY7C1021B-15VI
CY7C1021B-15VXI
CY7C1021B-15ZI
Package Type
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin TSOP Type II
15
51-85082
51-85087
51-85082
51-85087
Commercial
44-pin TSOP Type II (Pb-Free)
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin TSOP Type II
Industrial
CY7C1021BL-15ZI
CY7C1021B-15ZXI
CY7C1021BL-15ZXI
CY7C1021B-15VE
CY7C1021B-15VXE
CY7C1021B-15ZE
CY7C1021B-15ZSXE
44-pin TSOP Type II
44-pin TSOP Type II (Pb-Free)
44-pin TSOP Type II (Pb-Free)
44-pin (400-Mil) Molded SOJ
44-pin (400-Mil) Molded SOJ (Pb-Free)
44-pin TSOP Type II
51-85082
51-85087
Automotive
44-pin TSOP Type II (Pb-Free)
Package Diagrams
44-pin (400-Mil) Molded SOJ (51-85082)
44
23
DIMENSIONS IN INCHES MIN.
MAX.
0.395
0.405
0.435
0.445
22
1
SEATING PLANE
1.120
1.130
0.095
0.115
0.128
0.148
0.082
MIN.
0.007
0.013
0.004
0.365
0.375
0.023
0.033
0.050
TYP.
0.045
MAX.
0°-10°
0.025
MIN.
0.013
0.023
51-85082-*B
Document #: 38-05145 Rev. *C
Page 8 of 10
CY7C1021B
Package Diagrams (continued)
44-Pin TSOP II (51-85087)
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05145 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1021B
Document History Page
Document Title: CY7C1021B 1-Mbit (64K x 16) Static RAM
Document Number: 38-05145
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-00951 to 38-05145
1) Added Automotive Specs to Data Sheet
109889
238454
09/22/01
See ECN
SZV
RKF
*A
2) Added Pb-Free device offering in the Ordering Information
*B
*C
361795
505726
See ECN
See ECN
SYT
NXR
Added Pb-Free offerings in the Ordering Information
Removed CY7C10211B from Product offering
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Changed teh ICC Max value from 150 mA to 130 mA
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information Table
Document #: 38-05145 Rev. *C
Page 10 of 10
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