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CY7C1021BV33L-12ZCT [ROCHESTER]

Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, TSOP2-44;
CY7C1021BV33L-12ZCT
型号： CY7C1021BV33L-12ZCT
厂家： Rochester Electronics    Rochester Electronics
描述：

Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, TSOP2-44

静态存储器 光电二极管
文件： 总11页 (文件大小：241K)
中文：  中文翻译
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021BV33  
CY7C1021BV33  
64K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• 3.3V operation (3.0V–3.6V)  
• High speed  
— tAA = 10/12/15 ns  
• CMOS for optimum speed/power  
• Low Active Power (L version)  
— 576 mW (max.)  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O9 to I/O16. See the  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
• Low CMOS Standby Power (L version)  
— 1.80 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in 44-pin TSOP II and 400-mil SOJ  
• Available in a 48-Ball Mini BGA package  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and  
BLE are disabled (BHE, BLE HIGH), or during a write opera-  
tion (CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1021BV is a high-performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an au-  
tomatic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1021BV is available in 400-mil-wide SOJ, standard  
44-pin TSOP Type II, and 48-ball mini BGA packages.  
Logic Block Diagram  
Pin Configurations  
SOJ / TSOP II  
DATA IN DRIVERS  
Top View  
44  
1
A
A
A
A
A
A
5
4
3
2
1
0
43  
42  
41  
40  
39  
38  
A
2
3
4
5
6
6
A
7
A
A
A
7
6
5
4
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
64K x 16  
CE  
A
A
A
A
I/O –I/O  
RAM Array  
512 X 2048  
I/O  
1
8
7
1
16  
37  
36  
35  
34  
33  
3
2
I/O  
I/O  
8
2
3
15  
14  
13  
I/O –I/O  
9
9
16  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
1
0
4
CC  
V
SS  
A
V
V
I/O  
I/O  
CC  
32  
I/O  
5
6
7
8
12  
11  
10  
9
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
BHE  
19  
A
A
14  
9
10  
11  
WE  
CE  
OE  
A
20  
21  
22  
A
A
13  
A
12  
24  
23  
NC  
NC  
BLE  
Selection Guide  
7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15  
Maximum Access Time (ns)  
Maximum Operating Current (mA) Commercial  
Industrial  
8
170  
190  
5
10  
160  
180  
5
12  
150  
170  
5
15  
140  
160  
5
Maximum CMOS Standby Current Commercial  
(mA)  
L
0.500  
0.500  
0.500  
0.500  
Shaded areas contain advance information.  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05148 Rev. *A  
Revised September 13, 2002  
CY7C1021BV33  
Pin Configurations  
Mini BGA  
(Top View)  
1
2
3
4
6
5
A2  
A
B
A0  
A1  
A4  
NC  
I/O1  
BLE  
OE  
A3  
A5  
CE  
I/O9 BHE  
I/O10  
I/O11  
A6  
A7  
I/O2 I/O3  
C
I/O12  
VSS  
I/O4  
VCC  
NC  
NC  
D
E
I/O13  
VCC  
I/O5 VSS  
NC  
I/O14 A14 A15 I/O6 I/O7  
F
I/O15  
I/O16  
A13  
A10  
G
H
A12  
A9  
WE I/O8  
NC  
A11  
NC  
NC A8  
Current into Outputs (LOW) ........................................ 20 mA  
Maximum Ratings  
Static Discharge Voltage............................................ >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-Up Current..................................................... >200 mA  
Storage Temperature .................................–65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
DC Voltage Applied to Outputs  
3.3V ± 10%  
3.3V ± 10%  
in High Z State[2] ......................................–0.5V to VCC+0.5V  
–40°C to +85°C  
DC Input Voltage[2]...................................–0.5V to VCC+0.5V  
Note:  
2. Mimimum voltage is–2.0V for pulse durations of less than 20 ns.  
Document #: 38-05148 Rev. *A  
Page 2 of 11  
CY7C1021BV33  
Electrical Characteristics Over the Operating Range  
7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15  
Parameter  
Description  
Test Conditions  
VCC = Min.,  
OH = –4.0 mA  
VCC = Min., IOL = 8.0 mA  
Min. Max. Min.  
Max.  
Min.  
Max. Min. Max. Unit  
VOH  
Output HIGH  
Voltage  
2.4  
2.4  
2.4  
2.4  
V
I
VOL  
VIH  
VIL  
IIX  
Output LOW  
Voltage  
0.4  
2.2 VCC  
0.4  
0.4  
0.4  
V
Input HIGH  
Voltage  
+
2.2  
−0.3  
−1  
VCC  
+
2.2  
–0.3  
–1  
VCC  
0.3V  
+
2.2  
–0.3  
–1  
VCC  
0.3V  
+
V
0.3V  
0.3V  
Input LOW  
Voltage[2]  
−0.3  
−1  
0.8  
0.8  
0.8  
+1  
+1  
0.8  
+1  
+1  
V
Input Load  
Current  
GND < VI < VCC  
+1  
+1  
+1  
+1  
µA  
µA  
IOZ  
ICC  
Output Leakage GND < VI < VCC  
Current  
,
−1  
−1  
–1  
–1  
Output Disabled  
VCC Operating  
Supply Current  
VCC = Max.,  
IOUT = 0 mA,  
f = fMAX = 1/tRC  
Com  
Ind  
170  
190  
160  
120  
150  
170  
140  
160  
mA  
mA  
ISB1  
Automatic CE  
Power-Down  
Current  
Max. VCC  
CE > VIH  
VIN > VIH or  
VIN < VIL, f = fMAX  
,
40  
40  
40  
40  
mA  
—TTL Inputs  
ISB2  
Automatic CE  
Power-Down  
Current  
Max. VCC  
CE > VCC – 0.3V,  
VIN > VCC – 0.3V,  
,
5
5
5
5
mA  
L
500  
500  
500  
500  
µA  
—CMOS Inputs or VIN < 0.3V,  
f = 0  
Shaded areas contain advance information.  
Capacitance[3]  
Parameter  
Description  
Test Conditions  
TA = 25°C, f = 1 MHz  
Max.  
Unit  
pF  
CIN  
Input Capacitance  
Output Capacitance  
6
8
COUT  
pF  
Note:  
3. Tested initially and after any design or process changes that may affect these parameters.  
AC Test Loads and Waveforms  
R 317Ω  
R 317Ω  
ALL INPUT PULSES  
90%  
10%  
3.3V  
3.3V  
3.0V  
90%  
10%  
OUTPUT  
OUTPUT  
R2  
351Ω  
R2  
351Ω  
GND  
30 pF  
5 pF  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
Rise Time: 1 V/ns  
Fall Time: 1 V/ns  
(b)  
(a)  
167  
30 pF  
1.73V  
OUTPUT  
Equivalent to:  
THÉVENIN  
EQUIVALENT  
Document #: 38-05148 Rev. *A  
Page 3 of 11  
CY7C1021BV33  
Switching Characteristics[4] Over the Operating Range  
7C1021BV-8  
7C1021BV-10  
7C1021BV-12  
7C1021BV-15  
Parameter  
Description  
Min.  
Max.  
Min.  
10  
3
Max.  
Min.  
12  
3
Max.  
Min.  
Max. Unit  
READ CYCLE  
tRC  
Read Cycle Time  
8
3
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[5, 6]  
CE LOW to Low Z[6]  
CE HIGH to High Z[5, 6]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
Byte Enable to Data Valid  
Byte Enable to Low Z  
Byte Disable to High Z  
8
10  
12  
15  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
3
8
4
10  
4
12  
6
15  
7
0
3
0
0
3
0
0
3
0
0
3
0
4
4
5
5
6
6
7
7
tPD  
12  
12  
5
12  
6
15  
7
tDBE  
tLZBE  
tHZBE  
4
0
0
0
0
4
5
6
7
WRITE CYCLE[7]  
tWC  
tSCE  
tAW  
Write Cycle Time  
8
7
6
0
0
6
4
0
3
10  
8
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
8
tHA  
0
0
tSA  
0
0
0
tPWE  
tSD  
8
8
10  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z[6]  
6
6
tHD  
0
0
0
tLZWE  
tHZWE  
tBW  
3
3
3
WE LOW to High Z[5, 6]  
4
5
6
7
Byte Enable to End of Write  
8
8
8
9
Shaded areas contain advance information.  
Data Retention Characteristics Over the Operating Range (L version only)  
Parameter Description  
Conditions[8]  
VDR VCC for Data Retention  
ICCDR Data Retention Current  
Min.  
Max.  
Unit  
2.0  
V
Com’l  
VCC = VDR = 2.0V,  
CE > VCC – 0.3V,  
VIN > VCC – 0.3V or VIN < 0.3V  
100  
µA  
[9]  
tCDR  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
[10]  
tR  
tRC  
Notes:  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
OL/IOH and 30-pF load capacitance.  
5.  
t
HZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
7. The internal write time of the memory is defined by the overlap of CELOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,  
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
8. No input may exceed VCC + 0.5V.  
9. Tested initially and after any design or process changes that may affect these parameters.  
10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.  
Document #: 38-05148 Rev. *A  
Page 4 of 11  
CY7C1021BV33  
Data Retention Waveform  
DATA RETENTION MODE  
DR > 2V  
3.0V  
3.0V  
V
V
CC  
t
t
R
CDR  
CE  
Switching Waveforms  
Read Cycle No. 1[11, 12]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
(OEControlled)[12, 13]  
Read Cycle No. 2  
ADDRESS  
t
RC  
CE  
t
ACE  
OE  
t
HZOE  
t
DOE  
BHE, BLE  
t
LZOE  
t
HZCE  
t
DBE  
t
LZBE  
t
HZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
I
t
CC  
PU  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
I
SB  
Notes:  
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.  
12. WE is HIGH for read cycle.  
13. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-05148 Rev. *A  
Page 5 of 11  
CY7C1021BV33  
Switching Waveforms (continued)  
Write Cycle No. 1 (CE Controlled) [14, 15]  
t
WC  
ADDRESS  
t
SA  
t
SCE  
CE  
t
AW  
t
HA  
t
PWE  
WE  
t
BW  
BHE, BLE  
t
t
SD  
HD  
DATA I/O  
Write Cycle No. 2 (BLEor BHE Controlled)  
t
WC  
ADDRESS  
t
SA  
t
BW  
BHE, BLE  
t
AW  
t
HA  
t
PWE  
WE  
CE  
t
SCE  
t
t
SD  
HD  
DATA I/O  
Notes:  
14. Data I/O is high impedance if OE or BHE and/or BLE= VIH  
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05148 Rev. *A  
Page 6 of 11  
CY7C1021BV33  
Switching Waveforms (continued)  
Write Cycle No. 3  
Controlled, LOW)  
(WE  
t
WC  
ADDRESS  
t
SCE  
CE  
t
AW  
t
HA  
t
SA  
t
PWE  
WE  
t
BW  
BHE, BLE  
t
HZWE  
t
t
SD  
HD  
DATA I/O  
t
LZWE  
Truth Table  
CE OE WE BLE BHE  
I/O1–I/O8  
High Z  
I/O9–I/O16  
High Z  
Mode  
Power  
Standby (ISB  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
H
L
X
L
X
H
X
L
X
L
Power-Down  
Read - All bits  
)
Data Out  
Data Out  
High Z  
Data Out  
High Z  
)
L
H
L
Read - Lower bits only  
Read - Upper bits only  
Write - All bits  
)
H
L
Data Out  
Data In  
High Z  
)
L
X
L
L
Data In  
Data In  
High Z  
)
L
H
L
Write - Lower bits only  
Write - Upper bits only  
)
H
X
H
Data In  
High Z  
)
L
L
H
X
H
X
X
H
High Z  
Selected, Outputs Disabled  
Selected, Outputs Disabled  
)
High Z  
High Z  
)
Document #: 38-05148 Rev. *A  
Page 7 of 11  
CY7C1021BV33  
Ordering Information  
Package  
Name  
Operating  
Range  
Speed (ns)  
Ordering Code  
Package Type  
8
CY7C1021BV33-8BAC  
CY7C1021BV33-8VC  
CY7C1021BV33L-8VC  
CY7C1021BV33-8ZC  
CY7C1021BV33L-8ZC  
CY7C1021BV33-10BAC  
CY7C1021BV33-10VC  
CY7C1021BV33L-10VC  
CY7C1021BV33-10ZC  
CY7C1021BV33L-10ZC  
CY7C1021BV33-12BAC  
CY7C1021BV33-12VC  
CY7C1021BV33L-12VC  
CY7C1021BV33-12ZC  
CY7C1021BV33L-12ZC  
CY7C1021BV33-12BAI  
CY7C1021BV33-12VI  
CY7C1021BV33-15BAC  
CY7C1021BV33L-15BAC  
CY7C1021BV33-15VC  
CY7C1021BV33L-15VC  
CY7C1021BV33-15ZC  
CY7C1021BV33L-15VC  
CY7C1021BV33-15BAI  
CY7C1021BV33L-15BAI  
CY7C1021BV33-15VI  
CY7C1021BV33L-15ZI  
BA48A  
V34  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
44-Lead (400-Mil) Molded SOJ  
44-Lead (400-Mil) Molded SOJ  
44-Lead TSOP Type II  
Commercial  
Commercial  
Commercial  
V34  
Z44  
Z44  
44-Lead TSOP Type II  
10  
12  
BA48A  
V34  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
44-Lead (400-Mil) Molded SOJ  
44-Lead (400-Mil) Molded SOJ  
44-Lead TSOP Type II  
V34  
Z44  
Z44  
44-Lead TSOP Type II  
BA48A  
V34  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
44-Lead (400-Mil) Molded SOJ  
44-Lead (400-Mil) Molded SOJ  
44-Lead TSOP Type II  
V34  
Z44  
Z44  
44-Lead TSOP Type II  
BA48A  
V34  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
44-Lead (400-Mil) Molded SOJ  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
44-Lead (400-Mil) Molded SOJ  
44-Lead (400-Mil) Molded SOJ  
44-Lead TSOP Type II  
Industrial  
15  
BA48A  
BA48A  
V34  
Commercial  
V34  
Z44  
Z44  
44-Lead TSOP Type II  
BA48A  
BA48A  
V34  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)  
44-Lead (400-Mil) Molded SOJ  
44-Lead TSOP Type II  
Industrial  
Z44  
Shaded areas contain advance information.  
Document #: 38-05148 Rev. *A  
Page 8 of 11  
CY7C1021BV33  
Package Diagrams  
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A  
51-85096-*E  
Document #: 38-05148 Rev. *A  
Page 9 of 11  
CY7C1021BV33  
Package Diagrams (continued)  
44-Lead (400-Mil) Molded SOJ V34  
51-85082-*B  
44-Pin TSOP II Z44  
51-85087-A  
All product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05148 Rev. *A  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY7C1021BV33  
Document History Page  
Document Title: CY7C1021BV33 64K x 16 Static RAM  
Document Number: 38-05148  
Issue  
Orig. of  
Change  
REV.  
**  
*A  
ECN NO. Date  
Description of Change  
109892  
116474  
09/22/01  
09/16/02  
SZV  
CEA  
Change from Spec number: 38-00954 to 38-05148  
Add applications foot note to data sheet, page 1.  
Document #: 38-05148 Rev. *A  
Page 11 of 11  

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CYPRESS

CY7C1021BV33L-15BAIT

 Standard SRAM, 64KX16, 15ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
ROCHESTER

CY7C1021BV33L-15VC

 64K x 16 Static RAM
CYPRESS

CY7C1021BV33L-15VCT

 Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44
CYPRESS

CY7C1021BV33L-15ZC

 64K x 16 Static RAM
CYPRESS

CY7C1021BV33L-15ZCT

 Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, TSOP2-44
CYPRESS

CY7C1021BV33L-15ZI

 64K x 16 Static RAM
CYPRESS

CY7C1021BV33L-15ZIT

 Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, TSOP2-44
CYPRESS

CY7C1021BV33L-8VC

 64K x 16 Static RAM
CYPRESS

CY7C1021BV33L-8ZC

 64K x 16 Static RAM
CYPRESS
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