CY7C1031-8JCT [ROCHESTER]
Cache SRAM, 64KX18, 8.5ns, CMOS, PQCC52, PLASTIC, LCC-52;
| 型号： | CY7C1031-8JCT |
| 厂家： | 
Rochester Electronics |
| 描述： | Cache SRAM, 64KX18, 8.5ns, CMOS, PQCC52, PLASTIC, LCC-52 静态存储器 |
| 文件： | 总13页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1031
CY7C1032
64K x 18 Synchronous Cache RAM
Features
Functional Description
• Supports 66-MHz Pentium® microprocessor cache
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
systems with zero wait states
• 64K by 18 common I/O
• Fast clock-to-output times
— 8.5 ns
The CY7C1031 is designed for Intel® Pentium and i486
• Two-bit wraparound counter supporting Pentium
CPU-based systems; its counter follows the burst sequence of
microprocessor and 486 burst sequence (CY7C1031)
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
• Two-bit wraparound counter supporting linear burst
sequence (CY7C1032)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache
A synchronous self-timed write mechanism is provided to
simplify the write interface. A synchronous chip select input
and an asynchronous output enable input provide easy control
for bank selection and output three-state control.
controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
Logic Block Diagram
Pin Configuration
PLCC
18
Top View
DATA
IN
REGISTER
16
14
A
15
–A
0
7
6
5
4
3
2
1
52 51 50 49 48 47
46
9
9
ADDR
REG
[1]
DQ
DQ
DP
DQ
DQ
V
V
8
9
8
9
0
14
2
45
44
43
42
41
40
39
38
37
36
35
34
7
6
16
V
CCQ
10
11
12
13
14
15
16
17
18
19
20
2
V
SSQ
CCQ
SSQ
ADV
DQ
ADV
LOGIC
10
11
12
13
64K X 9
64K X 9
RAM ARRAY RAM ARRAY
DQ
DQ
DQ
V
DQ
7C1031
7C1032
5
4
3
2
DQ
DQ
DQ
V
V
DQ
DQ
SSQ
WH
WL
CLK
V
CCQ
SSQ
CCQ
ADSP
ADSC
CS
WH
WL
DQ
14
15
TIMING
CONTROL
DQ
1
0
[1]
9
9
DP
1
2122 23 24 25 26 27 28 29 30 31 32 33
18
DQ – DQ
15
0
DP – DP
1
0
OE
Selection Guide
7C1031-8
7C1032-8
7C1031-10
7C1032-10
7C1031-12
Unit
ns
Maximum Access Time
8.5
10
12
Maximum Operating Current
Commercial
280
280
230
mA
Note:
1. DP and DP are functionally equivalent to DQ .
0
1
x
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05278 Rev. *A
Revised April 1, 2004
CY7C1031
CY7C1032
Single Write Accesses Initiated by ADSP
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) CS is LOW and (2) ADSP is LOW.
ADSP-triggered write cycles are completed in two clock
periods. The address at A0 through A15 is loaded into the
address register and address advancement logic and
delivered to the RAM core. The write signal is ignored in this
cycle because the cache tag or other external logic uses this
clock period to perform address comparisons or protection
checks. If the write is allowed to proceed, the write input to the
CY7C1031 and CY7C1032 will be pulled LOW before the next
clock rise. ADSP is ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information
presented at DQ0–DQ15 and DP0–DP1 will be written into the
location specified by the address advancement logic. WL
controls the writing of DQ0–DQ7 and DP0 while WH controls
the writing of DQ8–DQ15 and DP1. Because the CY7C1031
and CY7C1032 are common-I/O devices, the output enable
signal (OE) must be deasserted before data from the CPU is
delivered to DQ0–DQ15 and DP0–DP1. As a safety precaution,
the appropriate data lines are three-stated in the cycle where
WH, WL, or both are sampled LOW, regardless of the state of
the OE input.
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC
is LOW, and (3) WH and WL are HIGH. The address at A0
through A15 is stored into the address advancement logic and
delivered to the RAM core. If the output enable (OE) signal is
asserted (LOW), data will be available at the data outputs a
maximum of 8.5 ns after clock rise. ADSP is ignored if CS is
HIGH.
Burst Sequences
The CY7C1031 provides a 2-bit wraparound counter, fed by
pins A0–A1, that implements the Intel 80486 and Pentium
processor’s address burst sequence (see Table 1). Note that
the burst sequence depends on the first burst address.
Table 1. Counter Implementation for the Intel Pentium/
80486 Processor’s Sequence
First
Second
Third
Fourth
Address
Address
Address
Address
AX + 1,Ax
AX + 1,Ax
AX + 1,Ax
AX + 1,Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC
is LOW, and (3) WH or WL are LOW. ADSC-triggered
accesses are completed in a single clock cycle.
The CY7C1032 provides a 2-bit wraparound counter, fed by
pins A0–A1, that implements a linear address burst sequence
(see Table 2).
The address at A0 through A15 is loaded into the address
register and address advancement logic and delivered to the
RAM core. Information presented at DQ0–DQ15 and DP0–DP1
will be written into the location specified by the address
advancement logic. Since the CY7C1031 and the CY7C1032
are common-I/O devices, the output enable signal (OE) must
be deasserted before data from the cache controller is
delivered to the data and parity lines. As a safety precaution,
the appropriate data and parity lines are three-stated in the
cycle where WH and WL are sampled LOW regardless of the
state of the OE input.
Table 2. Counter Implementation for a Linear Sequence
First
Second
Third
Fourth
Address
Address
Address
Address
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Document #: 38-05278 Rev. *A
Page 2 of 13
CY7C1031
CY7C1032
Application Example
Figure 1 shows a 512-Kbyte secondary cache for the Pentium
microprocessor using four CY7C1031 cache RAMs.
512 KB
66-MHz OSC
CLK
CLK
ADR
DATA
ADS
ADR
DATA
ADSP
ADSC
ADV
7C1031
PENTIUM
PROCESSOR
WH, WL
OE
WH, WL
WH, WL
WH, WL
2
2
2
2
WH ,
1
ADSC ADV OE WH ,
0
WH ,
2
WH ,
3
CLK
ADR
CLK
WL
1
WL
0
WL
2
WL
3
ADR
DATA
ADSP
CD
INTERFACE TO
MAIN MEMORY
CACHE
CACHE
TAG
DATA
CONTROLLER
MATCH
DIRTY
VALID
MATCH
DIRTY
VALID
Figure 1. Cache Using Four CY7C1031s
Pin Definitions
Signal Name
Type
# of Pins
Description
VCC
Input
1
4
1
4
1
16
1
1
1
1
+5V Power
+5V or 3.3V (Outputs)
Ground
Ground (Outputs)
Clock
Address
VCCQ
GND
VSSQ
CLK
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
A15 – A0
ADSP
ADSC
WH
WL
ADV
Address Strobe from Processor
Address Strobe from Cache Controller
Write Enable – High Byte
Write Enable – Low Byte
Advance
Output Enable
Chip Select
1
1
1
OE
CS
DQ15–DQ0
DP1–DP0
Input/Output
Input/Output
16
2
Regular Data
Parity Data
Document #: 38-05278 Rev. *A
Page 3 of 13
CY7C1031
CY7C1032
Pin Descriptions
Signal Name
Input Signals
CLK
I/O
Description
I
I
Clock signal. It is used to capture the address, the data to be written, and the following control
signals: ADSP, ADSC, CS, WH, WL, and ADV. It is also used to advance the on-chip
auto-address-increment logic (when the appropriate control signals have been set).
Sixteen address lines used to select one of 64K locations. They are captured in an on-chip
register on the rising edge of CLK if ADSP or ADSC is LOW. The rising edge of the clock also loads
the lower two address lines, A1–A0, into the on-chip auto-address-increment logic if ADSP or ADSC
is LOW.
A15–A0
ADSP
I
Address strobe from processor. This signal is sampled at the rising edge of CLK. When this input
and/or ADSC is asserted, A0–A15 will be captured in the on-chip address register. It also allows the
lower two address bits to be loaded into the on-chip auto-address-increment logic. If both ADSP
and ADSC are asserted at the rising edge of CLK, only ADSP will be recognized. The ADSP input
should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH.
ADSC
WH
I
I
Address strobe from cache controller. This signal is sampled at the rising edge of CLK. When
this input and/or ADSP is asserted, A0–A15 will be captured in the on-chip address register. It also
allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. The
ADSC input should not be connected to the ADS output of the processor.
Write signal for the high-order half of the RAM array. This signal is sampled by the rising edge
of CLK. If WH is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of
DQ15–DQ8 and DP1 from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WH, is ignored. Note that ADSP has no effect on WH if CS is HIGH.
WL
I
I
Write signal for the low-order half of the RAM array. This signal is sampled by the rising edge
of CLK. If WL is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of
DQ7–DQ0 and DP0 from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WL, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WL, is ignored. Note that ADSP has no effect on WL if CS is HIGH.
Advance. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically
increments the 2-bit on-chip auto-address-increment counter. In the CY7C1032, the address will
be incremented linearly. In the CY7C1031, the address will be incremented according to the
Pentium/486 burst sequence. This signal is ignored if ADSP or ADSC is asserted concurrently with
CS. Note that ADSP has no effect on ADV if CS is HIGH.
ADV
CS
OE
I
I
Chip select. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW,
the SRAM is deselected. If CS is LOW and ADSC or ADSP is LOW, a new address is captured by
the address register. If CS is HIGH, ADSP is ignored.
Output enable. This signal is an asynchronous input that controls the direction of the data I/O pins.
If OE is asserted (LOW), the data pins are outputs, and the SRAM can be read (as long as CS was
asserted when it was sampled at the beginning of the cycle). If OE is deasserted (HIGH), the data
I/O pins will be three-stated, functioning as inputs, and the SRAM can be written.
Bidirectional Signals
DQ15–DQ0
I/O
Sixteen bidirectional data I/O lines. DQ15–DQ8 are inputs to and outputs from the high-order half
of the RAM array, while DQ7–DQ0 are inputs to and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK.
As outputs, they carry the data read from the selected location in the RAM array. The direction of
the data pins is controlled by OE: when OE is HIGH, the data pins are three-stated and can be used
as inputs; when OE is LOW, the data pins are driven by the output buffers and are outputs.
DQ15–DQ8 and DQ7–DQ0 are also three-stated when WH and WL, respectively, is sampled LOW
at clock rise.
DP1–DP0
I/O
Two bidirectional data I/O lines. These operate in exactly the same manner as DQ15–DQ0, but
are named differently because their primary purpose is to store parity bits, while the DQs’ primary
purpose is to store ordinary data bits. DP1 is an input to and an output from the high-order half of
the RAM array, while DP0 is an input to and an output from the lower-order half of the RAM array.
Document #: 38-05278 Rev. *A
Page 4 of 13
CY7C1031
CY7C1032
DC Input Voltage[2] ...........................................–0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC Relative to GND ............ –0.5V to +7.0V
Ambient
DC Voltage Applied to Outputs
Range
Temperature[3]
VCC
VCCQ
in High-Z State[2]...............................................–0.5V to VCC + 0.5V
Com’l
0°C to +70°C
5V ± 5%
3.0V to VCC
Electrical Characteristics Over the Operating Range[4]
7C1031-8
7C1032-8
7C1031-10
7C1032-10
7C1031-12
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
Output Leakage Current
Test Conditions
VCC = Min., IOH = –4.0 mA 2.4
VCC = Min., IOL = 8.0 mA
Min.
Max.
VCCQ
0.4
CC + 0.3V 2.2
0.8
1
Min.
2.4
Max.
VCCQ
0.4
CC + 0.3V 2.2
0.8
1
Min.
2.4
Max.
VCCQ
0.4
CC + 0.3V
0.8
1
5
Unit
V
V
V
V
VOH
VOL
VIH
VIL
IX
2.2
–0.3
–1
–5
V
V
V
–0.3
–1
–5
–0.3
–1
–5
GND ≤ VI ≤ VCC
µA
µA
IOZ
GND ≤ VI ≤ VCC, Output
5
5
Disabled
IOS
ICC
Output Short Circuit
Current[5]
VCC = Max., VOUT = GND
–300
280
–300
280
–300
230
mA
mA
VCC Operating Supply
VCC = Max.,
OUT = 0 mA,
f = fMAX = 1/tCYC
Com’l
Current
I
ISB1
Automatic CE
Max. VCC, CS ≥ Com’l
80
30
80
30
60
30
mA
mA
Power-down
VIH, VIN ≥ VIH or
Current—TTL Inputs
VIN ≤ VIL, f = fMAX
ISB2
Automatic CE
Max. VCC, CS ≥ Com’l
VCC – 0.3V, VIN
CC –0.3VorVIN
0.3V, f = 0[6]
Power-down Current —
CMOS Inputs
≥
V
≤
Capacitance[7]
Parameter
CIN: Addresses
CIN: Other Inputs
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
4.5
5
8
Unit
pF
pF
Com’l
Com’l
Com’l
COUT
Output Capacitance
pF
Notes:
2. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
3. T is the case temperature.
A
4. See the last page for Group A subgroup testing information.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
6. Inputs are disabled, clock is allowed to run at speed.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05278 Rev. *A
Page 5 of 13
CY7C1031
CY7C1032
AC Test Loads and Waveforms
R1
V
CCQ
OUTPUT
ALL INPUT PULSES
OUTPUT
Z = 50Ω
0
3.0V
GND
90%
10%
R = 50Ω
L
90%
10%
R2
5 pF
V =1.5V
L
INCLUDING
JIGAND
≤ 3 ns
≤ 3 ns
(b)[8]
SCOPE
(a)
Switching Characteristics Over the Operating Range[9]
7C1031-8
7C1032-8
7C1031-10
7C1032-10
7C1031-12
Parameter
tCYC
tCH
tCL
tAS
Description
Min. Max. Min. Max. Min. Max. Unit
Clock Cycle Time
Clock HIGH
Clock LOW
15[10]
5
20
8
8
2.5
0.5
20
8
8
2.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
2.5
0.5
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
tAH
tCDV
tDOH
tADS
tADSH
tWES
tWEH
tADVS
tADVH
tDS
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
WH, WL Set-Up Before CLK Rise
WH, WL Hold After CLK Rise
8.5
10
12
3
3
3
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-Up
Chip Select Hold After CLK Rise
Chip Select Sampled to Output High Z[11]
OE HIGH to Output High Z[11]
tDH
tCSS
tCSH
tCSOZ
tEOZ
tEOV
tWEOZ
6
6
6
6
5
6
10
7
7
6
7
12
2
2
2
OE LOW to Output Valid
5
5
8.5
WH or WL Sampled LOW to Output High Z[11, 12]
WH or WL Sampled HIGH to Output Valid[12]
tWEOV
Notes:
8. Resistor values for V
= 5V are: R1 = 1179Ω and R2 = 868Ω. Resistor values for V
= 3.3V are R1 = 317Ω and R2 = 348Ω.
CCQ
CCQ
9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I /I and load capacitance. Shown in (a) and (b) of AC Test Loads.
OL OH
10. Do not use the burst mode, if device operates at a frequency above 50 MHz.
11. t
, t , and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
CSOZ EOZ
WEOZ
12. At any given voltage and temperature, t
min. is less than t
min.
WEOZ
WEOV
Document #: 38-05278 Rev. *A
Page 6 of 13
CY7C1031
CY7C1032
Switching Waveforms
Single Read[13]
t
t
CL
t
CYC
CH
CLK
CS
t
t
CSH
CSS
t
AS
t
AH
ADDRESS
[14]
t
t
ADS
ADSH
ADSP
or
ADSC
t
t
WEH
WES
[15]
WH, WL
t
t
DOH
CDV
DATA OUT
Single Write Timing: Write Initiated by ADSP
t
t
CL
CH
CLK
CS
t
t
CSS
CSH
t
AS
t
AH
ADDRESS
ADSP
t
t
ADSH
ADS
t
t
WEH
WES
[15]
WH, WL
t
t
DH
DS
DATA IN
DATA OUT
t
EOZ
OE
Notes:
13. OE is LOW throughout this operation.
14. If ADSP is asserted while CS is HIGH, ADSP will be ignored.
15. ADSP has no effect on ADV, WL, and WH if CS is HIGH.
Document #: 38-05278 Rev. *A
Page 7 of 13
CY7C1031
CY7C1032
Switching Waveforms (continued)
Single Write Timing: Write Initiated by ADSC
t
t
CL
CH
CLK
t
t
CSH
CSS
CS
t
AS
t
AH
ADDRESS
t
t
ADSH
ADS
ADSC
t
t
WEH
WES
WH, WL
t
t
DH
DS
DATA IN
DATA OUT
t
EOZ
OE
Burst Read Sequence with Four Accesses
CLK
t
t
CSS
CSH
CS
t
AS
t
AH
ADDRESS
[14]
t
t
ADS
ADSH
ADSP
or
ADSC
t
t
ADVH
ADVS
[15]
ADV
t
t
WEH
[15]
WES
WH,WL
OE
t
t
DOH
CDV
DATA OUT
DATA0
DATA1
DATA2
DATA3
Document #: 38-05278 Rev. *A
Page 8 of 13
CY7C1031
CY7C1032
Switching Waveforms (continued)
Output (Controlled by OE)
DATA OUT
OE
t
t
EOV
EOZ
Write Burst Timing: Write Initiated by ADSC
CLK
t
t
CSH
CSS
CS
t
t
WEH
WES
WH, WL
OE
t
t
ADS
ADSH
[14]
ADSP
t
t
ADSH
ADS
ADSC
ADDR
t
AS
t
AH
t
t
ADVH
ADVS
ADV
t
t
DH
DS
DATA
DATA0
DATA1
DATA2
DATA3
Document #: 38-05278 Rev. *A
Page 9 of 13
CY7C1031
CY7C1032
Switching Waveforms (continued)
Write Burst Timing: Write Initiated by ADSP
CLK
t
t
CSH
CSS
CS
[15]
WH,
WL
OE
ADSC
t
t
ADSH
ADS
[14]
ADSP
t
AS
t
AH
ADDR
[15]
t
t
ADVS ADVH
ADV
t
t
DS
DH
DATA
DATA1
DATA2
DATA3
DATA0
Output Timing (Controlled by CS)
CLK
t
t
ADSH
ADS
t
t
ADS
ADSH
ADSC
t
t
CSH
CSS
t
t
CSH
CSS
CS
t
t
CSOZ
CDV
DATA OUT
Document #: 38-05278 Rev. *A
Page 10 of 13
CY7C1031
CY7C1032
Switching Waveforms (continued)
Output Timing (Controlled by WH/ WL)
CLK
t
ADSH
t
t
t
ADSH
ADS
ADS
ADSC and
ADSP
t
t
WEH
WES
WH, WL
t
t
WEOZ
WEOV
DATA OUT
Truth Table
Input
CS ADSP ADSC ADV WH or WL CLK
Address
Operation
Chip deselected
L→H Same address as previous cycle Read cycle (ADSP ignored)
H
H
H
H
H
L
L
L
X
X
X
X
X
L
L
L
L
L
H
H
H
H
X
L
X
H
L
H
L
X
X
X
L
X
H
H
L
L→H N/A
L→H Incremented burst address
L→H Same address as previous cycle Write cycle (ADSP ignored)
L→H Incremented burst address
L→H External
L→H External
L→H External
L→H Incremented burst address
L→H Incremented burst address
Read cycle, in burst sequence (ADSP ignored)
L
Write cycle, in burst sequence (ADSP ignored)
Read cycle, begin burst
Read cycle, begin burst
Write cycle, begin burst
Write cycle, in burst sequence
Read cycle, in burst sequence
L
X
H
L
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
H
L→H Same address as previous cycle Write cycle
L→H Same address as previous cycle Read cycle
Ordering Information
Speed
Package
Operating
Range
(ns)
8
Ordering Code
Name
J69
Package Type
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
52-lead Plastic Leaded Chip Carrier
CY7C1031-8JC
CY7C1031-10JC
CY7C1031-12JC
CY7C1032-8JC
CY7C1032-10JC[16]
Commercial
Commercial
Commercial
Commercial
Commercial
10
12
8
J69
J69
J69
J69
10
Note:
16. EOL (End of Life).
Document #: 38-05278 Rev. *A
Page 11 of 13
CY7C1031
CY7C1032
Package Diagram
52-Lead Plastic Leaded Chip Carrier J69
MIN.
MAX.
DIMENSIONS IN INCHES
SEATING PLANE
PIN #1 ID
7
1
47
8
46
0.013
0.021
0.750
0.756
0.045
0.055
0.690
0.730
0.785
0.795
20
34
0.023
0.033
21
33
0.020 MIN.
0.750
0.756
0.090
0.130
0.165
0.200
51-85004-*A
0.785
0.795
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-05278 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1031
CY7C1032
Document History Page
Document Title: CY7C1031/CY7C1032 64K x 18 Synchronous Cache RAM
Document Number: 38-05278
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number: 38-00219 to 38-05278
114203
3/19/02
DSG
*A
212291
See ECN
VBL
Update ordering info by deleting CY7C1032-12 by adding EOL note to
CY7C1032-10
Document #: 38-05278 Rev. *A
Page 13 of 13
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