CY7C1041BL-25VCT [ROCHESTER]
Standard SRAM, 256KX16, 25ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44;
| 型号： | CY7C1041BL-25VCT |
| 厂家： | 
Rochester Electronics |
| 描述： | Standard SRAM, 256KX16, 25ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1041B
256K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Features
• High speed
— tAA = 12 ns
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1041B is a high-performance CMOS static RAM
The CY7C1041B is available in
a
standard 44-pin
organized as 262,144 words by 16 bits.
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configuration
SOJ
INPUT BUFFER
TSOP II
Top View
A
44
1
0
A
A
17
0
A
43
42
41
40
39
38
37
36
35
34
33
1
A
A
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
A
2
A
A
15
2
I/O0–I/O7
I/O8–I/O15
256K x 16
ARRAY
1024 x 4096
A
3
A
OE
3
A
4
BHE
BLE
A
4
A
5
CE
A
6
I/O
I/O
0
15
A
7
I/O
I/O
I/O
1
14
13
12
A
8
I/O
2
I/O
V
I/O
3
V
SS
CC
COLUMN
V
V
SS
CC
DECODER
32
I/O
I/O
I/O
4
5
6
7
11
10
9
8
31
30
29
28
27
26
25
I/O
I/O
I/O
I/O
I/O
WE 17
NC
BHE
18
A
A
14
5
WE
CE
OE
19
A
A
6
13
A
20
21
22
A
12
11
7
BLE
A
A
24
23
8
A
A
10
9
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05142 Rev. *A
Revised March 24, 2005
CY7C1041B
Selection Guide
7C1041B-12 7C1041B-15 7C1041B-17 7C1041B-20 7C1041B-25
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
12
200
220
3
15
190
210
3
17
180
200
3
20
170
190
3
25
160
180
3
Com’l
Ind’l
Com’l
Com’l
Ind’l
Maximum CMOS Standby
Current
mA
L
-
-
0.5
6
0.5
6
0.5
6
0.5
6
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Range
Commercial
Industrial
Temperature[2]
0°C to +70°C
VCC
5V ± 0.5
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
–40°C to +85°C
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1041B-12
7C1041B-15
7C1041B-17
Parameter
VOH
VOL
Description
Test Conditions
Min.
2.4
Max.
Min.
2.4
Max.
Min.
2.4
Max. Unit
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
V
0.4
0.4
0.4
V
V
VIH
2.2
VCC
2.2
VCC
2.2
VCC
+ 0.5
+ 0.5
+ 0.5
VIL
IIX
IOZ
Input LOW Voltage[1]
Input Load Current
Output Leakage
Current
–0.5
–1
–1
0.8
+1
+1
–0.5
–1
–1
0.8
+1
+1
–0.5
–1
–1
0.8
+1
+1
V
mA
mA
GND < VI < VCC
GND < VOUT < VCC
,
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
Com’l
Ind’l
200
220
40
190
210
40
180
200
40
mA
mA
mA
f = fMAX = 1/tRC
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
Automatic CE
VIN < VIL, f = fMAX
ISB2
Max. VCC
,
Com’l
Com’l
3
-
-
3
0.5
6
3
0.5
6
mA
mA
mA
Power-Down Current CE > VCC – 0.3V,
L
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0 Ind’l
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. T is the case temperature.
A
Document #: 38-05142 Rev. *A
Page 2 of 11
CY7C1041B
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
7C1041B-20
7C1041B-25
Parameter
VOH
VOL
VIH
VIL
IIX
Description
Min.
2.4
Max.
Min.
2.4
Max.
Unit
V
V
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
0.4
VCC+ 0.5
0.8
0.4
VCC + 0.5
0.8
2.2
–0.5
–1
2.2
–0.5
–1
GND < VI < VCC
+1
+1
+1
+1
mA
mA
IOZ
Output Leakage
GND < VOUT < VCC
,
–1
–1
Current
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
Com’l
Ind’l
170
190
40
160
180
40
mA
mA
mA
f = fMAX = 1/tRC
ISB1
Automatic CE
Max. VCC, CE > VIH
VIN > VIH or
Power-Down Current
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Max. VCC
,
Com’l
Com’l
Ind’l
3
0.5
6
3
0.5
6
mA
mA
mA
Power-Down Current
—CMOS Inputs
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
L
Capacitance[3]
Parameter
Description
Test Conditions
Max.
Unit
CIN
COUT
Input Capacitance
I/O Capacitance
TA = 25°C, f = 1 MHz,
8
8
pF
pF
V
CC = 5.0V
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
3.0V
90%
10%
OUTPUT
R2
R2
GND
≤ 3 ns
30 pF
5 pF
255Ω
255Ω
≤ 3 ns
INCLUDING
INCLUDING
JIG AND
SCOPE
JIG AND
SCOPE
(b)
(a)
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05142 Rev. *A
Page 3 of 11
CY7C1041B
Switching Characteristics[4] Over the Operating Range
7C1041B-12
7C1041B-15
7C1041B-17
Parameter
Read Cycle
tpower
tRC
tAA
tOHA
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
12
1
15
1
17
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
12
15
17
3
3
3
tACE
tDOE
12
6
15
7
17
7
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[8, 9]
0
3
0
0
3
0
0
3
0
6
6
7
7
7
7
12
6
15
7
17
7
0
0
0
6
7
7
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
Byte Enable to End of Write
12
10
10
0
0
10
7
15
12
12
0
0
12
8
17
14
14
0
0
14
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
3
0
3
0
3
6
7
7
10
12
12
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
started.
time has to be provided initially before a read/write operation is
power
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. The internal write time of the memory is defined by the overlap of CELOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05142 Rev. *A
Page 4 of 11
CY7C1041B
Switching Characteristics[4] Over the Operating Range (continued)
7C1041B-20
7C1041B-25
Parameter
Read Cycle
tpower
tRC
tAA
tOHA
Description
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
20
1
25
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
20
25
3
5
tACE
tDOE
20
8
25
10
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
5
0
8
8
10
10
tPD
tDBE
20
8
25
10
tLZBE
tHZBE
WRITE CYCLE[8, 9]
0
0
8
10
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
Byte Enable to End of Write
20
13
13
0
0
13
9
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
15
10
0
0
3
5
8
10
13
15
Data Retention Characteristics Over the Operating Range (L version only)
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions[11]
Min.
Max.
Unit
V
VDR
2.0
ICCDR
Com’l
L
VCC = VDR = 3.0V,
CE > VCC – 0.3V,
IN > VCC – 0.3V or VIN < 0.3V
200
mA
ns
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
V
[10]
tR
tRC
ns
Notes:
10. t < 3 ns for the -12 and -15 speeds. t < 5 ns for the -20 and slower speeds.
r
r
11. No input may exceed V + 0.5V.
CC
Document #: 38-05142 Rev. *A
Page 5 of 11
CY7C1041B
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
t
R
V
VCC
CE
DR
t
CDR
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
DATA VALID
t
LZCE
t
PD
t
PU
50%
50%
SUPPLY
CURRENT
Notes:
12. Device is continuously selected. OE, CE, BHE, and/or BHE = V .
IL
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05142 Rev. *A
Page 6 of 11
CY7C1041B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Notes:
15. Data I/O is high impedance if OE or BHE and/or BLE= V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05142 Rev. *A
Page 7 of 11
CY7C1041B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O0–I/O7
High Z
I/O8–I/O15
High Z
Mode
Power Down
Read All bits
Power
Standby (ISB)
X
L
X
H
H
H
L
X
L
L
Data Out
Data Out
High Z
Data Out
High Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
L
H
L
Read Lower bits only
Read Upper bits only
Write All bits
L
L
H
L
Data Out
Data In
High Z
L
X
X
X
H
L
Data In
Data In
High Z
L
L
L
H
L
Write Lower bits only
Write Upper bits only
Selected, Outputs Disabled
L
L
H
X
Data In
High Z
L
H
X
High Z
Document #: 38-05142 Rev. *A
Page 8 of 11
CY7C1041B
Ordering Information
Speed
Package
Name
Operating
Range
Commercial
(ns)
Ordering Code
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead TSOP Type II
44-Lead TSOP Type II (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II (Pb-free)
44-Lead TSOP Type II
44-Lead TSOP Type II (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
12
CY7C1041B-12VC
CY7C1041B-12VXC
CY7C1041B-12ZC
CY7C1041B-12ZXC
CY7C1041B-15VC
CY7C1041B-15VXC
CY7C1041BL-15VC
CY7C1041B-15ZC
CY7C1041B-15ZXC
CY7C1041BL-15ZC
CY7C1041BL-15ZXC
CY7C1041B-17VC
CY7C1041BL-17VC
CY7C1041B-17ZC
CY7C1041BL-17ZC
CY7C1041B-20VC
CY7C1041B-20VXC
CY7C1041BL-20VC
CY7C1041BL-20VXC
CY7C1041B-20ZC
CY7C1041B-20ZXC
CY7C1041BL-20ZC
CY7C1041B-25VC
CY7C1041BL-25VC
CY7C1041B-25ZC
CY7C1041BL-25ZC
CY7C1041B-15ZI
CY7C1041B-15ZXI
CY7C1041B-15VI
CY7C1041B-15VXI
CY7C1041B-17ZI
CY7C1041B-17VI
CY7C1041B-20ZI
CY7C1041B-20ZXI
CY7C1041B-20VI
CY7C1041B-20VXI
CY7C1041B-25ZI
CY7C1041B-25VI
V34
V34
Z44
Z44
V34
V34
V34
Z44
Z44
Z44
Z44
V34
V34
Z44
Z44
V34
V34
V34
V34
Z44
Z44
Z44
V34
V34
Z44
Z44
Z44
Z44
V34
V34
V34
Z44
Z44
Z44
Z44
Z44
Z44
Z44
15
17
20
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead TSOP Type II
44-Lead TSOP Type II (Pb-free)
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
25
15
44-Lead TSOP Type II
44-Lead TSOP Type II
Industrial
44-Lead TSOP Type II (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II (Pb-free)
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ (Pb-free)
44-Lead TSOP Type II
17
20
25
44-Lead (400-Mil) Molded SOJ
Document #: 38-05142 Rev. *A
Page 9 of 11
CY7C1041B
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
44-Pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05142 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1041B
Document History Page
Document Title: CY7C1041B 256K x 16 Static RAM
Document Number: 38-05142
Issue
Orig. of
Change
SZV
REV.
**
ECN NO. Date
109886
Description of Change
Change from Spec number: 38-00938 to 38-05142
09/15/01
*A
341401
See ECN AJU
Added Pb-free ordering information
Document #: 38-05142 Rev. *A
Page 11 of 11
相关型号：
CY7C1041BN-15VXCT
Standard SRAM, 256KX16, 15ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
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