CY7C1360A-150ACT [ROCHESTER]
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1360A-150ACT |
| 厂家： | 
Rochester Electronics |
| 描述： | Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总29页 (文件大小：1245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1360A
CY7C1362A
256K x 36/512K x 18 Synchronous
Pipelined Burst SRAM
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), depth-expansion
Chip Enables (CE2 and CE3), burst control inputs (ADSC,
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and
BWE), and global Write (GW). However, the CE3 chip enable
input is only available for the TA package version.
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225, 200, 166, and 150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V-tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for A package version and two chip
enables for BG and AJ package versions
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
• Address pipeline capability
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down feature available using ZZ
mode or CE deselect
• JTAG boundary scan for BG and AJ package version
• Low-profile119-bump,14-mm×22-mmPBGA(BallGrid
Array) and 100-pin TQFP packages
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the BGA and TQFP AJ package versions, four pins are
used to implement JTAG test capabilities: Test Mode Select
(TMS), Test Data-In (TDI), Test Clock (TCK), and Test
Data-Out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation. The
TA package version does not offer the JTAG capability.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A and CY7C1362A operate from a +3.3V
power supply. All inputs and outputs are LVTTL-compatible.
The CY7C1360A and CY7C1362A SRAMs integrate 262,144
×
36 and 524,288 × 18 SRAM cells with advanced
Selection Guide
7C1360A-225
7C1362A-225
7C1360A-200
7C1362A-200
7C1360A-166
7C1362A-166
7C1360A-150
7C1362A-150
Unit
ns
Maximum Access Time
2.5
650
10
3.0
600
10
3.5
520
10
3.5
460
10
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05258 Rev. *C
Revised January 18, 2003
CY7C1360A
CY7C1362A
Functional Block Diagram—256K × 36[1]
BYTE a WRITE
BW
a
BWE
D
Q
CLK
BYTE b WRITE
BW
b
D
Q
GW
BYTE c WRITE
BW
c
D
Q
BYTE d WRITE
BW
d
D
Q
CE
ENABLE
1
CE
D
Q
D
Q
2
[2]
CE
3
OE
ZZ
Power Down Logic
Input
Register
ADSP
16
A
Address
Register
OUTPUT
REGISTER
ADSC
DQa,DQb
DQc,DQd
DQa, DQb,
DQc, DQd
CLR
D
Q
ADV
Binary
Counter
& Logic
A0-A1
MODE
Functional Block Diagram—512K × 18[1]
BYTE b
WRITE
BW
b
D
Q
BWE
CLK
BYTE a
WRITE
BW
a
D
Q
GW
ENABLE
CE
1
CE
CE
D
Q
D
Q
2
3
[2]
ZZ
Power Down Logic
OE
ADSP
Input
Register
17
A
Address
Register
OUTPUT
REGISTER
ADSC
DQa, DQb,
DQa,DQb
CLR
D
Q
ADV
Binary
Counter
& Logic
A0-A1
MODE
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
2. CE3 is for A version only.
Document #: 38-05258 Rev. *C
Page 2 of 28
CY7C1360A
CY7C1362A
Pin Configurations
CY7C1360A
256K × 36 100-p
in TQFP
Top View
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
1
DQb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
3
4
5
6
7
8
9
V
CCQ
V
CCQ
V
SS
V
SS
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
CCQ
V
CCQ
DQc
DQc
NC
DQb
DQb
V
SS
V
CC
NC
NC
100-pin TQFP
A Version
100-pin TQFP
AJ Version
V
CC
VSS
V
ZZ
SS
ZZ
DQa
DQa
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
DQd
DQd
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
V
V
CCQ
CCQ
V
SS
V
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQa
DQa
V
SS
V
SS
V
CCQ
V
CCQ
DQd
DQd
DQd
DQa
DQa
DQa
CY7C1362A
512K × 18 100-p
in TQFP
Top View
NC
NC
NC
NC
NC
NC
A
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
NC
NC
V
V
V
CCQ
CCQ
CCQ
CCQ
V
V
SS
V
SS
V
SS
SS
NC
NC
DQb
DQb
NC
NC
DQb
DQb
NC
NC
DQa
DQa
DQa
DPa
DQa
DQa
9
9
V
V
SS
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
V
CCQ
V
CCQ
DQb
DQb
NC
V
CCQ
CCQ
DQb
DQb
NC
DQa
DQa
DQa
DQa
V
V
SS
SS
V
V
CC
100-pin TQFP
A Version
NC
CC
100-pin TQFP
AJ Version
NC
NC
NC
V
V
CC
CC
V
V
SS
ZZ
DQa
DQa
SS
ZZ
DQa
DQa
DQb
DQb
DQb
DQb
V
V
V
CCQ
V
CCQ
CCQ
CCQ
V
V
SS
V
SS
V
SS
SS
DQb
DQb
DQb
NC
DQb
DQb
DQb
NC
DQa
DQa
NC
DQa
DQa
NC
NC
NC
V
V
SS
V
SS
V
SS
SS
V
V
CCQ
NC
NC
NC
V
CCQ
NC
NC
NC
V
CCQ
DDQ
NC
NC
NC
NC
NC
NC
Document #: 38-05258 Rev. *C
Page 3 of 28
CY7C1360A
CY7C1362A
Pin Configurations (continued)
CY7C1360A 256K × 36 119-ball BGA Top View
1
2
3
A
4
ADSP
ADSC
VCC
NC
5
A
6
7
A
B
C
D
E
F
VCCQ
NC
A
A
VCCQ
NC
CE2
A
A
A
A
NC
A
A
A
NC
DQc
DQc
VCCQ
DQc
DQc
VCCQ
DQd
DQd
VCCQ
DQd
DQd
NC
DQc
DQc
DQc
DQc
DQc
VCC
DQd
DQd
DQd
DQd
DQd
A
VSS
VSS
VSS
BWc
VSS
NC
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQb
DQb
DQb
DQb
DQb
VCC
DQa
DQa
DQa
DQa
DQa
A
DQb
DQb
VCCQ
DQb
DQb
VCCQ
DQa
DQa
VCCQ
DQa
DQa
NC
CE
OE
G
H
J
ADV
GW
VCC
CLK
NC
K
L
VSS
BWd
VSS
VSS
VSS
MODE
A
M
N
P
R
T
BWE
A1
A0
VCC
A
NC
NC
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1362A 512K × 18 119-ball BGA Top View
1
2
3
A
4
ADSP
ADSC
VCC
NC
5
A
6
7
A
B
C
D
E
F
VCCQ
NC
A
A
VCCQ
NC
CE2
A
A
A
CE3
A
NC
A
A
NC
DQb
NC
NC
DQb
NC
DQb
NC
VCC
DQb
NC
DQb
NC
DQb
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
DQa
NC
DQa
NC
DQa
VCC
NC
DQa
NC
DQa
NC
A
NC
CE
DQa
VCCQ
DQa
NC
VCCQ
NC
OE
G
H
J
ADV
GW
VCC
CLK
NC
DQb
VCCQ
NC
VCCQ
DQa
NC
K
L
DQb
VCCQ
DQb
NC
M
N
P
R
T
BWE
A1
VCCQ
NC
A0
DQa
NC
NC
VCC
NC
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05258 Rev. *C
Page 4 of 28
CY7C1360A
CY7C1362A
256K × 36 Pin Descriptions
X36 PBGA Pins
X36 QFP Pins
Name
A0
A1
Type
Description
Addresses: These inputs are registered and must meet
4P
4N
37
36
Input-
Synchronous the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
2A,3A,5A,6A,3B,5B, 35, 34, 33, 32, 100, A
6B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
99, 82, 81, 44, 45,
46, 47, 48, 49, 50
92 (AJ Version)
43 (A Version)
5L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Byte Write: A byte Write is LOW for a Write cycle and
5G
3G
3L
Synchronous HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, condi-
tioned by BWE being LOW.
4M
4H
87
88
BWE
GW
Input-
Write Enable: This active LOW input gates byte Write
Synchronous operations and must meet the set-up and hold times
around the rising edge of CLK.
Input-
Global Write: This active LOW input allows a full 36-bit
Synchronous Write to occur independent of the BWE and BWn lines
andmustmeettheset-upandholdtimesaroundtherising
edge of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip
Synchronous enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
4E
2B
98
97
CE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
CE2
CE3
Input-
Chip Enable: This active HIGH input is used to enable
Synchronous the device.
–
92
Input-
Chip Enable: This active LOW input is used to enable the
(not available for
PBGA)
(for A version only)
Synchronous device. Not available for BG and AJ package versions.
4F
86
83
OE
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
4G
ADV
Input-
Address Advance: This active LOW input is used to
Synchronous control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input,
Synchronous alongwithCEbeingLOW, causesanewexternaladdress
to be registered and a Read cycle is initiated using the
new address.
Input-
Address Status Controller: This active LOW input
Synchronous causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Input-
Sleep: This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal operation,
this input has to be either LOW or NC (No Connect).
Document #: 38-05258 Rev. *C
Page 5 of 28
CY7C1360A
CY7C1362A
256K × 36 Pin Descriptions (continued)
X36 PBGA Pins
(a) 6P, 7P, 7N, 6N, 6M, (a) 51, 52, 53, 56, DQa
6L, 7L, 6K, 7K, 57, 58, 59, 62, 63 DQb
(b) 7H, 6H, 7G, 6G, 6F, (b) 68, 69, 72, 73, DQc
6E, 7E, 7D, 6D, 74, 75, 78, 79, 80 DQd
(c) 2D, 1D, 1E, 2E, 2F, (c) 1, 2, 3, 6, 7, 8, 9,
1G, 2G, 1H, 2H, 12, 13
(d) 1K, 2K, 1L, 2L, 2M, (d) 18, 19, 22, 23,
X36 QFP Pins
Name
Type
Description
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
1N, 2N, 1P, 2P
24, 25, 28, 29, 30
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not
available for A package version.
for BG and AJ
version
5U
42
TDO
VCC
Output
IEEE 1149.1 test output. LVTTL-level output. Not
available for A package version.
for BG and AJ
version
4C, 2J, 4J, 6J, 4R
15, 41, 65, 91
Power Supply Core power supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26, VSS
3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71,
Ground
Ground: GND.
5M, 3N, 5N, 3P, 5P
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,
1M, 7M, 1U, 7U 61, 70, 77
76, 90
VCCQ
NC
I/O Power
Supply
Power Supply for the I/O circuitry
1B,7B,1C,7C,4D,3J, 14, 16, 66
-
No Connect: These signals are not internally connected.
5J, 4L, 1R, 5R, 7R, 1T, 38, 39, 42 for A
User can leave it floating or connect it to VCC or VSS.
2T, 6T, 6U
version
512K × 18 Pin Descriptions
X18 PBGA Pins
4P
4N
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32, 100, A
5B, 6B, 2C, 3C, 5C, 99, 82, 81, 80, 48,
6C,2R,6R,2T,3T,5T, 47, 46, 45, 44, 49,
X18 QFP Pins
Name
Type
Description
37
36
A0
A1
Input-
Addresses: These inputs are registered and must meet
Synchronous the set up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
6T
50
92 (AJ Version)
43 (A Version)
5L
3G
93
94
BWa
BWb
Input-
Byte Write Enables: A byte Write enable is LOW for a
Synchronous WritecycleandHIGHfor aReadcycle. BWacontrolsDQa.
BWb controls DQb. Data I/O are high impedance if either
of these inputs are LOW, conditioned by BWE being LOW.
4M
4H
87
88
BWE
GW
Input-
Write Enable: This active LOW input gates byte Write
Synchronous operations and must meet the set-up and hold times
around the rising edge of CLK.
Input-
Global Write: This active LOW input allows a full 18-bit
Synchronous Write to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising
edge of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip
Synchronous enables, Write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
4E
2B
98
97
CE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
CE2
Input-
Synchronous device.
Chip Enable: This active HIGH input is used to enable the
Document #: 38-05258 Rev. *C
Page 6 of 28
CY7C1360A
CY7C1362A
512K × 18 Pin Descriptions (continued)
X18 PBGA Pins
X18 QFP Pins
92
Name
Type
Description
Chip Enable: This active LOW input is used to enable the
–
CE3
Input-
(not available for
PBGA)
(for A Version only)
Synchronous device. Not available for BG and AJ package versions.
4F
86
83
OE
Input
Output Enable: This active LOW asynchronous input
enables the data output drivers.
4G
ADV
Input-
Address Advance: This active LOW input is used to
Synchronous control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This activeLOWinput, along
Synchronous with CE being LOW, causes a new external address to be
registered and a Read cycle is initiated using the new
address.
Input-
Address Status Controller: This active LOW input
Synchronous causes device to be deselectedor selectedalongwith new
external address to be registered. A Read or Write cycle
is initiated depending upon Write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. An NC or HIGH on this pin
selects Interleaved Burst.
Input-
Sleep:This active HIGH inputputs thedevice in low power
Asynchronous consumption standby mode. For normal operation, this
input has to be either LOW or NC (No Connect).
(a)6D,7E,6F,7G,6H, (a) 58, 59, 62, 63, DQa
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. HighByte is DQb.
Input data must meet set up and hold times around the
rising edge of CLK.
7K, 6L, 6N, 7P
68, 69, 72, 73, 74 DQb
(b) 8, 9, 12, 13, 18,
19, 22, 23, 24
(b) 1D, 2E, 2G, 1H,
2K, 1L, 2M, 1N, 2P
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not
available for A package version.
for BG and AJ
versions
5U
42
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not
for BG and AJ
available for A package version.
version
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
Supply
Ground
Core power supply: +3.3V –5% and +10%
Ground: GND.
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26, VSS
5F, 5G, 3H, 5H, 3K, 40, 55, 60, 67, 71,
5K, 3L, 3M, 5M, 3N, 76, 90
5N, 3P, 5P
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,
1M, 7M, 1U, 7U 61, 70, 77
VCCQ
I/O Power
Supply
Power Supply for the I/O circuitry
1B, 7B, 1C, 7C, 2D, 1–3, 6, 7, 14, 16, NC
4D, 7D, 1E, 6E, 2F, 25, 28–30, 51–53,
1G, 6G, 2H, 7H, 3J, 56, 57, 66, 75, 78,
5J, 1K, 6K, 2L, 4L, 7L, 79, 80, 95, 96
6M, 2N, 7N, 1P, 6P, 38, 39, 42 for A
1R, 5R, 7R, 1T, 4T, 6U Version
–
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS
.
Document #: 38-05258 Rev. *C
Page 7 of 28
CY7C1360A
CY7C1362A
Write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
Introduction
Functional Overview
ADSP triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BWx
signals. The CY7C1360A/CY7C1362A provides byte Write
capability that is described in the Write cycle description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1360A and BWa,b for
CY7C1362A) input will selectively write to only the desired
bytes. Bytes not selected during a byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.8 ns
(133-MHz device).
The CY7C1360A/CY7C1362A supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1360A/CY7C1362A is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for 1360A and BWa,b
for 1362A) inputs. A Global Write Enable (GW) overrides all
byte Write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed Write circuitry.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the Write inputs (GW, BWE,
and BWx) are asserted active to conduct a Write to the desired
byte(s). ADSC triggered Write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global Write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte Write is conducted,
only the selected bytes are written. Bytes not selected during
a byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within preliminary ns (200-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Because the CY7C1360A/CY7C1362A is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a Write cycle is
detected, regardless of the state of OE.
Burst Sequences
The CY7C1360A/CY7C1362A provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel® Pentium® applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Document #: 38-05258 Rev. *C
Page 8 of 28
CY7C1360A
CY7C1362A
Burst Address Table (MODE = NC/V
)
Burst Address Table (MODE = GND)
CC
First
Address (ex-
ternal)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A[1:0]]
00
A[1:0]
A[1:0]
A[1:0]
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
01
10
11
Truth Table[3, 4, 5, 6, 7, 8, 9]
Next Cycle
Unselected
Address Used ZZ CE3 CE2 CE1 ADSP ADSC ADV
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
None
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1
X
1
X
X
0
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
X
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
X
1
1
X
1
X
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
X
X
X
X
X
X
X
Unselected
None
Unselected
None
X
1
Unselected
None
X
0
Unselected
None
X
0
Begin Read
External
External
Next
1
Begin Read
0
1
Hi-Z Read
Hi-Z Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
Next
0
DQ
Hi-Z Read
DQ Read
Hi-Z Read
DQ Read
Hi-Z Read
DQ Read
Read
Next
1
Next
0
Current
Current
Current
Current
Current
Current
External
Next
1
0
1
0
X
X
X
X
X
X
X
X
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Hi-Z Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
X
X
Next
Current
Current
None
ZZ “sleep”
Hi-Z
X
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd.
5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.
7. For a Write operation following a Read operation, OE must be HIGH before the input-data-required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05258 Rev. *C
Page 9 of 28
CY7C1360A
CY7C1362A
Partial Truth Table for Read/Write[10]
Function (1360A)
GW
1
BWE
1
BWd
X
1
BWc
X
1
BWb
X
1
BWa
X
1
Read
Read
1
0
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1362A)
GW
1
BWE
BWb
BWa
Read
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
1
Write Byte 0 – DQ[7:0] and DP0
Write Byte 1 – DQ[15:8] and DP1
Write All Bytes
1
1
1
Write All Bytes
0
Sleep Mode
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
Min.
Max.
10
Unit
mA
ns
IDDZZ
tZZS
2tCYC
tZZREC
2tCYC
ns
Note:
10. For the X18 product, there are only BWa and BWb.
Document #: 38-05258 Rev. *C
Page 10 of 28
CY7C1360A
CY7C1362A
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Never-
theless, the device supports the standard TAP controller archi-
tecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1-compliant TAPs. The TAP operates
using LVTTL/ LVCMOS logic level signaling.
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
TAP Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two LSBs of the serial instruction
register are loaded with a binary “01” pattern to allow for fault
isolation of the board-level serial test data path.
Test Access Port
TCK–Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS–Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
)
TDI–Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1, TAP Controller State Diagram). It is
allowable to leave this pin unconnected if it is not used in an
application. The pin is pulled up internally, resulting in a logic
HIGH level. TDI is connected to the Most Significant Bit (MSB)
of any register (see Figure 2.).
Boundary Scan Register
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for the x36 device and
51 bits for the x18 device. The boundary scan register, under
the control of the TAP controller, is loaded with the contents of
the device I/O ring when the controller is in Capture-DR state
and then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
TDO–Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the Least Signif-
icant Bit (LSB) of any register (see Figure 2.).
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name, the third column is the
TQFP pin number, and the fourth column is the BGA bump
number.
Document #: 38-05258 Rev. *C
Page 11 of 28
CY7C1360A
CY7C1362A
Identification (ID) Register
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
TAP Controller Instruction Set
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
Overview
There are two classes of instructions defined in IEEE Standard
1149.1-1990; the standard (public) instructions and device
specific (private) instructions. Some public instructions are
mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Although the TAP controller in this device follows IEEE 1149.1
conventions, it is not IEEE 1149.1-compliant because some of
the mandatory instructions are not fully implemented. The TAP
on this device may be used to monitor all input and I/O pads,
but can not be used to load address, data, or control signals
into the device or to preload the I/O buffers. In other words, the
device will not perform IEEE 1149.1 EXTEST, INTEST, or the
preload portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not imple-
mented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
BYPASS
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
IDCODE
Do not use these instructions. They are reserved for future
use.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
Document #: 38-05258 Rev. *C
Page 12 of 28
CY7C1360A
CY7C1362A
TEST-LOGIC
RESET
1
0
0
1
1
1
REUN-TEST/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05258 Rev. *C
Page 13 of 28
CY7C1360A
CY7C1362A
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register [12]
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Test Conditions
Min.
2.0
Max.
VCC + 0.3
0.8
Unit
V
VIH
VIl
Input High (Logic 1) Voltage[13, 14]
Input Low (Logic 0) Voltage[13, 14]
Input Leakage Current
–0.3
–5.0
–30
–5.0
V
ILI
0V < VIN < VCC
5.0
µA
µA
µA
ILI
TMS and TDI Input Leakage Current 0V < VIN < VCC
30
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
5.0
VOLC
VOHC
VOLT
LVCMOS Output Low Voltage[13, 15] IOLC = 100 µA
LVCMOS Output High Voltage[13, 15] IOHC = 100 µA
0.2
0.4
V
V
V
V
VCC – 0.2
LVTTL Output Low Voltage[13]
LVTTL Output High Voltage[13]
IOLT = 8.0 mA
IOHT = 8.0 mA
VOHT
2.4
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All voltage referenced to VSS (GND).
14. Overshoot: VIH(AC) < VCC + 1.5V for t < tKHKH/2; undershoot: VIL(AC) < – 0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for
t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than
tKHKL (min.).
15. This parameter is sampled.
Document #: 38-05258 Rev. *C
Page 14 of 28
CY7C1360A
CY7C1362A
TAP AC Switching Characteristics Over the Operating Range[16, 17]
Parameter
Clock
Description
Min.
Max.
Unit
tTHTH
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
fTF
50
tTHTL
8
8
tTLTH
ns
Output Times
tTLQX
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
tTLQV
10
tDVTH
5
5
tTHDX
Set-up Times
tMVTH
TMS Set-up
5
5
5
ns
ns
ns
tTDIS
TDI Set-up to TCK Clock Rise
Capture Set-up
tCS
Hold Times
tTHMX
TMS Hold
5
5
5
ns
ns
ns
tTDIH
TDI Hold after Clock Rise
Capture Hold
tCH
Notes:
16.
tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC test conditions.
TAP Timing and Test Conditions
ALL INPUT PULSES
1.5V
TDO
3.0V
Z =
5
0
Ω
50Ω
5
20 pF
0
V
SS
Vt = 1.5V
1.5 ns
1.5 ns
(b)
(a)
t
t
THTL
TLTH
t
THTH
TEST CLOCK
(TCK)
t
t
MVTH
THMX
TEST MODE SELECT
(TMS)
t
t
DVTH
THDX
TEST DATA IN
(TDI)
t
TLQV
t
TLQX
TEST DATA OUT
(TDO)
Document #: 38-05258 Rev. *C
Page 15 of 28
CY7C1360A
CY7C1362A
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
256K × 36
512K × 18
XXXX
Description
Reserved for revision number.
XXXX
00110
00111
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Reserved for future use.
Device Width (22:18)
00100
00011
Reserved (17:12)
XXXXXX
00011100100
1
XXXXXX
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
00011100100 Allows unique identification of DEVICE vendor.
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size (x36)
Bit Size (x18)
3
1
3
1
ID
32
70
32
51
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. Forces all device outputs to High-Z state. This instruction is
not IEEE 1149.1-compliant.
IDCODE
001
010
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. Forces all device outputs to High-Z state.
RESERVED
011
100
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. This instruction does not affect device operations. This
instruction does not implement IEEE 1149.1 PRELOAD function and is
therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does
not affect device operations.
Document #: 38-05258 Rev. *C
Page 16 of 28
CY7C1360A
CY7C1362A
Boundary Scan Order (256K × 36) (continued)
Boundary Scan Order (256K × 36)
Bit#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
A
TQFP
92
93
94
95
96
97
98
99
100
1
Bump ID
6B
5L
Bit#
1
Signal Name
A
TQFP
44
45
46
47
48
49
50
51
52
53
56
57
58
59
62
63
64
68
69
72
73
74
75
78
79
80
81
82
83
84
85
86
87
88
89
Bump ID
2R
3T
BWa
BWb
BWc
BWd
CE2
CE
2
A
5G
3G
3L
3
A
4T
4
A
5T
5
A
6R
3B
5B
6P
7N
6M
7L
2B
4E
3A
2A
2D
1E
2F
6
A
7
A
A
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2
3
6K
7P
6N
6L
6
1G
2H
1D
2E
2G
1H
5R
2K
1L
7
8
9
7K
7T
12
13
14
18
19
22
23
24
25
28
29
30
31
32
33
34
35
36
37
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
6H
7G
6F
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
2M
1N
2P
1K
2L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV
ADSP
ADSC
OE
A
A
A
BWE
GW
CLK
4M
4H
4K
A1
A0
Document #: 38-05258 Rev. *C
Page 17 of 28
CY7C1360A
CY7C1362A
Boundary Scan Order (512K × 18) (continued)
Boundary Scan Order (512K × 18)
Bit#
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal Name
CLK
A
TQFP
89
92
93
94
97
98
99
100
8
Bump ID
4K
Bit#
1
Signal Name
TQFP
44
45
46
47
48
49
50
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
87
88
Bump ID
2R
2T
A
A
6B
2
BWa
BWb
CE2
CE
5L
3
A
3T
3G
2B
4
A
5T
5
A
6R
3B
5B
7P
6N
6L
4E
6
A
A
3A
7
A
A
2A
8
DQa
DQa
DQa
DQa
ZZ
DQb
DQb
DQb
DQb
NC
1D
2E
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
2G
1H
5R
2K
7K
7T
DQa
DQa
DQa
DQa
DQa
A
6H
7G
6F
DQb
DQb
DQb
DQb
DQb
MODE
A
1L
2M
1N
2P
7E
6D
6T
3R
2C
3C
5C
6C
4N
4P
A
6A
5A
4G
4A
4B
4F
A
A
ADV
ADSP
ADSC
OE
BWE
GW
A
A
A1
A0
4M
4H
Document #: 38-05258 Rev. *C
Page 18 of 28
CY7C1360A
CY7C1362A
Short Circuit Output Current........................................ 50 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... >200mA
Operating Range
Voltage on VCC Supply Relative to VSS[19] .... –0.5V to +4.6V
VIN ................................................................... –0.5V to 5.5V
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature ..................................................+150°
Power Dissipation .........................................................1.0W
Ambient
[19,20,21]
Range
Commercial
Industrial
Temperature[18] VCC
VCCQ
0°C to +70°C
–40°C to +85°C
3.3V
2.5V – 5/
−5/+10% 3.3V + 10%
Electrical Characteristics Over the Operating Range
Parameter
VIHD
Description
Input High (Logic 1) Voltage[13, 22]
Test Conditions
All other inputs
Min.
2.0
Max.
Unit
V
VCC + 0.3
VIH
3.3V I/O
2.0
V
2.5V I/O
1.7
V
Input Low (Logic 0) Voltage[13, 22]
Input Leakage Current
VIL
3.3V I/O
–0.3
–0.3
0.8
0.7
5
V
2.5V I/O
V
ILI
0V < VIN < VCC
MODE and ZZ Input Leakage Current[23] 0V < VIN < VCC
µA
µA
µA
V
ILI
-
30
5
ILO
VOH
Output Leakage Current
Output High Voltage[13]
Output(s) disabled, 0V < VOUT < VCC
-
IOH = –5.0 mA for 3.3V I/O
IOH = –1.0 mA for 2.5V I/O
IOL = 8.0 mA for 3.3V I/O
IOL = 1.0 mA for 2.5V I/O
2.4
2.0
V
VOL
VCC
Output Low Voltage[13]
0.4
0.4
V
V
[19]
Supply Voltage[13]
I/O Supply Voltage[13]
3.135
3.135
2.375
3.63
3.63
2.9
V
VCCQ
3.3V I/O
2.5V I/O
V
V
Max.
225 200 166 150
Typ. MHz MHz MHz MHz Unit
Parameter
Description
VCC Operating Supply[24, 25, 26]
Conditions
ICC
Device selected; all inputs < VILor > VIH; 150 650 600 520 460 mA
VCC = Max.;
outputs open, f = f MAX = 1/tcyc
.
ISB1
ISB2
ISB3
ISB4
Automatic CE Power-down
Device deselected;
150 250 230 220 190 mA
Current—TTL Inputs[25, 26]
all inputs < VIL or > VIH; VCC = Max.;
f = f MAX = 1/tcyc
.
Automatic CE Power-down
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or > VCC – 0.2;
all inputs static; CLK frequency = 0
5
30
30
30
30 mA
Current—CMOS Inputs[25, 26]
Automatic CE Power-down
Current—
CMOS Inputs
Max. VDD Device Deselected, or V IN
0.3V or VIN > VDDQ — 0.3V
f = f MAX = 1/t CYC
<
90 260 230 200 180 mA
Automatic CS Power-down
Device deselected; all inputs < VIL
or > VIH; all inputs static;
15
30
30
30
30 mA
Current—TTL Inputs[25, 26]
VCC = Max. CLK frequency = 0
Capacitance[15]
Parameter
Description
Test Conditions
Typ.
5
Max.
Unit
pF
CI
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V
7
8
CI/O
Notes:
Input/Output Capacitance (DQ)
7
pF
18.
TA is the case temperature.
19. The ground level at the start of “power on” on the VCC pins should be no greater than 200mV.
20. Please refer to waveform (d).
21. Power supply ramp up should be monotonic.
22. Overshoot: VIH < + 6.0V for t < tKC /2; undershoot:VIL < –2.0V for t < tKC /2.
23. Output loading is specified with CL=5 pF as in AC Test Loads.
24. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
25. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
Document #: 38-05258 Rev. *C
Page 19 of 28
CY7C1360A
CY7C1362A
Thermal Resistance[15]
Parameter
Description
Test Conditions
TQFP Typ.
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
25
9
4-layer PCB
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
tPU = 200us
ALL INPUT PULSES
90%
OUTPUT
R = 317
Ω
VCCQ
OUTPUT
VCCQ
Vcctyp
Vccmin
90%
10%
Z
= 50Ω
For proper RESET
bring Vcc down to 0V
0
10%
R
= 50Ω
L
GND
≤
1 V/ns
5 pF
≤
1 V/ns
R = 351
Ω
= 1.5V
VTH
(c)
INCLUDING
JIG AND
SCOPE
(a)
(b)
(d)
Switching Characteristics Over the Operating Range[27]
225 MHz
200 MHz
166 MHz
150 MHz
Parameter
Clock
tKC
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock Cycle Time
4.4
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
6.7
2.6
2.6
ns
ns
ns
tKH
Clock HIGH Time
Clock LOW Time
tKL
Output Times
tKQ
Clock to Output Valid
VCCQ = 3.3V
VCCQ = 2.5V
2.8
2.8
3.1
3.1
3.5
4.0
3.5
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to Output Invalid
1.25
0
1.25
0
1.25
0
1.25
0
tKQLZ
tKQHZ
tOEQ
Clock to Output in Low-Z[15, 22, 28]
Clock to Output in High-Z[15, 22, 28]
OE to Output Valid[29]
1.25
3.0
2.8
2.8
1.25
2.6
3.0
3.0
1.0
2.8
3.5
4.0
1.25
4.0
3.5
4.5
VCCQ = 3.3V
VCCQ = 2.5V
tOELZ
tOEHZ
Set-up Times
OE to Output in Low-Z[15, 22, 28]
OE to Output in High-Z[15, 22, 28]
0
0
0
0
2.8
3.0
3.5
3.5
tS
Address, Controls, and Data In[30]
1.4
0.4
1.4
0.4
1.5
0.5
2.0
0.5
ns
ns
Hold Times
tH
Address, Controls, and Data In[30]
Notes:
26. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
28. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
29. OE is a “Don’t Care” when a byte Write enable is sampled LOW.
30. This is a synchronous device. All synchronous inputs must meet specified set up and hold time, except for “Don’t Care” as defined in the truth table.
.
Document #: 38-05258 Rev. *C
Page 20 of 28
CY7C1360A
CY7C1362A
Switching Waveforms
Read Timing[31, 32]
tKC
t
KL
CLK
tS
tKH
ADSP
tH
ADSC
tS
A
A1
A2
tH
BWx
GW
BWE
tS
CE
tS
ADV
tH
OE
tOEQ
tKQ
tKQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
DQx
SINGLE READ
BURST READ
Notes:
31. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
32. For the X18 product, there are only BWa and BWb for byte Write control.
Document #: 38-05258 Rev. *C
Page 21 of 28
CY7C1360A
CY7C1362A
Switching Waveforms (continued)
Write Timing[31, 32]
CLK
tS
ADSP
tH
ADSC
tS
A
A1
A2
A3
tH
BW
x
BWE
GW
CE
tS
ADV
tH
OE
tOEHZ
tKQX
Q
D(A1)
D(A2) D(A2+1) D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
DQ
x
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05258 Rev. *C
Page 22 of 28
CY7C1360A
CY7C1362A
Switching Waveforms (continued)
Read/Write Timing[31, 32]
CLK
tS
ADSP
tH
ADSC
tS
A
A2
A3
A4
A5
A1
tH
BW
x
BWE
GW
CE
ADV
OE
DQx
Q(A1)
Single Reads
D(A3)
Q(A4)
Q(A4+1) Q(A4+2)
D(A5)
D(A5+1)
Q(A2)
Single Write
Burst Read
Burst Write
Document #: 38-05258 Rev. *C
Page 23 of 28
CY7C1360A
CY7C1362A
Switching Waveforms (continued)
ZZ Mode Timing[33, 34]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Notes:
33. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
34. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05258 Rev. *C
Page 24 of 28
CY7C1360A
CY7C1362A
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
225
CY7C1360A-225AJC
CY7C1360A-225AC
CY7C1360A-225BGC
CY7C1360A-200AJC
CY7C1360A-200AC
CY7C1360A-200BGC
CY7C1360A-166AJC
CY7C1360A-166AC
CY7C1360A-166BGC
CY7C1360A-150AJC
CY7C1360A-150AC
CY7C1360A-150BGC
CY7C1362A-225AJC
CY7C1362A-225AC
CY7C1362A-225BGC
CY7C1362A-200AJC
CY7C1362A-200AC
CY7C1362A-200BGC
CY7C1362A-166AJC
CY7C1362A-166AC
CY7C1362A-166BGC
CY7C1362A-150AJC
CY7C1362A-150AC
CY7C1362A-150BGC
CY7C1360A-200AJI
CY7C1360A-200AI
CY7C1360A-200BGI
CY7C1360A-166AJI
CY7C1360A-166AI
CY7C1360A-166BGI
CY7C1360A-150AJI
CY7C1360A-150AI
CY7C1360A-150BGI
CY7C1362A-200AJI
CY7C1362A-200AI
CY7C1362A-200BGI
CY7C1362A-166AJI
CY7C1362A-166AI
CY7C1362A-166BGI
CY7C1362A-150AJI
CY7C1362A-150AI
CY7C1362A-150BGI
A101
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
Commercial
BG119
A101
200
166
150
225
200
166
150
200
166
150
200
166
150
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
Commercial
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
Industrial
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
Industrial
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead BGA (14 x 22 x 2.4 mm)
A101
BG119
Document #: 38-05258 Rev. *C
Page 25 of 28
CY7C1360A
CY7C1362A
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05258 Rev. *C
Page 26 of 28
CY7C1360A
CY7C1362A
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4) BG119
51-85115-*A
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-05258 Rev. *C
Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1360A
CY7C1362A
Document Title:CY7C1360A CY7C1362A 256K x 36/512K x 18 Synchronous Pipelined Burst SRAM
Document Number: 38-05258
Issue
Date
Orig. of
Change
REV
**
ECN No.
113846
116062
Description of Change
05/22/02
05/28/02
GLC
BRI
Change from Spec.: 38-00990 to 38-05258
*A
Removed GVT part numbers from title and body of data sheet
Added note 19 (pg. 19) regarding VCC on “Power On”
*B
*C
116765
123144
09/09/02
01/18/03
BRI
RBI
Updated package type names on page 3
ICC, ISB3, and ISB4 values corrected on page 19
Updated power-up requirements in Operating Range and in AC Test Loads
and Waveforms.
Document #: 38-05258 Rev. *C
Page 28 of 28
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