CY7C4245V-25ASC [ROCHESTER]
FIFO, 4KX18, 15ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64;
| 型号： | CY7C4245V-25ASC |
| 厂家： | 
Rochester Electronics |
| 描述： | FIFO, 4KX18, 15ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64 先进先出芯片 |
| 文件： | 总24页 (文件大小：1352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4425V /4215V CY7C4225V /4235V/4245V512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225V/4215V
CY7C4235V/4245V
512/1K/2K/4K x18 Low-Voltage
Synchronous FIFOs
Features
Functional Description
■ 3.3Voperationforlowpowerconsumptionandeasyintegration
into low-voltage systems
The CY7C42X5V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are
18 bits wide. The CY7C42X5V can be cascaded to increase
FIFO depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
■ High-speed, low-power, first-in first-out (FIFO)
memories
❐ 512 x 18 (CY7C4215V)
❐ 1K x 18 (CY7C4225V)
❐ 2K x 18 (CY7C4235V)
❐ 4K x 18 (CY7C4245V)
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and a Write
Enable pin (WEN).
■ 0.65µ CMOS
■ High-speed 67-MHz operation (15-ns read/write cycle times)
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is
continually written into the FIFO on each cycle. The output port
is controlled in a similar manner by a Free-Running Read Clock
(RCLK) and a Read Enable pin (REN). In addition, the
CY7C42X5V have an Output Enable pin (OE). The read and
write clocks may be tied together for single-clock operation or the
two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 66 MHz are
achievable.
■ Low power
❐ ICC = 30 mA
■ 5V tolerant inputs (VIH MAX = 5V)
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, Half Full, and programmable Almost Empty and
Almost Full status flags
■ TTL-compatible
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
■ Retransmit function
■ Output Enable (OE) pin
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI pins
of the next device, and the WXO and RXO pins of the last device
should be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
■ Independent read and write enable pins
■ Supports free-running 50% duty cycle clock inputs
■ Width-Expansion Capability
the remaining devices should be tied to VCC
.
■ Depth-Expansion Capability
The CY7C42X5V provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this pin
provides the expansion out (WXO) information that is used to
signal the next FIFO when it will be activated.
■ 64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP
■ Pb-Free packages available
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one clock
cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
V
CC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65μ P-Well CMOS technology. Input ESD
protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Cypress Semiconductor Corporation
Document #: 38-06029 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 19, 2010
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Logic Block Diagram
Document #: 38-06029 Rev. *D
Page 2 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Contents
Features............................................................................. 1
Functional Description..................................................... 1
Logic Block Diagram........................................................ 2
Contents............................................................................ 3
Pin Configuration ............................................................. 4
Selection Guide ................................................................ 4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 6
Resetting the FIFO............................................................ 6
FIFO Operation ................................................................. 6
Programming .................................................................... 6
Flag Operation .................................................................. 7
Full Flag....................................................................... 7
Empty Flag .................................................................. 7
Programmable Almost Empty/Almost Full Flag........... 7
Retransmit......................................................................... 7
Width Expansion Configuration...................................... 8
Depth Expansion Configuration
Operating Range............................................................. 10
Electrical Characteristics
Over the Operating Range ............................................... 10
Capacitance ...................................................................................... 10
Switching Characteristics
Over the Operating Range ............................................... 11
Switching Waveforms .................................................... 12
Ordering Information...................................................... 20
512 x 18 Low-Voltage Synchronous FIFO ................ 20
1K x 18 Low-Voltage Synchronous FIFO.................. 20
2K x 18 Low-Voltage Synchronous FIFO.................. 20
4K x 18 Low-Voltage Synchronous FIFO.................. 20
Package Diagrams.......................................................... 21
Document History Page................................................. 23
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support....................... 23
Products.................................................................... 23
PSoC Solutions......................................................... 23
(with Programmable Flags) ............................................. 8
Maximum Ratings........................................................... 10
Document #: 38-06029 Rev. *D
Page 3 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Pin Configuration
Figure 1. 64-Pin STQFP/TQFP
Top View
Q
Q
48
47
D
15
D
14
D
13
D
12
1
2
14
13
GND
46
45
3
4
Q
12
Q
V
44
43
42
41
11
D
D
5
6
7
8
11
10
CC
Q
10
D
9
Q
9
D
D
CY7C4215V
CY7C4225V
CY7C4235V
CY7C4245V
8
7
6
GND
40
39
9
10
Q
8
D
D
D
D
D
D
38
37
36
11
12
13
Q
7
5
Q
6
4
Q
5
3
35
34
14
15
GND
2
Q
4
1
D
0
33
V
CC
16
Selection Guide
Description
CY7C42X5V-15
CY7C42X5V-25
CY7C42X5V-35
Unit
MHz
ns
Maximum Frequency
66.7
11
15
4
40
15
25
6
28.6
20
35
7
Maximum Access Time
Minimum Cycle Time
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
1
1
2
ns
11
30
15
30
20
30
ns
Operating Current
Commercial
mA
CY7C4215V
CY7C4225V
CY7C4235V
CY7C4245V
Density
512 x 18
1K x 18
2K x 18
4K x 18
Packages
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14
TQFP
64-pin 10x10
STQFP
64-pin 14x14 TQFP 64-pin 14x14 TQFP
64-pin 10x10
STQFP
64-pin 10x10
STQFP
Document #: 38-06029 Rev. *D
Page 4 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Pin Definitions
Signal Name
D0−17
Description
I/O
Function
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I
O
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
Q0−17
WEN
REN
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is
not Empty. When LD is asserted, RCLK reads data out of the programmable
flag-offset register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded –
Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty
offset value programmed into the FIFO. PAE is asynchronous when
V
CC/SMODE is tied to VCC; it is synchronized to RCLK when VCC/SMODE is tied
to VSS
.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset
value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is
tied to VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS
.
LD
Load
I
I
When LD is LOW, D0−17 (O0−17) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT
First Load/
Retransmit
Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to
VSS; all other devices will have FL tied to VCC. In standard mode of width
expansion, FL is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit
function is also available in standalone mode by strobing RT.
WXI
RXI
RXO
RS
Write Expansion
Input
I
I
Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS
Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS
Cascaded – Connected to RXI of next device.
.
Read Expansion
Input
.
Read Expansion
Output
O
I
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance)
state.
V
CC/SMODE Synchronous
I
Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to VCC.
Synchronous Almost Empty/Almost Full flags – tied to VSS. (Almost Empty
synchronized to RCLK, Almost Full synchronized to WCLK.)
Almost Empty/
Almost Full Flags
Document #: 38-06029 Rev. *D
Page 5 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Architecture
Programming
The CY7C42X5V consists of an array of 64 to 4K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5V
also includes the control signals WXI, RXI, WXO, RXO for depth
expansion.
The CY7C42X5V devices contain two 12-bit offset registers.
Data present on D0–11 during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full)
flags become active. If the user elects not to program the FIFO’s
flags, the default offset values are used (see Table 2). When the
Load LD pin is set LOW and WEN is set LOW, data on the inputs
D0–11 is written into the Empty offset register on the first
LOW-to-HIGH transition of the write clock (WCLK). When the LD
pin and WEN are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the Write
Clock (WCLK). The third transition of the Write Clock (WCLK)
again writes to the Empty offset register (see Table 1). Writing all
offset registers does not have to occur at one time. One or two
offset registers can be written and then, by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When
the LD pin is set LOW, and WEN is LOW, the next offset register
in sequence is written.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. In order for the FIFO to reset to its
default state, a falling edge must occur on RS and the user must
not read or write while RS is LOW.
FIFO Operation
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When the WEN signal is active (LOW), data present on the D0-17
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory will be presented on the Q0−17 outputs. New data
will be presented on each rising edge of RCLK while REN is
active LOW and OE is LOW. REN must set up tENS before RCLK
for it to be a valid read function. WEN must occur tENS before
WCLK for it to be a valid write function.
Table 1. Write Offset Register
WCLK[1]
LD WEN
Selection
0
0
Writing to offset registers:
Empty Offset
An Output Enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q0−17 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
Full Offset
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0−17 outputs even
after additional reads occur.
Note
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06029 Rev. *D
Page 6 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
that the FIFO is either Almost Full or Almost Empty. See Table 2
for a description of programmable flags.
Flag Operation
The CY7C42X5V devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are synchronous.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
PAE and PAF are synchronous if VCC/SMODE is tied to VSS
.
Full Flag
Retransmit
The Full Flag (FF) will go LOW when device is Full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK, i.e., it is exclusively
updated by each rising edge of WCLK.
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last RS cycle. A HIGH pulse on
RT resets the internal read pointer to the first physical location of
the FIFO. WCLK and RCLK may be free running but must be
disabled during and tRTR after the retransmit pulse. With every
valid read cycle after retransmit, previously accessed data is
read and the read pointer is incremented until it is equal to the
write pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
cycle. Data written to the FIFO after activation of RT are trans-
mitted also.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN. EF is synchronized to RCLK, i.e., it is exclu-
sively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C42X5V features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described in
the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying
The full depth of the FIFO can be repeatedly retransmitted.
Table 2. Flag Truth Table
Number of Words in
FIFO
FF
PAF
HF
PAE
EF
7C4215V - 512 x 18
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
1 to n[2]
H
H
H
H
H
(n + 1) to 256
257 to (512 − (m + 1))
(512 − m)[3] to 511
512
H
H
H
H
L
L
L
Number of Words in FIFO
7C4235V - 2K x 18
0
FF
PAF
HF
PAE
EF
7C4225V - 1K x 18
0
1 to n[2]
7C4245V - 4K x 18
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n[2]
1 to n[2]
(n + 1) to 512
513 to (1024 − (m + 1))
(1024 − m)[3] to 1023
1024
(n + 1) to 1024
(n + 1) to 2048
H
H
H
H
1025 to (2048 − (m + 1)) 2049 to (4096 − (m + 1))
(2048 − m)[3] to 2047
(4096 − m)[3] to 4095
L
2048
4096
L
L
Notes
2. n = Empty Offset (Default Values: CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
3. m = Full Offset (Default Values: CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
Document #: 38-06029 Rev. *D
Page 7 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Width Expansion Configuration
The CY7C42X5V can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode
all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags
of every FIFO. This technique will avoid ready data from the FIFO that is “staggered” by one clock cycle due to the variations in skew
between RCLK and WCLK. Figure demonstrates a 36-word width by using two CY7C42X5V.
Figure 2. Block Diagram of Low-Voltage Synchronous FIFO Memories Used in a Width Expansion Configuration
RESET(RS)
RESET(RS)
DATAIN (D)
36
18
18
READCLOCK(RCLK)
READENABLE(REN)
OUTPUT ENABLE(OE)
PROGRAMMABLE(PAF)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
7C4215V
7C4225V
7C4235V
7C4245V
7C4215V
7C4225V
7C4235V
7C4245V
EMPTYFLAG (EF)
EF
FF
FF
EF
DATAOUT (Q)
18
36
FULL FLAG (FF)
18
FIRSTLOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
Depth Expansion Configuration (with Programmable Flags)
The CY7C42X5V can easily be adapted to applications requiring more than 64/256/512/1024/2048/4096 words of buffering. Figure
shows Depth Expansion using three CY7C42X5Vs. Maximum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite
PAE and PAF flags are not precise.
Document #: 38-06029 Rev. *D
Page 8 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Figure 3. Block Diagram of Low-Voltage Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
WXO RXO
7C4215V
7C4225V
7C4235V
7C4245V
VCC
FIRSTLOAD(FL)
FF
PAF
EF
PAE
WXI RXI
WXO RXO
DATAIN (D)
DATAOUT(Q)
7C4215V
7C4225V
7C4235V
7C4245V
VCC
FIRSTLOAD(FL)
FF
PAF
EF
PAE
WXI RXI
WRITECLOCK(WCLK)
WRITE ENABLE(WEN)
READCLOCK(RCLK)
READ ENABLE (REN)
WXO RXO
RESET(RS)
OUTPUT ENABLE(OE)
7C4215V
7C4225V
7C4235V
7C4245V
LOAD (LD)
FF
EF
FF
EF
PAE
PAE
PAF
PAF
WXI RXI
42X5V–23
FIRSTLOAD(FL)
Document #: 38-06029 Rev. *D
Page 9 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Maximum Ratings[4]
DC Input Voltage .................................................... −0.5V to +5V
Output Current into Outputs (LOW)............................. 20 mA
(Abovewhichtheusefullifemay beimpaired. Foruserguidelines,
not tested.)
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................... −65°C to +150°C
Ambient Temperature with
Latch-up Current......................................................>200 mA
Power Applied................................................ −55°C to +125°C
Operating Range
Supply Voltage to Ground Potential .................−0.5V to +5.0V
Range
Ambient Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State ............................................. −0.5V to VCC+0.5V
Commercial
0°C to +70°C
3.3V ± 300 mV
Electrical Characteristics Over the Operating Range
7C42X5V-15
7C42X5V-25
7C42X5V-35
Parameter
VOH
Description
Test Conditions
Unit
Max
Min
Max
Min
Max
Min
Output HIGH Voltage
VCC = Min.,
2.4
2.4
2.4
V
I
OH = −2.0 mA
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
VCC = Min.,
IOL = 8.0 mA
0.4
5.0
0.8
0.4
5.0
0.8
0.4
5.0
0.8
V
V
V
Low = 2.0V
High = VCC +0.5V
2.0
2.0
2.0
[5]
VIL
Low = −3.0V
High = 0.8 V
−0.5
−0.5
−0.5
IIX
IOZL
VCC = Max.
OE > VIH,
−10
−10
10
−10
−10
10
−10
−10
10
μA
μA
Output OFF,
High Z Current
+10
+10
+10
IOZH
VSS < VO < VCC
[6]
ICC
Operating Current
VCC = Max.,
IOUT = 0 mA
Com’l
Com’l
30
6
30
6
30
6
mA
mA
[7]
ISB
Standby Current
VCC = Max.,
I
OUT = 0 mA
Capacitance[8]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
Unit
CIN
TA = 25°C, f = 1 MHz,
CC = 5.0V
5
7
pF
pF
V
COUT
Notes
4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up
5. The V and V specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous
IH
IL
device or V
.
SS
6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs
are unloaded.
7. All inputs = V − 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
CC
8. Tested initially and after any design or process changes that may affect these parameters
Document #: 38-06029 Rev. *D
Page 10 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Figure 4. AC Test Loads and Waveforms[9, 10]
R1 = 330Ω
3.3V
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2 = 510Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth = 200Ω
OUTPUT
Vth = 2.0V
Switching Characteristics Over the Operating Range
7C42X5V-15 7C42X5V-25 7C42X5V-35
Parameter
Description
Unit
Min
Max
66.7
11
Min
Max
40
Min
Max
28.6 MHz
20
tS
Clock Cycle Frequency
tA
Data Access Time
2
15
6
2
25
10
10
6
15
2
35
14
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time.
6
Data Set-up Time
4
tDH
Data Hold Time
1
2
2
tENS
tENH
tRS
Enable Set-up Time
4
6
7
Enable Hold Time
1
2
2
Reset Pulse Width[11]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
Output Enable to Output Valid
Output Enable to Output in High Z[12]
Write Clock to Full Flag
Read Clock to Empty Flag
15
10
25
15
35
20
tRSR
tRSF
tPRT
tRTR
tOLZ
tOE
18
25
35
15
15
0
25
25
0
35
35
0
3
8
8
3
12
12
15
15
22
3
15
15
20
20
25
tOHZ
tWFF
tREF
tPAFasynch
3
3
3
11
11
18
Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC
)
tPAFsynch
tPAEasynch
tPAEsynch
tHF
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
Clock to Programmable Almost-Empty Flag[13]
11
18
11
16
15
22
15
20
20
25
20
25
ns
ns
ns
ns
)
(Asynchronous mode, VCC/SMODE tied to VCC
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
)
Clock to Half-Full Flag
Notes
9.
C
= 30 pF for all AC parameters except for t
.
OHZ
L
10. C = 5 pF for t
.
L
OHZ
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. t
, t
, after program register write will not be valid until 5 ns + t
.
PAF(E)
PAFasynch PAEasynch
Document #: 38-06029 Rev. *D
Page 11 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Characteristics Over the Operating Range (continued)
7C42X5V-15 7C42X5V-25 7C42X5V-35
Parameter
Description
Unit
Min
Max
Min
Max
Min
Max
tXO
Clock to Expansion Out
10
15
20
ns
ns
ns
ns
tXI
Expansion in Pulse Width
Expansion in Set-up Time
6.5
5
10
10
10
14
15
12
tXIS
tSKEW1
Skew Time between Read Clock and Write Clock for
Full Flag
6
tSKEW2
tSKEW3
Skew Time between Read Clock and Write Clock for
Empty Flag
6
10
18
12
20
ns
ns
Skew Time between Read Clock and Write Clock for
Programmable Almost Empty and Programmable
Almost Full Flags.
15
Switching Waveforms
Figure 5. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D0–D17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[14]
t
SKEW1
RCLK
REN
Note
14. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
SKEW1
the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK edge.
SKEW1
Document #: 38-06029 Rev. *D
Page 12 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 6. Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
REN
t
t
ENH
ENS
NO OPERATION
t
REF
t
REF
EF
t
A
VALID DATA
Q0–Q17
t
OLZ
t
OHZ
t
OE
OE
[15]
t
SKEW2
WCLK
WEN
RS
Figure 7. Reset Timing[16]
t
RS
t
RSR
REN,WEN,
LD
t
RSF
EF,PAE
t
RSF
FF,PAF,
HF
t
RSF
[17]
OE = 1
Q0–Q17
OE = 0
Notes
15. t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
SKEW2
the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK edge.
SKEW2
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Document #: 38-06029 Rev. *D
Page 13 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
D0–D17
WEN
t
DS
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
t
ENS
[18]
FRL
t
t
SKEW2
RCLK
t
REF
EF
REN
[19]
t
A
t
A
Q0–Q17
D
0
D
1
t
OLZ
t
OE
OE
Figure 9. Empty Flag Timing
WCLK
D0–D17
WEN
t
t
DS
DS
D0
D1
t
t
ENH
ENH
t
t
ENS
ENS
[18]
t
FRL
[18]
FRL
t
RCLK
t
t
t
REF
t
REF
t
REF
SKEW2
SKEW2
EF
REN
OE
t
A
Q0–Q17
D0
Notes
18. When t
> minimum specification, t
(maximum) = t
+ t
. When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
+
SKEW2
FRL
CLK
SKEW2
SKEW2
FRL
CLK
SKEW2
CLK
t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW2
19. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06029 Rev. *D
Page 14 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 10. Full Flag Timing
NO WRITE
NO WRITE
WCLK
[14]
[14]
t
t
DATA WRITE
t
SKEW1
DS
SKEW1
DATA WRITE
D0–D17
t
t
t
WFF
WFF
WFF
FF
WEN
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN
LOW
OE
t
A
t
A
DATAREAD
NEXT DATA READ
Q0–q17
DATA IN OUTPUT REGISTER
Figure 11. Half-Full Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
HF
HALF FULL+1
OR MORE
HALF FULL OR LESS
HALF FULL OR LESS
HF
t
HF
RCLK
REN
t
ENS
Document #: 38-06029 Rev. *D
Page 15 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 12. Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
PAE
[20]
n+1 WORDS
IN FIFO
PAE
n WORDS IN FIFO
t
PAE
RCLK
t
ENS
REN
Figure 13. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
t
t
CLKL
CLKH
WCLK
t
t
ENH
ENS
WEN
PAE
Note 21
N + 1 WORDS
INFIFO
Note 23
t
PAEsynch
t
[22]
t
SKEW3
PAEsynch
RCLK
REN
t
ENS
t
t
ENH
ENS
Notes
20. PAE offset − n. Number of data words into FIFO already = n.
21. PAE offset − n.
22. t
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
SKEW3
and the rising RCLK is less than t
, then PAE may not change state until the next RCLK.
SKEW3
23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
Document #: 38-06029 Rev. *D
Page 16 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 14. Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
Note 24
WCLK
WEN
t
t
ENH
ENS
t
PAF
FULL − M WORDS
[26]
[25]
IN FIFO
FULL − (M + 1) WORDS
PAF
[27]
IN FIFO
t
PAF
RCLK
REN
t
ENS
Figure 15. Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))
t
t
Note 28
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
Note 29
t
PAF
FULL − M WORDS
PAF
[26]
IN FIFO
FULL – (M + 1) WORDS
IN FIFO
t
PAFsynch
[30]
t
SKEW3
RCLK
REN
t
ENS
t
t
ENH
ENS
Notes
24. PAF offset = m. Number of data words written into FIFO already = 256 − m + 1 for the CY7C4205V, 512 − m + 1 for the CY7C4215V. 1024 − m + 1 for the CY7C4225V,
2048 − m + 1 for the CY7C4235V, and 4096 − m + 1 for the CY7C4245V.
25. PAF is offset = m.
26. 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V, and 4096 – m words in CY7C4245V.
27. 256 − m + 1 words in CY7C4205V, 512 − m +1 words in CY7C4215V, 1024 − m + 1 CY7C4225V, 2048 − m + 1 in CY74235V, and 4096 − m + 1 words in CY7C4245V.
28. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
29. PAF offset = m.
30. t
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK
SKEW3
and the rising edge of WCLK is less than t
, then PAF may not change state until the next WCLK rising edge.
SKEW3
Document #: 38-06029 Rev. *D
Page 17 of 23
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CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 16. Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
t
DH
DS
PAE OFFSET
D0–D17
D0–D11
PAE OFFSET
PAF OFFSET
Figure 17. Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
REN
t
A
Q0–Q17
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Figure 18. Write Expansion Out Timing
t
CLKH
WCLK
Note 31
t
XO
WXO
WEN
t
XO
t
ENS
Note
31. Write to Last Physical Location.
Document #: 38-06029 Rev. *D
Page 18 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Switching Waveforms (continued)
Figure 19. Read Expansion Out Timing
t
CLKH
RCLK
Note 32
t
XO
RXO
REN
t
XO
t
ENS
Figure 20. Write Expansion In Timing
t
XI
WXI
t
XIS
WCLK
Figure 21. Read Expansion In Timing
t
XI
RXI
t
XIS
RCLK
Figure 22. Retransmit Timing[33, 34, 35]
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
and/all
async flags
HF/PAE/PAF
Notes
32. Read from Last Physical Location.
33. Clocks are free running in this case.
34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
.
RTR
35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
to update these flags.
RTR
Document #: 38-06029 Rev. *D
Page 19 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Ordering Information
Speed
(ns)
Package
Name
Package
Type
Operating
Range
Ordering Code
512 x 18 Low-Voltage Synchronous FIFO
15 CY7C4215V-15ASXC
1K x 18 Low-Voltage Synchronous FIFO
15 CY7C4225V-15ASXC
2K x 18 Low-Voltage Synchronous FIFO
A64
A64
64-Pin Pb-Free 10x10 Thin Quad Flatpack
64-Pin Pb-Free 10x10 Thin Quad Flatpack
Commercial
Commercial
Commercial
15
CY7C4235V-15ASC
CY7C4235V-15ASXC
A64
A64
64-Pin 10x10 Thin Quad Flatpack
64-Pin Pb-Free 10x10 Thin Quad Flatpack
4K x 18 Low-Voltage Synchronous FIFO
15
25
CY7C4245V-15ASXC
CY7C4245V-25ASC
A64
A64
64-Pin Pb-Free 10x10 Thin Quad Flatpack
64-Pin 10x10 Thin Quad Flatpack
Commercial
Document #: 38-06029 Rev. *D
Page 20 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Package Diagrams
Figure 23. 64-Pin TQFP (10X10X1.4 mm)
51-85051 *B
Document #: 38-06029 Rev. *D
Page 21 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Figure 24. 64-Pin TQFP (14X14X1.4 mm)
51-85046 *D
Document #: 38-06029 Rev. *D
Page 22 of 23
[+] Feedback
CY7C4225V/4215V
CY7C4235V/4245V
Document History Page
Document Title: CY7C4225V/4215V/CY7C4235V/4245V 64/256/512/1K/2K/4K x 18 Low-Voltage Synchronous FIFOs
Document Number: 38-06029
Submission Orig. of
REV.
ECN NO.
Description of Change
Date
Change
**
109961
122281
127856
12/17/01
12/26/02
08/22/03
SZV
Change from Spec number: 38-00609 to 38-06029
*A
*B
RBI
Power up requirements added to Maximum Ratings Information
FSG
Fixed read cycle timing diagram
Corrected switching waveform diagram typos
Page 12: WEN changed to REN (typo)
Page 13: WCLK changed to RCLK (typo)
*C
*D
393636
See ECN
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C4205V-15ASXC, CY7C4215V-15ASXC, CY7C4225V-15ASXC,
CY7C4235V-15ASXC, CY7C4245V-15ASXC, CY7C4245V-25ASXC
2896039
03/19/2010
RAME
Added Contents
Updated package diagrams
Removed inactive parts from Ordering information table
Updated links in Sales, Solutions and Legal Information
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06029 Rev. *D
Revised March 19, 2010
Page 23 of 23
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相关型号：
CY7C4245V-25ASCT
FIFO, 4KX18, 15ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64
CYPRESS
CY7C4245V-25ASXCT
FIFO, 4KX18, 15ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, STQFP-64
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