CY7C4251V-15AXC [ROCHESTER]
8KX9 OTHER FIFO, 11ns, PQFP32, 7 X 7 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-32;
| 型号： | CY7C4251V-15AXC |
| 厂家： | 
Rochester Electronics |
| 描述： | 8KX9 OTHER FIFO, 11ns, PQFP32, 7 X 7 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-32 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总20页 (文件大小：1279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C4201V/4211V/4221VCY7C4241V/4251VLow Voltage 256/512/1K/4K/8K
x 9 Synchronous FIFOs
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Low Voltage 256/512/1K/4K/8K x 9 Syn-
chronous FIFOs
■ 32-pin PLCC
Features
■ Available in Pb-Free Packages
■ High-speed, low-power, first-in, first-out (FIFO) memories
❐ 256 x 9 (CY7C4201V)
❐ 512 x 9 (CY7C4211V)
Functional Description
❐ 1K x 9 (CY7C4221V)
❐ 4K x 9 (CY7C4241V)
❐ 8K x 9 (CY7C4251V)
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
■ High-speed 66-MHz operation (15-ns read/write cycle time)
■ Low power (ICC = 20 mA)
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a Free-Running Clock (WCLK) and two Write Enable pins
(WEN1, WEN2/LD).
■ 3.3Voperationforlowpowerconsumptionandeasyintegration
into low-voltage systems
■ 5V-tolerant inputs VIH max = 5V
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a Free-Running Read Clock (RCLK) and two Read
Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an
Output Enable Pin (OE). The Read (RCLK) and Write (WCLK)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 66 MHz are achievable.
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, and Programmable Almost Empty and
Almost Full status flags
■ TTL compatible
■ Output Enable (OE) pin
■ Independent read and write enable pins
■ Center power and ground pins for reduced noise
■ Width expansion capability
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic to
direct the flow of data.
■ Space saving 32-pin 7 mm × 7 mm TQFP
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 19, 2010
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Contents
Features............................................................................. 1
Functional Description..................................................... 1
Logic Block Diagram........................................................ 1
Contents............................................................................ 2
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 3
Pin Definitions .................................................................. 3
Functional Description......................................................4
Architecture ...................................................................... 4
Resetting the FIFO............................................................ 4
FIFO Operation ................................................................. 4
Programming .................................................................... 5
Programmable Flag (PAE, PAF) Operation ................ 6
Width Expansion Configuration...................................... 7
Flag Operation .................................................................. 7
Full Flag....................................................................... 7
Empty Flag .................................................................. 7
Maximum Ratings............................................................. 8
Operating Range............................................................... 8
Electrical Characteristics Over the Operating Range ..... 8
Capacitance ...................................................................... 8
Switching Characteristics Over the Operating Range .... 9
Switching Waveforms .................................................... 10
Ordering Information...................................................... 16
256 x 9 Low Voltage Synchronous FIFO................... 16
512 x 9 Low Voltage Synchronous FIFO................... 16
1K x 9 Low Voltage Synchronous FIFO .................... 16
4K x 9 Low Voltage Synchronous FIFO .................... 16
8K x 9 Low Voltage Synchronous FIFO .................... 16
Package Diagrams.......................................................... 17
Document History Page................................................. 19
Worldwide Sales and Design Support....................... 19
Products.................................................................... 19
PSoC Solutions......................................................... 19
Document #: 38-06010 Rev. *C
Page 2 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Pin Configuration
Figure 1. 32-Pin PLCC
Figure 2. 32-Pin TQFP
Top View
4
3
2
1 323130
29
28
D
RS
WEN1
1
5
6
7
8
D
0
PAF
PAE
27 WCLK
26
WEN2/LD
GND
REN1
RCLK
REN2
OE
V
9
CC
25
24
23
22
21
Q
Q
Q
Q
10
11
12
13
8
7
6
5
14151617181920
Selection Guide
Description
CY7C42X1V-15
CY7C42X1V-25
CY7C42X1V-35
Unit
MHz
ns
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
66.7
11
15
4
40
15
25
6
28.6
20
35
7
ns
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
ns
1
1
2
ns
10
20
15
20
20
20
ns
Active Power Supply Current
Commercial
mA
CY7C4421V
CY7C4201V
256 x 9
CY7C4211V
512 x 9
CY7C4221V
CY7C4231V
CY7C4241V
CY7C4251V
Density
64 x 9
1K x 9
2K x 9
4K x 9
8K x 9
Pin Definitions
Signal Name
D0−8
Description
I/O
Description
Data Inputs
I
O
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
Q0−8
Data Outputs
Write Enable 1
WEN1
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
REN1, REN2 Read Enable
Inputs
I
I
Enables the device for Read operation.
WCLK
Write Clock
The rising edge clocks data into the FIFO when WEN1is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
Document #: 38-06010 Rev. *C
Page 3 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Pin Definitions (continued)
Signal Name
Description
I/O
Description
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
PAF
RS
Programmable
Almost Full
O
I
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Functional Description
FIFO Operation
The CY7C42X1V provides four status pins: Empty, Full, Almost Empty,
Almost Full. The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to Empty-7 and
Full-7.
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D0-8 pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will be
presented on the Q0-8 outputs. New data will be presented on
each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up tENS before RCLK for it to be a valid
read function. WEN1 and WEN2 must occur tENS before WCLK
for it to be a valid write function.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle
An Output Enable (OE) pin is provided to three-state the Q0-8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q0-8 outputs after tOE
.
All configurations are fabricated using an advanced 0.65μ P-Well
CMOS technology. Input ESD protection is greater than 2001V, and
latch-up is prevented by the use of guard rings.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0-8 outputs even
after additional reads occur.
Architecture
The CY7C42X1V consists of an array of 64 to 8K words of nine
bits each (implemented by a dual-port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF.)
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored is the RAM array sequentially and independently
of any on-going read operation.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q0-8) go LOW tRSF after the
rising edge of RS. In order for the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW. All flags are guaranteed to be valid tRSF
after RS is taken LOW.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows for depth expansion. If
Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset
(RS=LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK.)
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Document #: 38-06010 Rev. *C
Page 4 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again. Figure 3 shows the register sizes and default
values for the various device types.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1V for writing or reading data to these
registers.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW, a
write operation stores data in the next offset register in
sequence.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset
Least Significant Bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
Most Significant Bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register contents
to the data outputs. Writes and reads should not be performed
simultaneously on the offset registers.
Figure 3. Offset Register Location and Default Values
64 x 9
6
256 x 9
7
512 x 9
7
1K x 9
7
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
0
0
0
1
(MSB)
(MSB)
00
0
0
6
7
7
7
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
0
1
(MSB)
0
(MSB)
00
2K x 9
4K x 9
8K x 9
0
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value= 007h
Empty Offset (LSB) Reg.
Default Value = 007h
0
0
0
2
3
4
(MSB)
0000
(MSB)
00000
(MSB)
000
7
7
7
Full Offset (LSB) Reg
Default Value = 007h
Full Offset (LSB) Reg
Default Value= 007h
Full Offset (LSB) Reg
Default Value = 007h
2
3
4
(MSB)
000
(MSB)
0000
(MSB)
00000
Document #: 38-06010 Rev. *C
Page 5 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
LOW when the FIFO contains n or fewer unread words. PAE is
set HIGH by the LOW-to-HIGH transition of RCLK when the
FIFO contains (n+1) or greater unread words.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in Table 1 or the default values are used, the programmable
Almost Empty Flag (PAE) and programmable Almost Full Flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
The number formed by the full offset least significant bit register
and full offset most significant bit register is referred to as m and
determines the operation of PAF. PAE is synchronized to the
LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW
when the number of unread words in the FIFO is greater than or
equal to CY7C4421V (64 – m), CY7C4201V (256 – m),
CY7C4211V (512 – m), CY7C4221V (1K – m), CY7C4231V (2K
– m), CY7C4241V (4K – m), and CY7C4251V (8K – m). PAF is
set HIGH by the LOW-to-HIGH transition of WCLK when the
number of available memory locations is greater than m.
Table 1. Writing the Offset Registers
LD WEN
WCLK[1]
Selection
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred to
as n and determines the operation of PAE. PAE is synchronized
to the LOW-to-HIGH transition of RCLK by one flip-flop and is
Table 2. Status Flags
Number of Words in FIFO
FF
PAF
PAE
EF
CY7C4421V
CY7C4201V
CY7C4211V
0
0
0
H
H
H
H
H
L
H
H
H
H
L
L
L
L
H
H
H
H
H
1 to n[2]
1 to n[2]
1 to n[2]
(n+1) to 32
33 to (64−(m+1))
(64−m)[3] to 63
64
(n+1) to 128
129 to (256−(m+1))
(256−m)[3] to 255
256
(n+1) to 256
257 to (512−(m+1))
(512−m)[3] to 511
512
H
H
H
H
L
Number of Words in FIFO
FF PAF PAE
EF
CY7C4221V
0
1 to n[2]
CY7C4231V
CY7C4241V
CY7C4251V
0
0
0
H
H
H
H
H
L
H
H
H
H
L
L
L
L
H
H
H
H
H
1 to n[2]
1 to n[2]
1 to n[2]
(n+1) to 512
(n+1) to 1024
(n+1) to 2048
(n+1) to 4096
H
H
H
H
513 to (1024 −(m+1)) 1025 to (2048 −(m+1)) 2049 to (4096 −(m+1)) 4097 to (8192 −(m+1))
(1024−m)[3] to 1023
1024
(2048−m)[3] to 2047
2048
(4096−m)[3] to 4095
4096
(8192−m)[3] to 8191
8192
L
Notes
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n=7 default value).
3. m = Full Offset (m=7 default value).
Document #: 38-06010 Rev. *C
Page 6 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Width Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corre-
sponding input control signals of multiple devices. A composite
flag should be created for each of the end-point status flags (EF
and FF). The partial status flags (PAE and PAF) can be detected
from any one device. Figure demonstrates a 18-bit word width
by using two CY7C42X1Vs. Any word width can be attained by
adding additional CY7C42X1Vs.
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is
exclusively updated by each rising edge of WCLK.
When the CY7C42X1V is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (see
Figure ). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN1 and REN2. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Figure 4. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Low-Voltage Synchronous FIFO
Memory Used in a Width-Expansion Configuration
RESET(RS)
RESET(RS)
DATAIN (D)
18
9
9
READ CLOCK(RCLK)
WRITE CLOCK(WCLK)
READ ENABLE1 (REN1)
WRITE ENABLE1 (WEN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
WRITE ENABLE2/LOAD
(WEN2/LD)
CY7C42X1V
CY7C42X1V
PROGRAMMABLE (PAF)
FULL FLAG (FF) # 1
EF
EMPTY FLAG (EF) #2
EF
FF
FF
DATA OUT (Q)
9
18
FULL FLAG (FF) # 2
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Document #: 38-06010 Rev. *C
Page 7 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch up Current.....................................................> 200 mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied .............................................–-55°C to +125°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential................–0.5V to +5.0V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +5.0V
–40° to +85°C
DC Input Voltage ............................................–0.5V to +5.0V
Electrical Characteristics Over the Operating Range
7C42X1V-15
7C42X1V-25
7C42X1V-35
Parameter
Description
Test Conditions
Unit
Max
Min
Max
Min
Max
Min
VOH
Output HIGH Voltage
VCC = Min.,
2.4
2.4
2.4
V
IOH = −2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
OL = 8.0 mA
0.4
0.4
0.4
V
I
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
2.0
−0.5
−10
−10
5.0
0.8
2.0
−0.5
−10
−10
5.0
0.8
2.0
−0.5
−10
−10
5.0
0.8
V
V
Input Leakage Current VCC = Max.
+10
+10
+10
+10
+10
+10
μA
μA
IOZL
IOZH
Output OFF, High Z
Current
OE > VIH,
SS < VO < VCC
V
[4]
ICC
Active Power Supply
Current
Com’l
20
6
20
6
20
6
mA
mA
[5]
ISB
Average Standby
Current
Com’l
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max
Unit
CIN
5
7
pF
pF
V
COUT
Figure 5. AC Test Loads and Waveforms[7, 8]
R1 = 330Ω
3.3V
OUTPUT
ALL INPUT PULSES
3.0V
GND
90%
10%
90%
10%
R2 = 510Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth = 200Ω
OUTPUT
Vth = 2.0V
Notes
4. Outputs open. Tested at Frequency = 20 MHz.
5. All inputs = V – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
CC
6. Tested initially and after any design or process changes that may affect these parameters.
7.
8.
C
C
= 30 pF for all AC parameters except for t
.
L
L
OHZ
= 5 pF for t
.
OHZ
Document #: 38-06010 Rev. *C
Page 8 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Characteristics Over the Operating Range
7C42X1V-15
7C42X1V-25
7C42X1V-35
Parameter
Description
Unit
Min
Max
66.7
11
Min
Max
40
Min
Max
28.6
20
tS
Clock Cycle Frequency
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
Data Access Time
2
15
6
2
25
10
10
6
15
2
35
14
14
7
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set-Up Time
4
tDH
Data Hold Time
1
2
2
tENS
tENH
tRS
Enable Set-Up Time
4
6
7
Enable Hold Time
1
2
2
Reset Pulse Width[9]
15
10
10
25
15
15
35
20
20
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-Up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z[10]
Output Enable to Output Valid
Output Enable to Output in High Z[10]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
18
25
35
0
3
3
0
3
3
0
3
3
8
12
12
15
15
22
22
15
15
20
20
25
25
tOHZ
tWFF
tREF
tPAF
tPAE
tSKEW1
8
11
11
16
16
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
6
10
18
12
20
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
15
ns
Notes
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
Document #: 38-06010 Rev. *C
Page 9 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms
Figure 6. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
8
t
ENH
t
ENS
WEN1
NO OPERATION
NO OPERATION
WEN2
t
t
WFF
(if applicable)
WFF
FF
[11]
t
SKEW1
RCLK
REN1,REN2
Figure 7. Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1,REN2
NO OPERATION
t
REF
t
REF
EF
t
A
VALID DATA
Q –Q
0
8
t
OLZ
t
OHZ
t
OE
OE
[12]
t
SKEW1
WCLK
WEN1
WEN2
Notes
11. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
SKEW1
between the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK rising edge.
SKEW1
12. t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
SKEW1
between the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK rising edge.
SKEW1
Document #: 38-06010 Rev. *C
Page 10 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms (continued)
Figure 8. Reset Timing[13]
t
RS
RS
t
t
t
t
RSR
RSS
REN1,
REN2
RSR
RSS
WEN1
t
t
RSR
RSS
[15]
WEN2/LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
O =1 [14]
E
Q
Q
8
0 −
OE=0
Notes
13. The clocks (RCLK, WCLK) can be free-running during reset.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
Document #: 38-06010 Rev. *C
Page 11 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms (continued)
Figure 9. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
8
t
ENS
[16]
t
WEN1
FRL
WEN2
(if applicable)
t
SKEW1
RCLK
EF
t
REF
[17]
t
A
t
A
REN1,
REN2
Q –Q
D
0
D
1
0
8
t
OLZ
t
OE
OE
Notes
16. When t
> minimum specification, t
(maximum) = t
+ t
. When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
SKEW1 CLK
SKEW1
FRL
CLK
SKEW1
SKEW1
FRL
CLK
+ t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW1
17. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06010 Rev. *C
Page 12 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms (continued)
Figure 10. Empty Flag Timing
WCLK
t
t
DS
DS
DATAWRITE2
DATAWRITE1
D –D
0
8
t
t
ENH
ENH
t
ENS
WEN1
t
ENS
t
t
t
ENS
ENH
ENH
t
ENS
WEN2
(if applicable)
[16]
[16]
t
t
FRL
FRL
RCLK
t
t
t
REF
t
t
SKEW1
REF
REF
SKEW1
EF
REN1,
REN2
LOW
OE
t
A
DATA IN OUTPUT REGISTER
DATA READ
Q –Q
0
8
Document #: 38-06010 Rev. *C
Page 13 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms (continued)
Figure 11. Full Flag Timing
NO WRITE
NO WRITE
NO WRITE
WCLK
[11]
[11]
t
t
DATA WRITE
t
SKEW1
DS
SKEW1
DATA WRITE
D –D
0
8
t
t
t
WFF
WFF
WFF
FF
WEN1
WEN2
(if applicable)
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN1,
REN2
LOW
OE
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
8
Figure 12. Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN1
t
t
t
ENS
ENH
WEN2
(if applicable)
t
ENS
[18]
ENH
Note 19
PAE
N + 1 WORDS
INFIFO
Note 20
t
PAE
t
t
PAE
SKEW2
RCLK
t
ENS
t
t
ENH
ENS
REN1,
REN2
Notes
18. t
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
SKEW2
WCLK and the rising RCLK is less than t
, then PAE may not change state until the next RCLK.
SKEW2
19. PAE offset = n.
20. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
Document #: 38-06010 Rev. *C
Page 14 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms (continued)
Figure 13. Programmable Almost Full Flag Timing
Note 21
t
t
CLKL
CLKH
WCLK
WEN1
t
t
ENS
ENH
[22]
WEN2
(if applicable)
t
t
t
PAF
ENS
ENH
FULL − M WORDS
IN FIFO [23]
PAF
FULL − (M+1) WORDS
IN FIFO
[24]
t
t
PAF
SKEW2
RCLK
t
ENS
t
t
ENH
ENS
REN1,
REN2
Figure 14. Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
WEN1
t
t
DH
DS
D –D
0
8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes
21. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
22. PAF offset = m.
23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for
CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V.
24. t
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge
SKEW2
of RCLK and the rising edge of WCLK is less than t
, then PAF may not change state until the next WCLK.
SKEW2
Document #: 38-06010 Rev. *C
Page 15 of 19
[+] Feedback
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Switching Waveforms (continued)
Figure 15. Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENS
ENH
WEN2/LD
t
ENS
PAF OFFSET
MSB
REN1,
REN2
t
A
PAF OFFSET
LSB
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
Q –Q
0
8
Ordering Information
Speed (ns)
256 x 9 Low Voltage Synchronous FIFO
15 CY7C4201V-15AXC A32
512 x 9 Low Voltage Synchronous FIFO
Ordering Code
Package Name
Package Type
Operating Range
32-Pin Pb-Free Thin Quad Flatpack
15
CY7C4211V-15AI
CY7C4211V-15AXI
A32
A32
32-Pin Thin Quad Flatpack
Industrial
32-Pin Pb-Free Thin Quad Flatpack
1K x 9 Low Voltage Synchronous FIFO
15 CY7C4221V-15AC A32
4K x 9 Low Voltage Synchronous FIFO
15 CY7C4241V-15AXC A32
8K x 9 Low Voltage Synchronous FIFO
32-Pin Thin Quad Flatpack
Commercial
Commercial
32-Pin Pb-Free Thin Quad Flatpack
15
25
CY7C4251V-15AXC
CY7C4251V-25AXC
A32
A32
32-Pin Pb-Free Thin Quad Flatpack
32-Pin Pb-Free Thin Quad Flatpack
Commercial
Commercial
Document #: 38-06010 Rev. *C
Page 16 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Package Diagrams
Figure 16. 32-Pin TQFP (7X7X1.0 mm)
51-85063 *C
Document #: 38-06010 Rev. *C
Page 17 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Figure 17. 32-Pin PLCC (.453X.553) in
51-85002 *C
Document #: 38-06010 Rev. *C
Page 18 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Document History Page
Document Title: CY7C4201V/4211V/4221V/CY7C4241V/4251V Low Voltage 256/512/1K/4K/8K x 9
Synchronous FIFOs
Document Number: 38-06010
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
*A
106471
127857
09/10/01
08/25/03
SZV
FSG
Change from Spec number: 38-00622 to 38-06010
Fixed empty flag timing diagram
Fixed switching waveform diagram typo
*B
384573
See ECN
ESH
Added Pb-Free logo to top of front page
Inserted industrial temperature range into operating range
Added parts CY7C4251V-25AXC, CY7C4251V-15AXC, CY7C4241V-15AXC,
CY7C4241V-15JXC, CY7C4241V-25XC, CY7C4231V-25AXC,
CY7C4221V-15AI, CY7C4211V-15AXI, CY7C4201V-15AXC to ordering infor-
mation.
*C
2896039
03/19/2010
RAME
Added Contents
Updated package diagrams
Removed inactive parts from Ordering information table
Removed references to CY7C4421V and CY7C4231V parts
Updated links in Sales, Solutions and Legal Information
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06010 Rev. *C
Revised March 19, 2010
Page 19 of 19
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CY7C4251V-35AC
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