DS1044R-20 [ROCHESTER]
SILICON DELAY LINE, TRUE OUTPUT, PDSO14, 0.150 INCH, SOIC-14;
| 型号： | DS1044R-20 |
| 厂家： | 
Rochester Electronics |
| 描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO14, 0.150 INCH, SOIC-14 光电二极管 输出元件 逻辑集成电路 延迟线 |
| 文件： | 总11页 (文件大小：1001K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1044
DS1044
4–in–1 High–Speed Silicon Delay Line
FEATURES
PIN ASSIGNMENT
• All–silicon timing circuit
V
IN1
NC
IN2
IN3
IN4
1
2
3
4
5
14
13
12
11
10
CC
• Four independent buffered delays
• Initial delay tolerance ±1.5 ns
NC
OUT1
NC
• Stable and precise over temperature and voltage
OUT2
• Leading and trailing edge precision preserves the
input symmetry
NC
6
7
9
8
OUT3
OUT4
GND
• Standard 14–pin DIP, 14–pin SOIC (150 mil)
• Vapor phase, IR and wave solderable
• Available in Tape and Reel
DS1044 14–PIN DIP
DS1044R 14–PIN SOIC (150 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN1–IN4
OUT1–OUT4
NC
– Input Signals
– Output Signals
– No Connection
– +5 Volt Supply
– Ground
V
CC
GND
DESCRIPTION
The DS1044 series is a 4–in–1 version of the low–
power, +5 Volt, high speed, DS1035.
delay line solution. The DS1044’s nominal tolerance is
±1.5 ns and an additional tolerance over temperature
andvoltage of ±1.0 ns for the faster delays. Eachoutput
is capable of driving up to 10 LS loads.
TheDS1044seriesofdelaylineshavefourindependent
logic buffered delays in a single package. The device is
Dallas Semiconductor’s fastest 4–in–1 delay line. It is
available in a standard 14–pin DIP and 14–pin SOIC.
Standard delay values are indicated in Table 1. Cus-
tomers may contact Dallas Semiconductor at (972)
371–4348 for further information.
The device features precise leading and trailing edge
accuracies. It has the inherent reliability of an all–silicon
021798 1/6
DS1044
LOGIC DIAGRAM Figure 1
IN
OUT
TIME DELAY
ONE OF FOUR
PART NUMBER DELAY TABLE (tPLH, tPHL) Table 1
DELAY PER OUTPUT
TOLERANCE OVER
(temp and voltage)
PART NUMBER
(ns)
INITIAL TOLERANCE
DS1044–5
DS1044–6
DS1044–7
DS1044–8
DS1044–10
DS1044–12
DS1044–14
DS1044–18
DS1044–20
DS1044–25
5
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
±2.0 ns
±1.0 ns
±1.0 ns
±1.0 ns
±1.0 ns
±1.0 ns
±1.0 ns
±1.5 ns
±1.5 ns
±1.5 ns
±1.5 ns
6
7
8
10
12
14
18
20
25
NOTES:
1. Nominal conditions are +25°C and V =+5.0 volts.
CC
2. Temperature range of 0°C to 70°C and voltage range of 4.75 volts to 5.25 volts.
3. Delay accuracy are for both leading and trailing edges.
021798 2/6
DS1044
to the output. The DS1044 output taps are selected and
connected to the interval counter by a VHF switch con-
trol unit. All measurements are fully automated with
each instrument controlled by the computer over an
IEEE 488 bus.
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for
measuring the timing parameters of the DS1044. The
input waveform is produced by a precision pulse gener-
ator under software control. Time delays are measured
by a time interval counter (20 ps resolution) connected
DS1044 TEST CIRCUIT Figure 2
PULSE
GENERATOR
START
TIME INTERVAL
COUNTER
4
INPUTS
50Ω
STOP
VHF
UNIT UNDER
TEST
SWITCH
CONTROL
UNIT
OUT
50Ω
OUTPUTS 1–4
021798 3/6
DS1044
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–1.0V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
Short Circuit Output Current
–55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC=+5V ± 5%)
TEST
CONDITION
PARAMETER
Supply Voltage
Active Current
SYMBOL
MIN
TYP
MAX
5.25
45
UNITS
V
V
4.75
5.00
CC
CC
I
V
=5.25V
mA
CC
Period=1µs
High Level Input Voltage
Low Level Input Voltage
Input Leakage
V
2.2
V
+0.5
V
V
IH
CC
V
–0.5
–1.0
0.8
IL
L
I
0V<V <V
1.0
µA
mA
I
CC
High Level Output Current
I
V =4.75V
CC
–1.0
OH
V
OH
=4V
Low Level Output Current
I
OL
V
V
=4.75V
12
mA
CC
=0.5V
OL
AC ELECTRICAL CHARACTERISTICS
(+25°C; VCC=5V ± 5%)
PARAMETER
Period
SYMBOL
MIN
2 (t
TYP
MAX
UNITS
ns
NOTES
t
)
3
3
PERIOD
WI
Input Pulse Width
t
WI
100% of
ns
Tap Delay
Input–to–Tap Output Delay
Output Rise or Fall Time
Power–up Time
t
t
Table 1
2.0
ns
ns
PLH, PHL
t
, t
OR OF
2.5
t
100
ms
PU
CAPACITANCE
PARAMETER
(tA=25°C)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
10
pF
IN
021798 4/6
DS1044
TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C
Supply Voltage (V ): 5.0V ± 0.1V
CC
Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise and Fall Time: 3.0 ns Max. – Measured between 0.6V and 2.4V.
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load Capacitance: 15 pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM
PERIOD
t
t
FALL
RISE
80%
20%
1.5V
1.5V
1.5V
IN
t
t
WI
WI
t
PHL
t
PLH
1.5V
1.5V
OUT
NOTES:
1. All voltages are referenced to ground.
2. @ V =5 volts and 25°C, delay accuracy on both the rising and falling edges within tolerances given in
CC
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive
with respect to de–coupling, layout, etc.
021798 5/6
DS1044
t
Input Fall Time): The elapsed time between the
FALL (
TERMINOLOGY
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following
pulse.
80% and the 20% point on the trailing edge on the input
pulse.
t
(Time Delay, Rising): The elapsed time between
PLH
t
(Pulse Width): The elapsed time on the pulse
the 1.5 volt point on the leading edge of the input pulse
and the 1.5 volt point on the leading edge of the output
pulse.
WI
between the 1.5 volt point on the leading edge and the
1.5 volt point on the trailing edge or the 1.5 volt point on
the trailing edge and the 1.5 volt point on the leading
edge.
t
(Time Delay, Falling): The elapsed time between
PHL
the 1.5 volt point on the falling edge of the input pulse
and the 1.5 volt point on the falling edge of the output
pulse.
t
(Input Rise Time): The elapsed time between the
RISE
20% and the 80% point on the leading edge of the input
pulse.
021798 6/6
EN GL ISH • ? ? ? ? • ? ? ? • ? ? ?
BU Y C OM PA N Y M EM B ER S
W HA T ' S N EW PR ODUCT SS OLU TI ONS D E SI G N AP P NOT ES SUPP ORT
DS 1 04 4
Pa r t Nu mb e r T ab l e
N o te s:
1 . S ee t he DS1 044 Q uic kVie w D at a Sh ee t f or f urt her inf orm ati on o n th is p rodu ct fam i l y or d ow n lo a d th e D S 1 04 4
f ul l d at a s h ee t ( PD F , 3 6k B) .
2. O th er o p ti on s a n d l inks f or p urch asi ng p arts a re l is te d at : h t tp : / /w w w. m a xi m - ic. com /s al es .
3 . Did n' t F ind W ha t Y ou N e ed ? A sk our ap pli cat ion s e ng ine ers . Exp ert a ssi stance i n findi ng part s, us uall y wi thi n one
b us i ne ss d a y.
4 . Pa r t n u mb e r suf f ix e s: T o r T &R = ta p e a n d r e e l; + = Ro HS/le ad - fr e e ; # = RoH S/ lea d - e xe m p t. Mo r e : S e e f ul l da ta
s h ee t o r P a rt N a mi n g C o n v en t i o n s .
5 . * S om e p ac ka g es h ave v ariat io ns , li st ed o n t h e d ra w ing . "P kg Co de /V ar ia ti on " t e l ls w h i ch va ri a t io n th e p ro du c t
use s.
P art Num ber
D S 1 0 4 4 - 1 8
F r ee
Sa mp le
B uy
D i re c t
T em p
R oHS/L ead- Fr ee?
Ma t e ri a l s A n a ly s is
P a c ka g e : TY PE P INS S IZE
D R A WI N G C O D E / V A R *
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 0 4 4 - 2 5
D S 1 0 4 4 - 2 0
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 0 4 4 - 1 4
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D
S
1
0
4
4
-
1
2
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 0 4 4 - 1 0
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 0 4 4 - 8
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 0 4 4 - 7
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 0 4 4 - 6
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D
S
1
0
4
4
-
5
P DIP ; 14 pi n ;3 00
Dwg : 5 6 - G 5 0 0 5 - 0 0 1 A (P D F )
U se p k g co d e/ va ri a ti o n: P1 4- 4 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1044R -6 /T &R
D S 1 04 4 R -1 0 +
D S1044R- 20/T &R
D S 10 4 4 R -5 / T &R
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S14+ 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1044R- 18/T &R
D S1044R- 14/T &R
D S1044R- 12/T &R
D S 10 4 4 R -8 / T &R
D S 10 4 4 R -7 / T &R
DS 1 04 4R -8
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
DS 1 04 4R -6
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
DS 1 04 4 R- 2 5/ T &R /
DS 1 04 4R -1 0+T & R
D S1 0 4 4 R- 7
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S14+ 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1 04 4 R- 1 0
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S1 04 4 R- 1 2
D S1 04 4 R- 1 4
D S1 04 4 R- 1 8
D S1 04 4 R- 2 0
D S1 04 4 R- 2 5
D S 1 04 4 R -2 5 +
DS 1 04 4R -5
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
Use pkgcode/v ariation : S14+ 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
S O I C ; 1 4 p i n ; 1 5 0
Dwg : 5 6 - G 2 0 0 8 - 0 0 1 C (P D F )
U se p k g co d e/ va ri a ti o n: S1 4- 1 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
Did n' t F ind W ha t You Ne ed ?
CO NT ACT U S: SE ND US AN EMAI L
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