DS2760BE-025 [ROCHESTER]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, TSSOP-16;
| 型号： | DS2760BE-025 |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, TSSOP-16 光电二极管 |
| 文件： | 总26页 (文件大小：972K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2760
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
1
2
3
4
CꢀLi+ safety circuit
- Overvoltage protection
A
B
CC
PLS
DC
1
2
16
15
14
13
12
11
10
9
VIN
VDD
PIO
VSS
VSS
VSS
PS
SNS
- Overcurrent/short circuit protection
- Undervoltage protection
PLS DC
DQ
3
C
D
CꢀZero Volt Battery Recovery Charge
CꢀAvailable in two configurations:
- Internal 25mꢀ sense resistor
SNS
CC
IS2
IS1
SNS
4
5
6
7
8
Probe
SNS
SNS
VSS
VIN
Probe
- External user-selectable sense resistor
CꢀCurrent measurement
E
F
DQ
IS2
VDD PIO
PS
IS1
VSS
DS2760
- 12-bit bidirectional measurement
- Internal sense resistor configuration:
0.625mA LSB and ±1.9A dynamic range
- External sense resistor configuration:
15.625ꢁV LSB and ±64mV dynamic range
CꢀCurrent accumulation
DS2760
16-Pin TSSOP Package
Flip-Chip Packaging
Top View
PIN DESCRIPTION
- Charge control output
CC
DC
- Internal sense resistor: 0.25mAhr LSB
- External sense resistor: 6.25ꢁVhr LSB
CꢀVoltage measurement with 4.88mV resolution
CꢀTemperature measurement using integrated
sensor with 0.125LC resolution
- Discharge control output
DQ - Data input/output
PIO - Programmable I/O pin
PLS - Battery pack positive terminal input
- Power switch sense input
PS
CꢀSystem power management and control feature
support
VIN - Voltage sense input
VDD - Power supply input (2.5V to 5.5V)
VSS - Device ground
Cꢀ32 bytes of lockable EEPROM
Cꢀ16 bytes of general purpose SRAM
CꢀDallas 1-Wire® interface with unique 64-bit
device address
SNS - Sense resistor connection
IS1 - Current sense input
IS2 - Current sense input
SNS Probe - Do not connect
VSS Probe - Do not connect
CꢀLow power consumption:
- Active current: 90ꢁA max
- Sleep current:
2ꢁA max
1-Wire is a registered trademark of Dallas Semiconductor.
1 of 25
010906
DS2760
ORDERING INFORMATION
Part
Marking
DS2760A
DS2760B
DS2760A
DS2760B
2760A25
2760B25
Description
DS2760AE+
DS2760BE+
DS2760AE+T&R
DS2760 BE+T&R
DS2760AE+025
DS2760BE+025
TSSOP, External Sense Resistor, 4.275V Vov, Lead-Free
TSSOP, External Sense Resistor, 4.35V Vov, Lead-Free
DS2760AE+ on Tape & Reel, Lead-Free
DS2760BE+ on Tape & Reel, Lead-Free
TSSOP, 25mꢀ Sense Resistor, 4.275V Vov, Lead-Free
TSSOP, 25mꢀ Sense Resistor, 4.35V Vov, Lead-Free
DS2760AE+025 in Tape & Reel, Lead-Free
DS2760BE+025 in Tape & Reel, Lead-Free
Flipchip, External Sense Resistor, Tape & Reel, 4.275V Vov
Flipchip, External Sense Resistor, Tape & Reel, 4.35V Vov
Flipchip, 25mꢀ Sense Resistor, Tape & Reel, 4.275V Vov
Flipchip, 25mꢀ Sense Resistor, Tape & Reel, 4.35V Vov
TSSOP, External Sense Resistor, 4.275V Vov
TSSOP, External Sense Resistor, 4.35V Vov
DS2760AE on Tape & Reel
DS2760AE+025/T&R 2760A25
DS2760BE+025/T&R 2760B25
DS2760AX
DS2760A
DS2760B
DS2760AR
DS2760BR
DS2760A
DS2760B
DS2760A
DS2760B
2760A25
2760B25
DS2760BX
DS2760AX-025
DS2760BX-025
DS2760AE
DS2760BE
DS2760AE/T&R
DS2760 BE/T&R
DS2760AE-025
DS2760BE-025
DS2760BE on Tape & Reel
TSSOP, 25mꢀ Sense Resistor, 4.275V Vov
TSSOP, 25mꢀ Sense Resistor, 4.35V Vov
DS2760AE-025 in Tape & Reel
DS2760AE-025/T&R 2760A25
DS2760BE-025/T&R 2760B25
DS2760BE-025 in Tape & Reel
DESCRIPTION
The DS2760 High-Precision Li+ Battery Monitor is a data acquisition, information storage, and safety
protection device tailored for cost-sensitive battery pack applications. This low-power device integrates
precise temperature, voltage, and current measurement, nonvolatile data storage, and Li+ protection into
the small footprint of either a TSSOP package or flip chip. The DS2760 is a key component in
applications including remaining capacity estimation, safety monitoring, and battery-specific data storage.
Via its 1-Wire interface, the DS2760 gives the host system read/write access to status and control
registers, instrumentation registers, and general purpose data storage. Each device has a unique factory-
programmed 64-bit net address which allows it to be individually addressed by the host system,
supporting multi-battery operation.
The DS2760 is capable of performing temperature, voltage and current measurement to a resolution
sufficient to support process monitoring applications such as battery charge control, remaining capacity
estimation, and safety monitoring. Temperature is measured using an on-chip sensor, eliminating the need
for a separate thermistor. Bidirectional current measurement and accumulation are accomplished using
either an internal 25mꢀ sense resistor or an external device. The DS2760 also features a programmable
I/O pin that allows the host system to sense and control other electronics in the pack, including switches,
vibration motors, speakers and LEDs.
Three types of memory are provided on the DS2760 for battery information storage: EEPROM, lockable
EEPROM and SRAM. EEPROM memory saves important battery data in true nonvolatile memory that
is unaffected by severe battery depletion, accidental shorts or ESD events. Lockable EEPROM becomes
ROM when locked to provide additional security for unchanging battery data. SRAM provides
inexpensive storage for temporary data.
2
DS2760
BLOCK DIAGRAM Figure 1
1-WIRE
REGISTERS AND
USER MEMORY
DQ
INTERFACE
AND
LOCKABLE EEPROM
SRAM
ADDRESS
VOLTAGE
THERMAL
SENSE
REFERENCE
TEMPERATURE
VOLTAGE
VIN
IS1
MUX
ADC
CURRENT
+
-
TIMEBASE
ACCUM. CURRENT
STATUS / CONTROL
IS2
PIO
PLS
PS
LI+ PROTECTION
CC
DC
internal sense resistor configuration only
25mꢀ
chip ground
SNS
VSS
IS2
IS1
3
DS2760
DETAILED PIN DESCRIPTION Table 1
SYMBOL TSSOP*
FLIP
CHIP*
C1
DESCRIPTION
1
3
7
Charge Protection Control Output. Controls an external p-channel
CC
DC
DQ
high-side charge protection FET.
B2
B4
Discharge Protection Control Output. Controls an external p-channel
high-side discharge protection FET.
Data Input/Out. 1-Wire data line. Open-drain output driver. Connect
this pin to the DATA terminal of the battery pack. Pin has an internal
1ꢁA pull-down for sensing disconnection.
14
2
E2
B1
Programmable I/O Pin. Used to control and monitor user-defined
PIO
PLS
external circuitry. Open drain to VSS.
Battery Pack Positive Terminal Input. The device monitors the state of
the battery pack’s positive terminal through this pin in order to detect
events such as the attachment of a charger or the removal of a short
circuit. Additionally, a charge path to recover a deeply depleted cell is
provided from PLS to VDD.
10
16
E4
D1
Power Switch Sense Input. The device wakes up from Sleep Mode
when it senses the closure of a switch to VSS on this pin. Pin has an
internal 1ꢁA pull-up to VDD.
PS
VIN
VDD
VSS
Voltage Sense Input. The voltage of the Li+ cell is monitored via this
input pin. This pin has a weak pullup to VDD.
15
E1
F3
Power Supply Input. Connect to the positive terminal of the Li+ cell
through a decoupling network.
11,12,13
Device Ground. Connect directly to the negative terminal of the Li+ cell.
For the external sense resistor configuration, connect the sense resistor
between VSS and SNS.
SNS
IS1
4,5,6
9
A3
D4
Sense Resistor Connection. Connect to the negative terminal of the
battery pack. In the internal sense resistor configuration, the sense resistor
is connected between VSS and SNS.
Current Sense Input. This pin is internally connected to VSS through a
4.7kꢀ resistor. Connect a 0.1ꢁF capacitor between IS1 and IS2 to
complete a low-pass input filter.
IS2
8
C4
C2
Current Sense Input. This pin is internally connected to SNS through a
4.7kꢀ resistor.
SNS
Probe
VSS
N/A
Do Not Connect.
Do Not Connect.
N/A
D2
Probe
* Mechanical drawing for the 16-pin TSSOP and DS2760 flip-chip package can be found at:
http://pdfserv.maxim-ic.com/arpdf/Packages/16tssop.pdf
http://pdfserv.maxim-ic.com/arpdf/Packages/chips/2760x.pdf
4
DS2760
APPLICATION EXAMPLE Figure 2
102
BAT+
PACK+
150ꢀ
1kꢀ
1kꢀ
1kꢀ
DS2760
CC
PLS
DC
VIN
VDD
104
PIO
VSS
VSS
VSS
PS
150ꢀ
SNS
SNS
SNS
DQ
150ꢀ
PS
IS2
IS1
4.7kꢀ
102
104
PACK-
BAT-
(1)
RSENS
DS2760
SNS
VSS
(2)
RSENSINT
RKS
IS1
RKS
IS2
voltage
sense
1 – RSENS is present for external sense resistor configurations only
2 – RSENSINT is present for internal sense resistor configurations only
5
DS2760
POWER MODES
The DS2760 has two power modes: Active and Sleep. While in Active Mode, the DS2760 continually
measures current, voltage and temperature to provide data to the host system and to support current
accumulation and Li+ safety monitoring. In Sleep Mode, the DS2760 ceases these activities. The
DS2760 enters Sleep Mode when any of the following conditions occurs:
Cꢀthe PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than
2 seconds (pack disconnection)
Cꢀthe voltage on VIN drops below undervoltage threshold VUV for tUVD (cell depletion)
Cꢀthe pack is disabled through the issuance of a SWAP command (SWEN bit =1)
The DS2760 returns to Active Mode when any of the following occurs:
Cꢀthe PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high
(pack connection)
Cꢀthe
pin is pulled low (power switch)
PS
Cꢀthe voltage on PLS becomes greater than the voltage on VIN (charger connection) with the SWEN bit
set to 0
Cꢀthe pack is enabled through the issuance of a SWAP command (SWEN bit =1)
The DS2760 defaults to Sleep Mode when power is first applied.
LI+ PROTECTION CIRCUITRY
During Active Mode, the DS2760 constantly monitors cell voltage and current to protect the battery from
overcharge (overvoltage), overdischarge (undervoltage) and excessive charge and discharge currents
(overcurrent, short circuit). Conditions and DS2760 responses are described in the sections below and
summarized in Table 2 and Figure 3.
LI+ PROTECTION CONDITIONS AND DS2760 RESPONSES Table 2
Condition
Name
Activation
Delay
tOVD
tUVD
Release
Threshold
VIN < VCE(1)
Threshold
VIN > VOV
VIN < VUV
Response
high
Overvoltage
CC
Undervoltage
VPLS > VDD
,
high,
CC DC
(charger connected)
Sleep Mode
(2)
(3)
Overcurrent, Charge
Overcurrent, Discharge
Short Circuit
VIS > VOC
tOCD
tOCD
VPLS < VDD – VTP
,
high
CC DC
(2)
(4)
VIS < -VOC
VPLS > VDD – VTP
high
DC
DC
(4)
VSNS > VSC
tSCD
and VDD for
VPLS > VDD – VTP
high
VIS = VIS1 – VIS2. Logic high = VPLS for
All voltages are with respect to VSS. ISNS
DC.
CC
references current delivered from pin SNS.
(1) If VDD <2.2V, release is delayed until the recovery charge current (IRC) passed from PLS to VDD
charges the battery and allows VDD to exceed 2.2V.
(2) for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of
current: ISNS > IOC for charge direction and ISNS < -IOC for discharge direction
(3) with test current ITST current flowing from PLS to VSS (pull-down on PLS)
(4) with test current ITST current flowing from VDD to PLS (pull-up on PLS)
Overvoltage. If the voltage of the cell exceeds overvoltage threshold VOV for a period longer than
overvoltage delay tOVD, the DS2760 shuts off the external charge FET and sets the OV flag in the
Protection Register. When the cell voltage falls below charge enable threshold VCE, the DS2760 turns the
6
DS2760
charge FET back on (unless another protection condition prevents it). Discharging remains enabled
during overvoltage.
Undervoltage. If the voltage of the cell drops below undervoltage threshold VUV for a period longer than
undervoltage delay tUVD, the DS2760 shuts off the charge and discharge FETs, sets the UV flag in the
Protection Register, and enters Sleep Mode. The DS2760 provides a current-limited (IRC) recovery
charge path from PLS to VDD to gently charge severely depleted cells. The recovery path is enabled
when 0 ? VDD < 3V(typ). Once VDD reaches 3V(typ), the DS2760 will return to normal operation,
awaiting connection of a charger to turn on the charge FET and pull out of Sleep Mode.
Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (VIS = VIS1
– VIS2) is the filtered voltage drop across the current sense resistor. If VIS exceeds overcurrent threshold
VOC for a period longer than overcurrent delay tOCD, the DS2760 shuts off both external FETs and sets the
COC flag in the Protection Register. The charge current path is not re-established until the voltage on the
PLS pin drops below VDD – VTP. The DS2760 provides a test current of value ITST from PLS to VSS to
pull PLS down in order to detect the removal of the offending charge current source.
Overcurrent, Discharge Direction. If VIS is less than –VOC for a period longer than tOCD, the DS2760
shuts off the external discharge FET and sets the DOC flag in the Protection Register. The discharge
current path is not re-established until the voltage on PLS rises above VDD – VTP. The DS2760 provides a
test current of value ITST from VDD to PLS to pull PLS up in order to detect the removal of the offending
low-impedance load.
Short Circuit. If the voltage on the SNS pin with respect to VSS exceeds short circuit threshold VSC for
a period longer than short circuit delay tSCD, the DS2760 shuts off the external discharge FET and sets the
DOC flag in the Protection Register. The discharge current path is not re-established until the voltage on
PLS rises above VDD – VTP. The DS2760 provides a test current of value ITST from VDD to PLS to pull
PLS up in order to detect the removal of the short circuit.
LITHIUM-ION PROTECTION CIRCUITRY EXAMPLE WAVEFORMS Figure 3
VOV
VCE
VCELL
VUV
charge
VIS
VOC
0
-VOC
-VSC
discharge
(1)
VPLS
VSS
tOVD
tOVD
tOCD
CC
VDD
VSS
t
t
t
DC
active
Sleep
Mode
inactive
(1) To allow the device to react quickly to short circuits, detection is actually done on the SNS pin rather
than on the filtered IS1 and IS2 pins. The actual short circuit detect condition is VSNS > VSC.
7
DS2760
Summary. All of the protection conditions described above are OR’ed together to affect the
and
DC
CC
outputs.
= (Undervoltage) or (Overcurrent, EITHER Direction) or (Short Circuit) or
(Protection Register bit DE = 0) or (Sleep Mode)
DC
= (Overvoltage) or (Undervoltage) or (Overcurrent, Charge Direction) or (Protection Register
CC
bit CE = 0) or (Sleep Mode)
CURRENT MEASUREMENT
In the Active Mode of operation, the DS2760 continually measures the current flow into and out of the
battery by measuring the voltage drop across a current sense resistor. The DS2760 is available in two
configurations: (1) internal 25mꢀ current sense resistor, and (2) external user-selectable sense resistor. In
either configuration, the DS2760 considers the voltage difference between pins IS1 and IS2 (VIS = VIS1
–
VIS2) to be the filtered voltage drop across the sense resistor. A positive VIS value indicates current is
flowing into the battery (charging), while a negative VIS value indicates current is flowing out of the
battery (discharging).
VIS is measured with a signed resolution of 12-bits. The current register is updated in two’s complement
format every 88ms (128/fsample) with an average of 128 readings. Currents outside the range of the
register are reported at the limit of the range. The format of the Current Register is shown in Figure 4.
For the internal sense resistor configuration, the DS2760 maintains the Current Register in units of Amps,
with a resolution of 0.625mA and full scale range of no less than M1.9A (see Note 7 on IFS spec for more
details). The DS2760 automatically compensates for internal sense resistor process variations and
temperature effects when reporting current.
For the external sense resistor configuration, the DS2760 writes the measured VIS voltage to the Current
Register, with a resolution of 15.625ꢁV and a full scale range of M64mV.
CURRENT REGISTER FORMAT Figure 4
MSB—Address 0E
211 210 29 28 27 26 25
LSb—Address 0F
24 23 22 21 20
S
X
X
X
MSb
LSb
MSb
LSb
Units: 0.625 mA for internal sense resistor
15.625 ꢀV for external sense resistor
CURRENT ACCUMULATOR
The Current Accumulator facilitates remaining capacity estimation by tracking the net current flow into
and out of the battery. Current flow into the battery increments the Current Accumulator while current
flow out of the battery decrements it. Data is maintained in the Current Accumulator in two’s-
complement format. The format of the Current Accumulator is shown in Figure 5.
When the internal sense resistor is used, the DS2760 maintains the Current Accumulator in units of Amp-
hours, with a resolution of 0.25mAhrs and full scale range of M8.2Ahrs. When using an external sense
8
DS2760
resistor, the DS2760 maintains the Current Accumulator in units of Volt-hours, with a resolution of
6.25 ꢁVhrs and a full scale range of M205 mVhrs.
The Current Accumulator is a read/write register that can be altered by the host system as needed.
CURRENT ACCUMULATOR FORMAT Figure 5
MSB—Address 10
LSb—Address 11
S
214 213 212 211 210 29 28
27 26 25 24 23 22 21 20
MSb
LSb
MSb
LSb
Units: 0.25 mAhrs for internal sense resistor
6.25 ꢀVhrs for external sense resistor
CURRENT OFFSET COMPENSATION
Current measurement and the current accumulation are both internally compensated for offset on a
continual basis minimizing error resulting from variations in device temperature and voltage.
Additionally a constant bias may be utilized to alter any other sources of offset. This bias resides in
EEPROM address 33h in two’s-complement format and is subtracted from each current measurement.
The current offset bias is applied to both the internal and external sense resistor configurations. The
factory default for the current offset compensation is a value of 0.
CURRENT OFFSET BIAS Figure 6
Address 33
S
26 25 24 23 22 21 20
MSb
LSb
Units: 0.625 mA for internal sense resistor
15.625 ꢀV for external sense resistor
VOLTAGE MEASUREMENT
The DS2760 continually measures the voltage between pins VIN and VSS over a range of 0 to 4.75V.
The resulting data is placed in the Voltage Register in two’s-complement format with a resolution of
4.88mV. Voltages above the maximum register value are reported as the maximum value. The Voltage
Register format is shown in Figure 7.
VOLTAGE REGISTER FORMAT Figure 7
MSB—Address 0C
29 28 27 26 25 24 23
LSb—Address 0D
22 21 20
MSb
S
X
X
X
X
X
MSb
LSb
LSb
Units: 4.88 mV
9
DS2760
TEMPERATURE MEASUREMENT
The DS2760 uses an integrated temperature sensor to continually measure battery temperature.
Temperature measurements are placed in the Temperature Register in two’s-complement format with a
resolution of 0.125°C over a range of M127°C. The Temperature Register format is shown in Figure 8.
TEMPERATURE REGISTER FORMAT Figure 8
MSB—Address 18
29 28 27 26 25 24 23
LSB—Address 19
22 21 20
MSb
S
X
X
X
X
X
MSb
LSb
LSb
Units: 0.125LC
PROGRAMMABLE I/O
To use the PIO pin as an output, write the desired output value to the PIO bit in the Special Feature
Register. Writing a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to VSS. Writing a
1 to the PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To
sense the value on the PIO pin, read the PIO bit. The DS2760 turns off the PIO output driver and sets the
PIO high when it enters Sleep Mode or when DQ is low for more than 2 seconds, regardless of the state
of the PMOD bit.
POWER SWITCH INPUT
The DS2760 provides a power control function that uses the discharge protection FET to gate battery
power to the system. The
pin, internally pulled to VDD through a 1ꢁA current source, is continuously
PS
monitored for a low-impedance connection to VSS. If the DS2760 is in Sleep Mode, the detection of a
low on causes the device to transition into Active Mode, turning on the discharge FET. If the DS2760
PS
is already in Active Mode, activity on
has no effect other than the mirroring of its logic level in the
PS
bit in the Special Feature Register. The reading of a 0 in the
bit should be immediately followed
PS
PS
by writing a 1 to the
bit to ensure proper operation.
PS
MEMORY
The DS2760 has a 256-byte linear address space with registers for instrumentation, status and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general-purpose except addresses 30h, 31h, and 33h,
which should be written with the default values for the Protection Register, Status Register, and Current
Offset Register, respectively. When the MSB of any 2-byte register is read, both the MSB and LSB are
latched and held for the duration of the Read Data command to prevent updates during the read and
ensure synchronization between the two register bytes. For consistent results, always read the MSB and
the LSB of a two-byte register during the same Read Data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the Write Data
command updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The
Copy Data command copies the contents of shadow RAM to EEPROM in an unlocked block of
EEPROM but has no effect on locked blocks. The Recall Data command copies the contents of a block of
EEPROM to shadow RAM regardless of whether the block is locked or not.
10
DS2760
MEMORY MAP Table 3
Address (Hex)
Description
Read/Write
00
01
Protection Register
R/W
R
Status Register
Reserved
02-06
07
EEPROM Register
R/W
R/W
08
Special Feature Register
Reserved
09-0B
0C
Voltage Register MSb
Voltage Register LSb
Current Register MSB
Current Register LSb
Accumulated Current Register MSB
Accumulated Current Register LSb
Reserved
R
R
0D
0E
R
0F
R
10
R/W
R/W
11
12-17
18
Temperature Register MSB
Temperature Register LSb
Reserved
R
R
19
1A-1F
20-2F
30-3F
40-7F
80-8F
90-FF
EEPROM, block 0
EEPROM, block 1
Reserved
SRAM
Reserved
R/W*
R/W*
R/W
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTER
The Protection Register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, COC and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The default
values of the CE and DE bits of the Protection Register are stored in lockable EEPROM in the
corresponding bits in address 30h. A Recall Data command for EEPROM block 1 recalls the default
values of 1 into CE and DE. The format of the Protection Register is shown in Figure 9. The function of
each bit is described in detail in the following paragraphs.
PROTECTION REGISTER FORMAT Figure 9
Address 00
bit 7
OV
bit 6
UV
bit 5
bit 4
bit 3
bit 2
bit 1
CE
bit 0
DE
COC
DOC
CC
DC
OV – Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage
condition. This bit must be reset by the host system.
UV – Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
undervoltage condition. This bit must be reset by the host system.
11
DS2760
COC – Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
charge-direction overcurrent condition. This bit must be reset by the host system.
DOC – Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
discharge-direction overcurrent condition. This bit must be reset by the host system.
CC – CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.
DC – DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE – Charge Enable. Writing a 0 to this bit disables charging (CC output high, external charge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2760 automatically sets this bit to 1 when it transitions
from Sleep Mode to Active Mode.
DE – Discharge Enable. Writing a 0 to this bit disables discharging (DC output high, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2760 automatically sets this bit to 1 when
it transitions from Sleep Mode to Active Mode.
STATUS REGISTER
The default values for the Status Register bits are stored in lockable EEPROM in the corresponding bits
of address 31h. A Recall Data command for EEPROM block 1 recalls the default values into the Status
Register bits. The format of the Status Register is shown in Figure 10. The function of each bit is
described in detail in the following paragraphs.
STATUS REGISTER FORMAT Figure 10
Address 01
bit 7
X
bit 6
X
bit 5
bit 4
bit 3
bit 2
X
bit 1
X
bit 0
X
PMOD RNAOP SWEN
PMOD – Sleep Mode Enable. A value of 1 in this bit enables the DS2760 to enter Sleep Mode when the
DQ line goes low for greater than 2 seconds and leave Sleep Mode when the DQ line goes high. A value
of 0 disables DQ-related transitions into and out of Sleep Mode. This bit is read-only. The desired
default value should be set in bit 5 of address 31h. The factory default is 0.
RNAOP – Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address
command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should
be set in bit 4 of address 31h. The factory default is 0.
SWEN - SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP
command. If set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of
address 31h. This bit is read-only. The factory default is 0.
X – Reserved bits.
12
DS2760
EEPROM REGISTER
The format of the EEPROM Register is shown in Figure 11. The function of each bit is described in
detail in the following paragraphs.
EEPROM REGISTER FORMAT Figure 11
Address 07
bit 7
EEC
bit 6
bit 5
X
bit 4
X
bit 3
X
bit 2
X
bit 1
BL1
bit 0
BL0
LOCK
EEC – EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data command is in
progress. While this bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that
data may be written to unlocked EEPROM blocks.
LOCK – EEPROM Lock Enable. When this bit is 0, the Lock command is ignored. Writing a 1 to this
bit enables the Lock command. After the Lock command is executed, the LOCK bit is reset to 0. The
factory default is 0.
BL1 – EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM Block 1
(addresses 30-3F) is locked (read-only) while a 0 indicates Block 1 is unlocked (read/write).
BL0 – EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM Block 0
(addresses 20-2F) is locked (read-only) while a 0 indicates Block 0 is unlocked (read/write).
X – Reserved bits.
SPECIAL FEATURE REGISTER
The format of the Special Feature Register is shown in Figure 12. The function of each bit is described in
detail in the following paragraphs.
SPECIAL FEATURE REGISTER FORMAT Figure 12
Address 08
bit 7
bit 6
PIO
bit 5
bit 4
X
bit 3
X
bit 2
X
bit 1
X
bit 0
X
MSTR
PS
PS – PS Pin Mirror. This read-only bit mirrors the state of the PS pin. The reading of a 0 in this bit
should be immediately followed by writing a 1 to this location to insure proper operation.
PIO – PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.
MSTR - SWAP Master Status Bit. This bit indicates whether a device has been selected through the
SWAP command. Selection of this device through the SWAP command and the appropriate Net Address
will result in setting this bit, indicating that this device is the master. A 0 signifies that this device is not
the master.
X – Reserved bits.
13
DS2760
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. A multidrop bus is a
1-Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the
DS2760 is a slave device. The bus master is typically a microprocessor in the host system. The
discussion of this bus system consists of four topics: 64-Bit Net Address, Hardware Configuration,
Transaction Sequence, and 1-Wire Signaling.
64-BIT NET ADDRESS
Each DS2760 has a unique, factory-programmed 1-Wire net address which is 64 bits in length. The first
8 bits are the 1-Wire family code (30h for DS2760). The next 48 bits are a unique serial number. The
last 8 bits are a CRC of the first 56 bits (see Figure 13). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2760 to communicate via the 1-Wire protocol detailed in the
1-Wire Bus System section of this data sheet.
1-WIRE NET ADDRESS FORMAT Figure 13
8-bit CRC
MSb
48-bit Serial Number
8-Bit Family Code 30h)
LSb
CRC GENERATION
The DS2760 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure
error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of
the address and compare it to the CRC from the DS2760. The host system is responsible for verifying the
CRC value and taking action as a result. The DS2760 does not compare CRC values and does not
prevent a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC
can result in a communication channel with a very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as
shown in Figure 10, or it can be generated in software. Additional information about the Dallas 1-Wire
Cyclic Redundancy Check is available in Application Note 27 entitled “Understanding and Using Cyclic
Redundancy Checks with Dallas Semiconductor Touch Memory Products”. (This application note can be
found on the Maxim/Dallas Semiconductor website at www.maxim-ic.com).
In the circuit in Figure 14, the shift register bits are initialized to 0. Then, starting with the least
significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has
been entered, then the serial number is entered. After the 48th bit of the serial number has been entered,
the shift register contains the CRC value.
14
DS2760
1-WIRE CRC GENERATION BLOCK DIAGRAM Figure 14
input
XOR
MSb
LSb
XOR
XOR
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2760 used an open-drain output driver as part of
the bidirectional interface circuitry shown in Figure 15. If a bidirectional pin is not available on the bus
master, separate output and input pins can be tied together.
The 1-Wire bus must have a pull-up resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5kꢀ. The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus MUST be left in the idle state in order to properly
resume the transaction later. If the bus is left low for more than 120ꢀs, slave devices on the bus begin to
interpret the low period as a Reset Pulse, effectively terminating the transaction.
1-WIRE BUS INTERFACE CIRCUITRY Figure 15
BUS MASTER
DS2760 1-WIRE PORT
+VPULLUP (2.0V–5.5V)
4.7kꢀ
Rx
Rx
Tx
1ꢁA
Tx
Typ.
Rx = Receive
Tx = Transmit
100ꢀ
MOSFET
TRANSACTION SEQUENCE
The protocol for accessing the DS2760 via the 1-Wire port is as follows:
CꢀInitialization
CꢀNet Address Command
CꢀFunction Command
CꢀTransaction/Data
The sections that follow describe each of these steps in detail.
15
DS2760
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a Reset Pulse
transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2760
and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on
the bus and ready to operate. For more details, see the 1-Wire Signaling section.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the Net Address
Commands described in the following paragraphs. The name of each ROM Command is followed by the
8-bit opcode for that command in square brackets. Figure 16 presents a transaction flowchart of the Net
Address Commands.
Read Net Address [33h or 39h]. This command allows the bus master to read the DS2760’s 1-Wire net
address. This command can only be used if there is a single slave on the bus. If more than one slave is
present, a data collision occurs when all slaves try to transmit at the same time (open-drain produces a
wired-AND result). The RNAOP bit in the Status Register selects the opcode for this command, with
RNAOP=0 indicating 33h and RNAOP=1 indicating 39h.
Match Net Address [55h]. This command allows the bus master to specifically address one DS2760 on
the 1-Wire bus. Only the addressed DS2760 responds to any subsequent Function Command. All other
slave devices ignore the Function Command and wait for a reset pulse. This command can be used with
one or more slave devices on the bus.
Skip Net Address [CCh]. This command saves time when there is only one DS2760 on the bus by
allowing the bus master to issue a Function Command without specifying the address of the slave. If
more than one slave device is present on the bus, a subsequent Function Command can cause a data
collision when all slaves transmit data at the same time.
Search Net Address [F0h]. This command allows the bus master to use a process of elimination to
identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the
repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired
value of that bit. The bus master performs this simple three-step routine on each bit location of the net
address. After one complete pass through all 64 bits, the bus master knows the address of one device.
The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the
Book of DS19xx iButton® Standards for a comprehensive discussion of a net address search, including an
actual example. (This publication can be found on the Maxim/Dallas Semiconductor website at
www.maxim-ic.com).
SWAP [AAh]. SWAP is a Net Address level command specifically intended to aid in distributed
multiplexing applications and is described specifically with regards to power control using the 27xx series
of products. The term power control refers to the ability of the DS2760 to control the flow of power into
or out the battery pack using control pins DC and CC . The SWAP command is issued followed by the
Net Address. The effect is to cause the addressed device to enable power to or from the system while
simultaneously (break-before-make) deselecting and powering down (SLEEP) all other packs. This
switching sequence is controlled by a timing pulse issued on the DQ line following the net address. The
falling edge of the pulse is used to disable power with the rising edge enabling power flow by the selected
device. The DS2760 will recognize a SWAP command, device address, and timing pulse if and only if
the SWEN bit is set.
iButton is a registered trademark of Dallas Semiconductor.
16
DS2760
FUNCTION COMMANDS
After successfully completing one of the Net Address Commands, the bus master can access the features
of the DS2760 with any of the Function Commands described in the following paragraphs. The name of
each function is followed by the 8-bit opcode for that command in square brackets.
Read Data [69h, XX]. This command reads data from the DS2760 starting at memory address XX. The
LSb of the data in address XX is available to be read immediately after the MSb of the address has been
entered. Because the address is automatically incremented after the MSb of each byte is received, the
LSb of the data at address XX+1 is available to be read immediately after the MSb of the data at address
XX. If the bus master continues to read beyond address FFh, the DS2760 outputs logic 1 until a Reset
Pulse occurs. Addresses labeled “Reserved” in the Memory Map contain undefined data. The Read Data
command may be terminated by the bus master with a Reset Pulse at any bit boundary.
Write Data [6 Ch, XX]. This command writes data to the DS2760 starting at memory address XX. The
LSb of the data to be stored at address XX can be written immediately after the MSb of address has been
entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb
to be stored at address XX+1 can be written immediately after the MSb to be stored at address XX. If the
bus master continues to write beyond address FFh, the DS2760 ignores the data. Writes to read-only
addresses, reserved addresses and locked EEPROM blocks are ignored. Incomplete bytes are not written.
Writes to unlocked EEPROM blocks are to shadow RAM rather than EEPROM. See the Memory section
for more details.
Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 16-byte
EEPROM block containing address XX. Copy Data commands that address locked blocks are ignored.
While the Copy Data command is executing, the EEC bit in the EEPROM Register is set to 1 and writes
to EEPROM addresses are ignored. Reads and writes to non-EEPROM addresses can still occur while
the copy is in progress. The Copy Data command takes tEEC time to execute, starting on the next falling
edge after the address is transmitted.
Recall Data [B8h, XX]. This command recalls the contents of the 16-byte EEPROM block containing
address XX to shadow RAM.
Lock [6 Ah, XX]. This command locks (write-protects) the 16-byte block of EEPROM memory
containing memory address XX. The LOCK bit in the EEPROM Register must be set to l before the
Lock command is executed. If the LOCK bit is 0, the Lock command has no effect. The Lock command
is permanent; a locked block can never be written again.
17
DS2760
FUNCTION COMMANDS Table 4
Command
Bus State After
Command
Read Data
Write Data
Copy Data
Description
Protocol Command Protocol
Bus Data
Reads data from memory
starting at address XX
69h, XX
6Ch, XX
48h, XX
Master Rx
Master Tx
up to 256 bytes
of data
up to 256 bytes
of data
Writes data to memory
starting at address XX
Copies shadow RAM data
to EEPROM block
Bus Idle
Bus Idle
Bus Idle
none
none
none
containing address XX
Recalls EEPROM block
containing address XX to
shadow RAM
Recall Data
Lock
B8h, XX
6Ah, XX
Permanently locks the
block of EEPROM
containing address XX
18
DS2760
NET ADDRESS COMMAND FLOW CHART Figure 16
MASTER Tx
RESET PULSE
DS2760 Tx
PRESENCE PULSE
MASTER Tx
NET ADDRESS
COMMAND
33h / 39h
READ
NO
55h
NO
F0h
NO
AAh
NO
CCh
NO
MATCH
SEARCH
SWAP
SKIP
YES
YES
YES
YES
YES
MASTER Tx
BIT 0
MASTER Tx
BIT 0
MASTER Tx
FUNCTION
COMMAND
DS2760 Tx
FAMILY CODE
1 BYTE
DS2760 Tx BIT 0
DS2760 Tx BIT 0
MASTER Tx BIT 0
DS2760 Tx
SERIAL NUMBER
6 BYTES
BIT 0
NO
NO
BIT 0
NO
BIT 0
MATCH ?
MATCH ?
MATCH ?
DS2760 Tx
CRC
1 BYTE
YES
YES
YES
MASTER Tx
BIT 1
MASTER Tx
BIT 1
DS2760 Tx BIT 1
DS2760 Tx BIT 1
MASTER Tx BIT 1
BIT 1
NO
NO
BIT 1
NO
BIT 1
MATCH ?
MATCH ?
MATCH ?
YES
YES
YES
MASTER Tx
BIT 63
MASTER Tx
BIT 63
DS2760 Tx BIT 63
DS2760 Tx BIT 63
MASTER Tx BIT 63
MASTER Tx
FUNCTION
COMMAND
NO
YES
BIT 63
BIT 63
YES
MATCH ?
MATCH ?
NO
FALLING EDGE
OF DQ
RISING EDGE
OF DQ
DS2760 to Sleep
Mode
DS2760 to Active
Mode
19
DS2760
I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2760 are: the initialization sequence (Reset Pulse followed by Presence Pulse), Write 0, Write 1, and
Read Data. All of these types of signaling except the Presence Pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2760 is shown in Figure 17.
A Presence Pulse following a Reset Pulse indicates the DS2760 is read to accept a Net Address
Command. The bus master transmits (Tx) a Reset Pulse for tRSTL. The bus master then releases the line
and goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pull-up resistor. After
detecting the rising edge on the DQ pin, the DS2760 waits for tPDH and then transmits the Presence Pulse
for tPDL
.
1-WIRE INITIALIZATION SEQUENCE Figure 17
tRSTL
tRSTH
tPDH
tPDL
PACK+
PACK–
DQ
LINE TYPE LEGEND:
Both bus master and
DS2760 active low
WRITE TIME SLOTS
A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to
a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must
be tSLOT (60ꢀs to 120ꢀs) in duration with a 1ꢀs minimum recovery time, tREC, between cycles. The
DS2760 samples the 1-Wire bus line between 15ꢀs and 60ꢀs after the line falls. If the line is high when
sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 18). For the bus
master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15ꢀs after the start of the write time slot. For the host to generate a Write 0 time
slot, the bus line must be pulled low and held low for the duration of the write time slot.
READ TIME SLOTS
A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to a
logic low level. The bus master must keep the bus line low for at least 1ꢀs and then release it to allow the
DS2760 to present valid data. The bus master can then sample the data tRDV (15ꢀs) from the start of the
read time slot. By the end of the read time slot, the DS2760 releases the bus line and allows it to be
pulled high by the external pull-up resistor. All read time slots must be tSLOT (60ꢀs to 120ꢁs) in duration
with a 1ꢀs minimum recovery time, tREC, between cycles. See Figure 18 for more information.
20
DS2760
1-WIRE WRITE AND READ TIME SLOTS Figure 18
WRITE 0 SLOT
WRITE 1 SLOT
tSLOT
tSLOT
t
t
t
PACK+
PACK–
DQ
DS2760 Sample Window
DS2760 Sample Window
>1ꢀs
15ꢀs
15ꢀs
30ꢀs
15ꢀs
15ꢀs
30ꢀs
READ 0 SLOT
READ 1 SLOT
tSLOT
t
t
PACK+
PACK–
DQ
>1ꢀs
LINE TYPE LEGEND:
t
t
Both bus master and
DS2760 active low
SWAP COMMAND TIMING Figure 19
tSWL
DQ
tSWOFF
CC , DC
tSWON
CC , DC
21
DS2760
ABSOLUTE MAXIMUM RATINGS*
Voltage on PLS and CC pin, Relative to VSS
Voltage on PIO pin, Relative to VSS
-0.3V to +18V
-0.3V to +12V
Voltage on VIN and PS , Relative to VSS
Voltage on any other pin, Relative to VSS
Continuous Internal Sense Resistor Current
Pulsed Internal Sense Resistor Current
Operating Temperature Range
-0.3V to VDD + 0.3
-0.3V to +6V
M2.5A
M50A for <100µs/sec, <1000 pulses
-40°C to +85°C
Storage Temperature Range
-55°C to +125°C
Soldering Temperature
See IPC/JEDEC J-STD-020A
Specification
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC
OPERATING CONDITIONS
(-20LC to +70LC, 2.5V ? VDD ? 5.5V)
PARAMETER
Supply Voltage
Data Pin
SYMBOL
VDD
CONDITION
MIN
2.5
TYP MAX
UNITS
NOTES
5.5
5.5
V
V
1
1
DQ
-0.3
DC ELECTRICAL CHARACTERISTICS
(-20LC to +70LC; 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX UNITS NOTES
Active Current
IACTIVE
60
90
DQ = VDD,
norm. operation
DQ = 0V,
ꢀA
Sleep Mode Current
ISLEEP
1
2
ꢀA
no activity,
floating
PS
Input Logic High:
DQ, PIO
Input Logic High:
Input Logic Low:
DQ, PIO
Input Logic Low:
Output Logic High: CC
VIH
1.5
V
1
VIH
VIL
VDD - 0.2V
V
V
1
1
PS
PS
0.4
0.2
VIL
VOH
VOH
VOL
V
V
V
V
1
1
1
1
IOH = -0.1mA
IOH = -0.1mA
IOL = 0.1mA
VPLS - 0.4V
VDD - 0.4V
Output Logic High: DC
Output Logic Low:
0.4
0.4
CC , DC
Output Logic Low:
DQ, PIO
VOL
IOL = 4mA
V
1
DQ Pulldown Current
Input Resistance: VIN
Internal Current Sense
Resistor
IPD
RIN
RSNS
1
ꢀA
Mꢁ
mꢁ
5
20
25
30
+25LC
DQ Low to Sleep time
tSLEEP
2.1
sec
22
DS2760
ELECTRICAL CHARACTERISTICS:
PROTECTION CIRCUITRY
(0LC to +50LC; 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
MIN
4.325
4.250
4.10
2.5
1.8
45
TYP
4.350
4.275
4.15
2.6
MAX
4.375
4.300
4.20
2.7
UNITS
NOTES
Overvoltage Detect
VOV
V
1, 2
Charge Enable
VCE
VUV
IOC
V
V
1
1
Undervoltage Detect
Overcurrent Detect
Overcurrent Detect
Short Circuit Detect
Short Circuit Detect
Overvoltage Delay
Undervoltage Delay
Overcurrent Delay
Short Circuit Delay
Test Threshold
1.9
2.0
A
3
VOC
ISC
47.5
8.0
50
mV
1, 4
3
1
5.0
150
0.8
90
11
A
mV
sec
ms
ms
ꢀs
VSC
tOVD
tUVD
tOCD
tSCD
VTP
ITST
IRC
200
1
250
1.2
100
10
110
20
5
80
100
1.0
120
1.5
0.5
10
V
ꢀA
mA
Test Current
Recovery Charge Current
20
40
0.5
1
2
13
23
DS2760
ELECTRICAL CHARACTERISTICS:
TEMPERATURE, VOLTAGE, CURRENT
(0LC to +50LC; 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
TLSB
MIN
TYP
MAX
UNITS
LC
NOTES
Temperature Resolution
Temperature Full Scale
Magnitude
0.125
TFS
127
LC
Temperature Error
Voltage Resolution
Voltage Full Scale
Magnitude
Voltage Offset Error
Voltage Gain Error
TERR
VLSB
VFS
5
6
M3
LC
mV
V
4.88
4.75
1.9
VOERR
VGERR
1
5
LSB
%V
reading
mA
Current Resolution
ILSB
IFS
IOERR
0.625
15.625
2.56
3
ꢀV
4
Current Full Scale
Magnitude
Current Offset Error
Current Gain Error
A
3, 7
64
mV
4
1
3
1
LSB
%I
8
IGERR
3, 9, 14
reading
mAhr
µVhr
Hz
4
3
4
Accumulated Current
Resolution
qCA
fSAMP
tERR
0.25
6.25
1456
Current Sampling
Frequency
Internal Timebase Accuracy
%
10
M1
M3
24
DS2760
ELECTRICAL CHARACTERISTICS:
1-WIRE INTERFACE
(-20LC to +70LC; 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
tSLOT
tREC
MIN
60
1
TYP
MAX
UNITS
ꢀs
NOTES
Time Slot
120
Recovery Time
ꢀs
Write 0 Low Time
Write 1 Low Time
Read Data Valid
Reset Time High
Reset Time Low
Presence Detect High
Presence Detect Low
SWAP timing pulse width
SWAP timing pulse
tLOW0
tLOW1
tRDV
60
1
120
15
15
ꢀs
ꢀs
ꢀs
tRSTH
tRSTL
tPDH
480
480
15
60
0.2
0
ꢀs
960
60
240
120
1
ꢀs
ꢀs
tPDL
ꢀs
tSWL
ꢀs
tSWOFF
ꢀs
12
12
falling edge to DC release
SWAP timing pulse rising
tSWON
CDQ
0
1
ꢀs
edge to DC engage
DQ Capacitance
60
pF
EEPROM RELIABILITY SPECIFICATION
(-20LC to +70LC; 2.5V ? VDD ? 5.5V)
PARAMETER
SYMBOL
tEEC
MIN
TYP
MAX
UNITS
ms
NOTES
Copy to EEPROM Time
EEPROM Copy Endurance
2
10
NEEC
25000
cycles
11
NOTES
1) All voltages are referenced to VSS.
2) See “Ordering Information” section of datasheet to determine corresponding part number for each VOV value.
3) Internal current sense resistor configuration.
4) External current sense resistor configuration.
5) Self heating due to output pin loading and sense resistor power dissipation can alter the reading from ambient conditions.
6) Voltage offset measurement is with respect to VOV at +25°C.
7) The current register supports measurement magnitudes up to 2.56A using the internal sense resistor option and 64mV with
the external resistor option. Compensation of the internal sense resistor value for process and temperature variation can
reduce the maximum reportable magnitude to 1.9A.
8) Current offset error null to ±1LSB typically requires 3.5s in-system calibration by user.
9) Current gain error specification applies to gain error in converting the voltage difference at IS1 and IS2, and excludes any
error remaining after the DS2760 compensates for the internal sense resistor’s temperature coefficient of 3700ppm/LC to
an accuracy of M500ppm/LC. The DS2760 does not compensate for external sense resistor characteristics, and any error
terms arising from the use of an external sense resistor should be taken into account when calculating total current
measurement error.
10) Typical value for tERR is at 3.6V and +25LC.
11) 4-year data retention at +70LC.
12) Typical load capacitance on DC and CC is 1000pF.
13) Test conditions are PLS = 4.1V, VDD = 2.5V. Maximum current for conditions of PLS = 15V, VDD =0V is 10mA.
14) Error at time of shipment from Dallas Semiconductor is 3% max. Board mounting processes may cause the current gain
error to widen to as much as 10% for devices with the internal sense resistor option. Contact factory for on-board
recalibration procedure for devices with the internal sense resistor option to improve accuracy.
25
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