ICL3244ECB-T_技术文档

ICL3224E, ICL3226E, ICL3244E

®

Data Sheet

June 2003

FN4899.3

+/-15kV ESD Protected, +3V to +5.5V,

1Microamp, 250kbps, RS-232

Transceivers with Enhanced Automatic

Powerdown

Features

• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)

• Manual and Enhanced Automatic Powerdown Features

• Drop in Replacements for MAX3224E, MAX3226E,

MAX3244E

The Intersil ICL32XXE devices are 3.0V to 5.5V powered

RS-232 transmitters/receivers which meet ElA/TIA-232 and

V.28/V.24 specifications, even at V

= 3.0V. Additionally,

• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V

CC

they provide ±15kV ESD protection (IEC61000-4-2 Air Gap

and Human Body Model) on transmitter outputs and receiver

inputs (RS-232 pins). Targeted applications are PDAs,

Palmtops, and notebook and laptop computers where the

low operational, and even lower standby, power

• RS-232 Compatible with V

• Latch-Up Free

= 2.7V

CC

• On-Chip Voltage Converters Require Only Four External

0.1µF Capacitors

consumption is critical. Efficient on-chip charge pumps,

coupled with manual and enhanced automatic powerdown

functions, reduce the standby supply current to a 1µA trickle.

Small footprint packaging, and the use of small, low value

capacitors ensure board space savings as well. Data rates

greater than 250kbps are guaranteed at worst case load

conditions. This family is fully compatible with 3.3V only

systems, mixed 3.3V and 5.0V systems, and 5.0V only

systems.

• Guaranteed Mouse Driveability (ICL3244E)

• “Ready to Transmit” Indicator Output (ICL3224E/26E)

• Receiver Hysteresis For Improved Noise Immunity

• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps

• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/µs

• Wide Power Supply Range . . . . . . . Single +3V to +5.5V

• Low Supply Current in Powerdown State. . . . . . . . . . .1µA

The ICL3244E is a 3 driver, 5 receiver device that provides a

complete serial port suitable for laptop or notebook

computers. It also includes a noninverting always-active

receiver for “wake-up” capability.

Applications

• Any System Requiring RS-232 Communication Ports

- Battery Powered, Hand-Held, and Portable Equipment

- Laptop Computers, Notebooks, Palmtops

- Modems, Printers and other Peripherals

- Digital Cameras

These devices, feature an enhanced automatic

powerdown function which powers down the on-chip power-

supply and driver circuits. This occurs when all receiver and

transmitter inputs detect no signal transitions for a period of

30 seconds. These devices power back up, automatically,

whenever they sense a transition on any transmitter or

receiver input.

- Cellular/Mobile Phones

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

Table 1 summarizes the features of the devices represented

by this data sheet, while Application Note AN9863

summarizes the features of each device comprising the

ICL32XXE 3V family.

TABLE 1. SUMMARY OF FEATURES

ENHANCED

AUTOMATIC

POWERDOWN

FUNCTION?

NO. OF

MONITOR Rx.

DATA

RATE

(kbps)

MANUAL

POWER-

DOWN?

PART

NUMBER

NO. OF NO.OF

Rx. ENABLE

FUNCTION?

READY

OUTPUT?

Tx.

Rx.

(R

)

OUTB

ICL3224E

ICL3226E

ICL3244E

2

0

250

No

Yes

No

Yes

1

0

1

3

5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ICL3224E, ICL3226E, ICL3244E

Ordering Information

(NOTE 1)

PART NO.

TEMP.

RANGE ( C)

o

PACKAGE

20 Ld SSOP

20 Ld PDIP

16 Ld SSOP

28 Ld SSOP

28 Ld SOIC

28 Ld TSSOP

PKG. DWG. #

M20.209

E20.3

ICL3224ECA

ICL3224EIA

ICL3224ECP

ICL3226ECA

ICL3226EIA

ICL3244ECA

ICL3244EIA

ICL3244ECB

ICL3244EIB

ICL3244ECV

ICL3244EIV

NOTES:

0 to 70

-40 to 85

0 to 70

M16.209

M28.209

M28.3

-40 to 85

0 to 70

-40 to 85

0 to 70

-40 to 85

0 to 70

M28.3

M28.173

-40 to 85

1. Most surface mount devices are available on tape and reel; add

“-T” to suffix.

Pinouts

ICL3224E (PDIP, SSOP)

ICL3226E (SSOP)

TOP VIEW

READY

C1+

V+

1

2

3

4

5

6

7

8

16 FORCEOFF

15

READY

1

2

20 FORCEOFF

19

V

C1+

V+

V

CC

14 GND

13 T1

3

18 GND

17 T1

C1-

C2+

C2-

V-

4

OUT

C2+

C2-

12 FORCEON

5

16 R1

15 R1

IN

11 T1

IN

6

OUT

V-

10 INVALID

7

14 FORCEON

R1

IN

9 R1

OUT

T2

8

13 T1

IN

OUT

R2

9

12

T2

IN

11 INVALID

10

R2

OUT

ICL3244E (SOIC, SSOP, TSSOP)

TOP VIEW

C2+

C2-

V-

1

2

28 C1+

27 V+

3

26 V

CC

25 GND

R1

R2

R3

R4

R5

4

IN

5

24 C1-

6

23 FORCEON

22 FORCEOFF

21 INVALID

7

8

T1

9

20

R2

OUT

OUTB

OUT

10

11

12

13

14

19 R1

18 R2

17 R3

16 R4

15 R5

T2

T3

T2

T1

IN

2

ICL3224E, ICL3226E, ICL3244E

Pin Descriptions

FUNCTION

V

System power supply input (3.0V to 5.5V).

CC

V+

Internally generated positive transmitter supply (+5.5V).

Internally generated negative transmitter supply (-5.5V).

Ground connection.

V-

GND

C1+

C1-

External capacitor (voltage doubler) is connected to this lead.

External capacitor (voltage inverter) is connected to this lead.

TTL/CMOS compatible transmitter Inputs.

C2+

C2-

T

IN

T

±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.

±15kV ESD Protected, RS-232 compatible receiver inputs.

TTL/CMOS level receiver outputs.

OUT

R

IN

R

OUT

R

TTL/CMOS level, noninverting, always enabled receiver outputs.

Active low output that indicates if no valid RS-232 levels are present on any receiver input.

Active high output that indicates when the ICL32XXE is ready to transmit (i.e., V- ≤ -4V)

OUTB

INVALID

READY

FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).

FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).

Typical Operating Circuits

ICL3224E

+3.3V

+

0.1µF

19

2

C

0.1µF

C1+

V

3

1

CC

C

0.1µF

+

3

+

V+

V-

4

C1-

5

C

0.1µF

2

C2+

+

7

C

4

0.1µF

6

C2-

+

T

1

2

13

17

8

T1

T2

T1

T2

IN

OUT

12

15

IN

TTL/CMOS

RS-232

16

LOGIC LEVELS

LEVELS

R1

R2

R1

R2

OUT

IN

5kΩ

R

1

10

9

OUT

R

2

1

20

11

READY

V

FORCEOFF

INVALID

CC

14

TO POWER

CONTROL LOGIC

FORCEON

GND

18

3

ICL3224E, ICL3226E, ICL3244E

Typical Operating Circuits (Continued)

ICL3226E

15

+3.3V

+

0.1µF

2

C

3

7

C1+

1

V

C

0.1µF

CC

3

+

V+

V-

0.1µF

4

C1-

5

C

0.1µF

2

C2+

+

C

4

0.1µF

6

C2-

+

T

1

11

9

13

8

TTL/CMOS

LOGIC LEVELS

T1

OUT

T1

RS-232

LEVELS

IN

R1

IN

OUT

1

5kΩ

R

1

READY

16

10

V

CC

FORCEOFF

INVALID

12

TO POWER

CONTROL LOGIC

FORCEON

GND

14

ICL3244E

+3.3V

+

0.1µF

26

28

27

C

0.1µF

C1+

1

V

CC

C

0.1µF

+

3

+

V+

V-

24

C1-

1

C

0.1µF

2

C2+

3

9

C

4

2

C2-

0.1µF

+

T

1

2

3

14

T1

IN

OUT

13

12

10

11

RS-232

LEVELS

T2

T3

T2

T3

IN

OUT

20

19

R2

OUTB

TTL/CMOS

LOGIC LEVELS

4

5

R1

R2

OUT

IN

R

1

2

5kΩ

18

R2

OUT

IN

R

17

16

6

7

RS-232

LEVELS

R3

R4

R3

R4

OUT

IN

R

3

4

OUT

IN

5kΩ

15

23

8

R5

OUT

IN

R

5

FORCEON

22

21

V

CC

FORCEOFF

GND

TO POWER

CONTROL LOGIC

INVALID

25

4

ICL3224E, ICL3226E, ICL3244E

Absolute Maximum Ratings

Thermal Information

o

V

to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

Thermal Resistance (Typical, Note 2)

θ_JA( C/W)

CC

V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V

Input Voltages

20 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .

28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .

16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .

20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .

28 Ld SSOP and TSSOP Packages . . . . . . . . . . . .

Moisture Sensitivity (see Technical Brief TB363)

All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1

Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

80

75

140

125

100

T

, FORCEOFF, FORCEON . . . . . . . . . . . . . . . . . . -0.3V to 6V

IN

R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

IN

Output Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V

o

T

OUT

o

R

, INVALID, READY . . . . . . . . . . . . . . . . -0.3V to V +0.3V

OUT CC

o

Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

T

OUT

(SOIC, SSOP, TSSOP - Lead Tips Only)

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table

Operating Conditions

Temperature Range

ICL32XXEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

ICL32XXEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.

CC

1

4

o

Typicals are at T = 25 C

A

TEMP

o

PARAMETER

TEST CONDITIONS

( C)

MIN

TYP

MAX

UNITS

DC CHARACTERISTICS

Supply Current, Automatic

Powerdown

All R Open, FORCEON = GND, FORCEOFF = V

IN

25

-

1.0

10

µA

CC

Supply Current, Powerdown

FORCEOFF = GND

25

-

1.0

0.3

10

µA

Supply Current,

All Outputs Unloaded, FORCEON = FORCEOFF = V

1.0

mA

CC

Automatic Powerdown Disabled

LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS

Input Logic Threshold Low

Input Logic Threshold High

T

, FORCEON, FORCEOFF

Full

25

-

0.8

V

IN

, FORCEON, FORCEOFF

V

= 3.3V

= 5.0V

2.0

-

CC

2.4

V

Transmitter Input Hysteresis

Input Leakage Current

Output Leakage Current

Output Voltage Low

-

0.5

±0.01

±0.05

-

V

T

, FORCEON, FORCEOFF

Full

±1.0

±10

0.4

-

µA

V

IN

FORCEOFF = GND, ICL3244E Only

I

= 1.6mA

= -1.0mA

OUT

Output Voltage High

RECEIVER INPUTS

Input Voltage Range

Input Threshold Low

I

V

-0.6 V

-0.1

CC

V

CC

Full

25

-25

0.6

0.8

-

25

-

V

= 3.3V

= 5.0V

1.2

1.5

CC

25

-

5

ICL3224E, ICL3226E, ICL3244E

Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.

CC

1

4

o

Typicals are at T = 25 C (Continued)

A

TEMP

o

PARAMETER

TEST CONDITIONS

( C)

MIN

TYP

1.5

1.8

0.5

5

MAX

2.4

-

UNITS

Input Threshold High

V

= 3.3V

= 5.0V

25

-

V

CC

Input Hysteresis

-

V

Input Resistance

3

7

kΩ

TRANSMITTER OUTPUTS

Output Voltage Swing

Output Resistance

All Transmitter Outputs Loaded with 3kΩ to Ground

Full

±5.0

±5.4

10M

±35

-

V

Ω

V

= V+ = V- = 0V, Transmitter Output = ±2V

300

-

CC

Output Short-Circuit Current

Output Leakage Current

-

±60

±25

mA

µA

V

= ±12V, V

= 0V or 3V to 5.5V

CC

OUT

Automatic Powerdown or FORCEOFF = GND

MOUSE DRIVEABILITY (ICL3244E Only)

Transmitter Output Voltage

(See Figure 11)

T1 = T2 = GND, T3 = V , T3

Loaded with 3kΩ

Full

±5

-

V

IN

OUT

IN

CC

OUT

to GND, T1

and T2

Loaded with 2.5mA Each

OUT

ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF = V

)

CC

Receiver Input Thresholds to

INVALID High

See Figure 6

Full

25

-2.7

-0.3

-

2.7

0.3

0.4

-

V

Receiver Input Thresholds to

INVALID Low

See Figure 6

INVALID, READY Output Voltage

Low

I

= 1.6mA

= -1.0mA

-

V

OUT

INVALID, READY Output Voltage

High

V

-0.6

-

V

CC

Receiver Positive or Negative

-

1

-

µs

Threshold to INVALID High Delay

(t

INVH)

Receiver Positive or Negative

Threshold to INVALID Low Delay

25

-

30

-

µs

(t

INVL)

Receiver or Transmitter Edge to

Transmitters Enabled Delay (t

Note 3

25

100

30

-

µs

)

WU

Receiver or Transmitter Edge to

Transmitters Disabled Delay

Full

15

60

sec

(t

)

AUTOPWDN

TIMING CHARACTERISTICS

Maximum Data Rate

R

= 3kΩ, C = 1000pF, One Transmitter Switching

Full

25

250

500

0.15

200

100

-

kbps

µs

L

Receiver Propagation Delay

Receiver Input to Receiver

Output, C = 150pF

t

-

PHL

PLH

L

µs

Receiver Output Enable Time

Receiver Output Disable Time

Transmitter Skew

Normal Operation (ICL3244E Only)

ns

t

- t

PHL PLH

ns

6

ICL3224E, ICL3226E, ICL3244E

Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.

CC

1

4

o

Typicals are at T = 25 C (Continued)

A

TEMP

o

PARAMETER

Receiver Skew

TEST CONDITIONS

( C)

MIN

TYP

50

-

MAX

-

UNITS

ns

t

- t

PHL PLH

25

-

Transition Region Slew Rate

V

R

= 3.3V,

C = 150pF to 1000pF

6

4

30

V/µs

CC

L

= 3kΩ to 7kΩ,

L

C = 150pF to 2500pF

8

Measured From 3V to -3V or -3V

L

to 3V

ESD PERFORMANCE

RS-232 Pins (T

, R

)

Human Body Model

25

-

±15

±8

-

kV

OUT IN

IEC61000-4-2 Contact Discharge

IEC61000-4-2 Air Gap Discharge

Human Body Model

±15

±3

All Other Pins

NOTE:

3. An “edge” is defined as a transition through the transmitter or receiver input thresholds.

All devices guarantee a 250kbps data rate for full load

conditions (3kΩ and 1000pF), V ≥ 3.0V, with one

Detailed Description

CC

transmitter operating at full speed. Under more typical

conditions of V ≥ 3.3V, R = 3kΩ, and C = 250pF, one

These ICL32XXE interface ICs operate from a single +3V to

+5.5V supply, guarantee a 250kbps minimum data rate,

require only four small external 0.1µF capacitors, feature low

power consumption, and meet all ElA RS-232C and V.28

specifications. The circuit is divided into three sections: The

charge pump, the transmitters, and the receivers.

CC

L

transmitter easily operates at 1Mbps.

Transmitter inputs float if left unconnected, and may cause

increases. Connect unused inputs to GND for the best

I

CC

performance.

Charge-Pump

Receivers

Intersil’s new ICL32XXE family utilizes regulated on-chip

dual charge pumps as voltage doublers, and voltage

All the ICL32XXE devices contain standard inverting

receivers, but only the ICL3244E receivers can three-state,

via the FORCEOFF control line. Additionally, the ICL3244E

includes a noninverting (monitor) receiver (denoted by the

inverters to generate ±5.5V transmitter supplies from a V

CC

supply as low as 3.0V. This allows these devices to maintain

RS-232 compliant output levels over the ±10% tolerance

range of 3.3V powered systems. The efficient on-chip power

supplies require only four small, external 0.1µF capacitors

R

label) that is always active, regardless of the state of

OUTB

any control lines. Both receiver types convert RS-232

signals to CMOS output levels and accept inputs up to ±25V

while presenting the required 3kΩ to 7kΩ input impedance

for the voltage doubler and inverter functions at V

= 3.3V.

CC

See the “Capacitor Selection” section, and Table 3 for

capacitor recommendations for other operating conditions.

The charge pumps operate discontinuously (i.e., they turn off

as soon as the V+ and V- supplies are pumped up to the

nominal values), resulting in significant power savings.

(see Figure 1) even if the power is off (V

= 0V). The

CC

receivers’ Schmitt trigger input stage uses hysteresis to

increase noise immunity and decrease errors due to slow

input signal transitions.

V

Transmitters

CC

The transmitters are proprietary, low dropout, inverting

drivers that translate TTL/CMOS inputs to EIA/TIA-232

output levels. Coupled with the on-chip ±5.5V supplies,

these transmitters deliver true RS-232 levels over a wide

range of single supply system voltages.

R

XIN

XOUT

GND ≤ V

≤ V

-25V ≤ V

≤ +25V

5kΩ

ROUT

CC

RIN

GND

FIGURE 1. INVERTING RECEIVER CONNECTIONS

Transmitter outputs disable and assume a high impedance

state when the device enters the powerdown mode (see

Table 2). These outputs may be driven to ±12V when

disabled.

7

ICL3224E, ICL3226E, ICL3244E

The ICL3244E inverting receivers disable during forced

driving powered down peripherals must be disabled to

prevent current flow through the peripheral’s protection

diodes (see Figures 2 and 3). This renders them useless for

wake up functions, but the corresponding monitor receiver

can be dedicated to this task as shown in Figure 3.

(manual) powerdown, but not during automatic powerdown

(see Table 2). Conversely, the monitor receiver remains

active even during manual powerdown making it extremely

useful for Ring Indicator monitoring. Standard receivers

TABLE 2. POWERDOWN LOGIC TRUTH TABLE

RS-232

RCVR OR

LEVEL

XMTR

EDGE

PRESENT

AT

(NOTE 4)

WITHIN 30 FORCEOFF FORCEON TRANSMITTER RECEIVER

R

RECEIVER INVALID

OUTB

SEC?

INPUT

OUTPUTS

OUTPUTS OUTPUTS

INPUT?

OUTPUT

MODE OF OPERATION

ICL3224E, ICL3226E

NO

YES

NO

X

H

L

H

L

Active

High-Z

Active

N.A.

NO

YES

NO

L

H

L

Normal Operation (Enhanced

Auto Powerdown Disabled)

Normal Operation (Enhanced

Auto Powerdown Enabled)

L

YES

NO

H

L

Powerdown Due to Enhanced

Auto Powerdown Logic

L

YES

NO

H

L

X

Manual Powerdown

X

L

YES

H

ICL322XE - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)

X

NOTE 5

Active

N.A.

YES

NO

H

L

Normal Operation

High-Z

Forced Auto Powerdown

ICL3244E

NO

H

L

H

L

Active

High-Z

Active

High-Z

Active

NO

YES

NO

L

H

L

Normal Operation (Enhanced

Auto Powerdown Disabled)

NO

YES

NO

Normal Operation (Enhanced

Auto Powerdown Enabled)

L

YES

NO

H

L

Powerdown Due to Enhanced

Auto Powerdown Logic

NO

L

YES

NO

H

L

X

Manual Powerdown

X

L

YES

H

ICL3244E - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)

X

NOTE 5

Active

YES

NO

H

L

Normal Operation

High-Z

Forced Auto Powerdown

NOTES:

4. Applies only to the ICL3244E.

5. Input is connected to INVALID Output.

8

ICL3224E, ICL3226E, ICL3244E

active and powerdown modes, under logic or software

V

CC

V

CC

control, only the FORCEOFF input need be driven. The

FORCEON state isn’t critical, as FORCEOFF dominates

over FORCEON. Nevertheless, if strictly manual control over

powerdown is desired, the user must strap FORCEON high

to disable the enhanced automatic powerdown circuitry.

ICL3244E inverting (standard) receiver outputs also disable

when the device is in powerdown, thereby eliminating the

possible current path through a shutdown peripheral’s input

protection diode (see Figures 2 and 3).

CURRENT

FLOW

V

CC

V

= V

CC

OUT

Rx

POWERED

DOWN

UART

Tx

OLD

RS-232 CHIP

Connecting FORCEOFF and FORCEON together disables

the enhanced automatic powerdown feature, enabling them

to function as a manual SHUTDOWN input (see Figure 4).

SHDN = GND

GND

FORCEOFF

PWR

FIGURE 2. POWER DRAIN THROUGH POWERED DOWN

PERIPHERAL

FORCEON

MGT

LOGIC

V

INVALID

CC

ICL32XXE

TRANSITION

DETECTOR

TO

WAKE-UP

LOGIC

ICL3244E

I/O

UART

V

R2

CC

OUTB

CPU

R

V

= HI-Z

X

OUT

R2

OUT

R2

IN

POWERED

DOWN

UART

T

T1

X

IN

FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN

WHEN NO VALID RECEIVER SIGNALS ARE

PRESENT

T1

OUT

FORCEOFF = GND

With any of the above control schemes, the time required to

FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN

exit powerdown, and resume transmission is only 100µs.

Powerdown Functionality

When using both manual and enhanced automatic

powerdown (FORCEON = 0), the ICL32XXE won’t power up

from manual powerdown until both FORCEOFF and

FORCEON are driven high, or until a transition occurs on a

receiver or transmitter input. Figure 5 illustrates a circuit for

ensuring that the ICL32XXE powers up as soon as

FORCEOFF switches high. The rising edge of the Master

Powerdown signal forces the device to power up, and the

ICL32XXE returns to enhanced automatic powerdown mode

an RC time constant after this rising edge. The time constant

isn’t critical, because the ICL32XXE remains powered up for

30 seconds after the FORCEON falling edge, even if there

are no signal transitions. This gives slow-to-wake systems

(e.g., a mouse) plenty of time to start transmitting, and as

long as it starts transmitting within 30 seconds both systems

remain enabled.

This 3V family of RS-232 interface devices requires a

nominal supply current of 0.3mA during normal operation

(not in powerdown mode). This is considerably less than the

5mA to 11mA current required of 5V RS-232 devices. The

already low current requirement drops significantly when the

device enters powerdown mode. In powerdown, supply

current drops to 1µA, because the on-chip charge pump

turns off (V+ collapses to V , V- collapses to GND), and

CC

the transmitter outputs three-state. Inverting receiver outputs

may or may not disable in powerdown; refer to Table 2 for

details. This micro-power mode makes these devices ideal

for battery powered and portable applications.

Software Controlled (Manual) Powerdown

These devices allow the user to force the IC into the low

power, standby state, and utilize a two pin approach where

the FORCEON and FORCEOFF inputs determine the IC’s

mode. For always enabled operation, FORCEON and

FORCEOFF are both strapped high. To switch between

9

ICL3224E, ICL3226E, ICL3244E

whenever it detects a transition on one of these inputs. This

MASTER POWERDOWN LINE

automatic powerdown feature provides additional system

power savings without changes to the existing operating

system.

POWER

MANAGEMENT

UNIT

0.1µF

1MΩ

Enhanced automatic powerdown operates when the

FORCEON input is low, and the FORCEOFF input is high.

Tying FORCEON high disables automatic powerdown, but

manual powerdown is always available via the overriding

FORCEOFF input. Table 2 summarizes the enhanced

automatic powerdown functionality.

FORCEOFF

FORCEON

ICL32XXE

FIGURE 5. CIRCUIT TO ENSURE IMMEDIATE POWER UP

WHEN EXITING FORCED POWERDOWN

Figure 7 illustrates the enhanced powerdown control logic.

Note that once the ICL32XXE enters powerdown (manually

or automatically), the 30 second timer remains timed out

(set), keeping the ICL32XXE powered down until FORCEON

transitions high, or until a transition occurs on a receiver or

transmitter input.

INVALID Output

The INVALID output always indicates (see Table 2) whether

or not 30µs have elapsed with invalid RS-232 signals (see

Figures 6 and 8) persisting on all of the receiver inputs,

giving the user an easy way to determine when the interface

block should power down. Invalid receiver levels occur

whenever the driving peripheral’s outputs are shut off

(powered down) or when the RS-232 interface cable is

disconnected. In the case of a disconnected interface cable

where all the receiver inputs are floating (but pulled to GND

by the internal receiver pull down resistors), the INVALID

logic detects the invalid levels and drives the output low. The

power management logic then uses this indicator to power

down the interface block. Reconnecting the cable restores

valid levels at the receiver inputs, INVALID switches high,

and the power management logic wakes up the interface

block. INVALID can also be used to indicate the DTR or

RING INDICATOR signal, as long as the other receiver

inputs are floating, or driven to GND (as in the case of a

powered down driver).

FORCEOFF

EDGE

T_IN

DETECT

S

30s

AUTOSHDN

TIMER

R

EDGE

DETECT

R_IN

FORCEON

FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC

The INVALID output signal switches low to indicate that

invalid levels have persisted on all of the receiver inputs for

more than 30µs (see Figure 8), but this has no direct effect

on the state of the ICL32XXE (see the next sections for

methods of utilizing INVALID to power down the device).

INVALID switches high 1µs after detecting a valid RS-232

level on a receiver input. INVALID operates in all modes

(forced or automatic powerdown, or forced on), so it is also

useful for systems employing manual powerdown circuitry.

VALID RS-232 LEVEL - INVALID = 1

2.7V

INDETERMINATE

0.3V

INVALID LEVEL - INVALID = 0

-0.3V

The time to recover from automatic powerdown mode is

typically 100µs.

INDETERMINATE

Emulating Standard Automatic Powerdown

-2.7V

VALID RS-232 LEVEL - INVALID = 1

If enhanced automatic powerdown isn’t desired, the user can

implement the standard automatic powerdown feature

(mimics the function on the ICL3221E/23E/43E) by

FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS

connecting the INVALID output to the FORCEON and

FORCEOFF inputs, as shown in Figure 9. After 30µs of

invalid receiver levels, INVALID switches low and drives the

ICL32XXE into a forced powerdown condition. INVALID

switches high as soon as a receiver input senses a valid

RS-232 level, forcing the ICL32XXE to power on. See the

“INVALID DRIVING FORCEON AND FORCEOFF” section

of Table 2 for an operational summary. This operational

mode is perfect for handheld devices that communicate with

Enhanced Automatic Powerdown

Even greater power savings is available by using these

devices which feature an enhanced automatic powerdown

function. When the enhanced powerdown logic determines

that no transitions have occurred on any of the transmitter

nor receiver inputs for 30 seconds, the charge pump and

transmitters powerdown, thereby reducing supply current to

1µA. The ICL32XXE automatically powers back up

10

ICL3224E, ICL3226E, ICL3244E

RECEIVER

INPUTS

INVALID

REGION

}

TRANSMITTER

INPUTS

TRANSMITTER

OUTPUTS

t

INVH

INVALID

OUTPUT

t

INVL

t

AUTOPWDN

t

WU

t

WU

t

AUTOPWDN

READY

OUTPUT

V+

V

CC

0

V-

FIGURE 8. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS

another computer via a detachable cable. Detaching the

cable allows the internal receiver pull-down resistors to pull

the inputs to GND (an invalid RS-232 level), causing the

30µs timer to time-out and drive the IC into powerdown.

Reconnecting the cable restores valid levels, causing the IC

to power back up.

ICL32XXE

Hybrid Automatic Powerdown Options

For devices which communicate only through a detachable

cable, connecting INVALID to FORCEOFF (with

I/O

UART

CPU

FORCEON = 0) may be a desirable configuration. While the

cable is attached INVALID and FORCEOFF remain high, so

the enhanced automatic powerdown logic powers down the

RS-232 device whenever there is 30 seconds of inactivity on

the receiver and transmitter inputs. Detaching the cable

allows the receiver inputs to drop to an invalid level (GND),

so INVALID switches low and forces the RS-232 device to

power down. The ICL32XXE remains powered down until

the cable is reconnected (INVALID = FORCEOFF = 1) and a

transition occurs on a receiver or transmitter input (see

Figure 7). For immediate power up when the cable is

reattached, connect FORCEON to FORCEOFF through a

network similar to that shown in Figure 5.

FIGURE 9. CONNECTIONS FOR AUTOMATIC POWERDOWN

WHEN NO VALID RECEIVER SIGNALS ARE

PRESENT

Ready Output (ICL3224E and ICL3226E only)

The Ready output indicates that the ICL322XE is ready to

transmit. Ready switches low whenever the device enters

powerdown, and switches back high during power-up when

V- reaches -4V or lower.

Capacitor Selection

The charge pumps require 0.1µF capacitors for 3.3V

operation. For other supply voltages refer to Table 3 for

capacitor values. Do not use values smaller than those listed

in Table 3. Increasing the capacitor values (by a factor of 2)

reduces ripple on the transmitter outputs and slightly

reduces power consumption. C , C , and C can be

2

3

4

increased without increasing C ’s value, however, do not

1

increase C without also increasing C , C , and C to

1

2

3

4

maintain the proper ratios (C to the other capacitors).

1

11

ICL3224E, ICL3226E, ICL3244E

When using minimum required capacitor values, make sure

Mouse Driveability

that capacitor values do not degrade excessively with

temperature. If in doubt, use capacitors with a larger nominal

value. The capacitor’s equivalent series resistance (ESR)

usually rises at low temperatures and it influences the

amount of ripple on V+ and V-.

The ICL3244E is specifically designed to power a serial

mouse while operating from low voltage supplies. Figure 11

shows the transmitter output voltages under increasing load

current. The on-chip switching regulator ensures the

transmitters will supply at least ±5V during worst case

conditions (15mA for paralleled V+ transmitters, 7.3mA for

single V- transmitter).

TABLE 3. REQUIRED CAPACITOR VALUES

V

C

C , C , C

CC

1

2

3

4

6

5

(V)

(µF)

3.0 to 3.6

4.5 to 5.5

3.0 to 5.5

0.1

V

+

OUT

4

3

0.047

0.1

0.33

0.47

V

= 3.0V

CC

2

1

T1

0

Power Supply Decoupling

V

+

OUT

-1

-2

-3

-4

-5

-6

In most circumstances a 0.1µF bypass capacitor is

adequate. In applications that are particularly sensitive to

power supply noise, decouple V to ground with a

T2

T3

ICL3244E

V

-

CC

OUT

V

-

OUT

8

capacitor of the same value as the charge-pump capacitor C .

Connect the bypass capacitor as close as possible to the IC.

1

0

1

2

3

4

5

6

7

9

10

Operation Down to 2.7V

LOAD CURRENT PER TRANSMITTER (mA)

ICL32XXE transmitter outputs meet RS-562 levels (±3.7V),

FIGURE 11. TRANSMITTER OUTPUT VOLTAGE vs LOAD

CURRENT (PER TRANSMITTER, i.e., DOUBLE

CURRENT AXIS FOR TOTAL V CURRENT)

at full data rate, with V

as low as 2.7V. RS-562 levels

CC

OUT+

typically ensure inter operability with RS-232 devices.

High Data Rates

Transmitter Outputs when Exiting

Powerdown

The ICL32XXE maintain the RS-232 ±5V minimum

transmitter output voltages even at high data rates. Figure

12 details a transmitter loopback test circuit, and Figure 13

illustrates the loopback test result at 120kbps. For this test,

all transmitters were simultaneously driving RS-232 loads in

parallel with 1000pF, at 120kbps. Figure 14 shows the

loopback results for a single transmitter driving 1000pF and

an RS-232 load at 250kbps. The static transmitters were

also loaded with an RS-232 receiver.

Figure 10 shows the response of two transmitter outputs

when exiting powerdown mode. As they activate, the two

transmitter outputs properly go to opposite RS-232 levels,

with no glitching, ringing, nor undesirable transients. Each

transmitter is loaded with 3kΩ in parallel with 2500pF. Note

that the transmitters enable only when the magnitude of the

supplies exceed approximately 3V.

V

CC

+

5V/DIV.

0.1µF

FORCEOFF

T1

V

CC

V+

V-

+

C1+

C1-

C2+

C2-

+

C

1

2

V

= +3.3V

C

CC

3

4

C1 - C4 = 0.1µF

ICL32XXE

2V/DIV.

+

C

+

C

T

T2

IN

OUT

1000pF

R

IN

R

OUT

5V/DIV.

READY

TIME (20µs/DIV.)

FORCEON

5K

FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING

POWERDOWN

V

FORCEOFF

CC

FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT

12

ICL3224E, ICL3226E, ICL3244E

±15kV ESD Protection

5V/DIV.

T1

All pins on ICL32XX devices include ESD protection

structures, but the ICL32XXE family incorporates advanced

structures which allow the RS-232 pins (transmitter outputs

and receiver inputs) to survive ESD events up to ±15kV. The

RS-232 pins are particularly vulnerable to ESD damage

because they typically connect to an exposed port on the

exterior of the finished product. Simply touching the port

pins, or connecting a cable, can cause an ESD event that

might destroy unprotected ICs. These new ESD structures

protect the device whether or not it is powered up, protect

without allowing any latchup mechanism to activate, and

don’t interfere with RS-232 signals as large as ±25V.

IN

T1

OUT

R1

V

= +3.3V

CC

C1 - C4 = 0.1µF

5µs/DIV.

Human Body Model (HBM) Testing

FIGURE 13. LOOPBACK TEST AT 120kbps

As the name implies, this test method emulates the ESD

event delivered to an IC during human handling. The tester

delivers the charge through a 1.5kΩ current limiting resistor,

making the test less severe than the IEC61000 test which

utilizes a 330Ω limiting resistor. The HBM method

5V/DIV.

T1

IN

determines an ICs ability to withstand the ESD transients

typically present during handling and manufacturing. Due to

the random nature of these events, each pin is tested with

respect to all other pins. The RS-232 pins on “E” family

devices can withstand HBM ESD events to ±15kV.

T1

OUT

IEC61000-4-2 Testing

The IEC 61000 test method applies to finished equipment,

rather than to an individual IC. Therefore, the pins most likely to

suffer an ESD event are those that are exposed to the outside

world (the RS-232 pins in this case), and the IC is tested in its

typical application configuration (power applied) rather than

testing each pin-to-pin combination. The lower current limiting

resistor coupled with the larger charge storage capacitor yields

a test that is much more severe than the HBM test. The extra

ESD protection built into this device’s RS-232 pins allows the

design of equipment meeting level 4 criteria without the need

for additional board level protection on the RS-232 port.

R1

OUT

V

= +3.3V

CC

C1 - C4 = 0.1µF

2µs/DIV.

FIGURE 14. LOOPBACK TEST AT 250kbps

Interconnection with 3V and 5V Logic

The ICL32XXE directly interfaces with 5V CMOS and TTL

logic families. Nevertheless, with the ICL32XX at 3.3V, and

the logic supply at 5V, AC, HC, and CD4000 outputs can

drive ICL32XX inputs, but ICL32XX outputs do not reach the

AIR-GAP DISCHARGE TEST METHOD

minimum V for these logic families. See Table 4 for more

information.

IH

For this test method, a charged probe tip moves toward the IC

pin until the voltage arcs to it. The current waveform delivered

to the IC pin depends on approach speed, humidity,

temperature, etc., so it is difficult to obtain repeatable results.

The “E” device RS-232 pins withstand ±15kV air-gap

discharges.

TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS

SUPPLY VOLTAGES

SYSTEM

V

CC

POWER-SUPPLY SUPPLY

VOLTAGE

(V)

VOLTAGE

(V)

CONTACT DISCHARGE TEST METHOD

COMPATIBILITY

During the contact discharge test, the probe contacts the

tested pin before the probe tip is energized, thereby

eliminating the variables associated with the air-gap

discharge. The result is a more repeatable and predictable

test, but equipment limits prevent testing devices at voltages

higher than ±8kV. All “E” family devices survive ±8kV contact

discharges on the RS-232 pins.

3.3

Compatible with all CMOS

families.

5

Compatible with all TTL and

CMOS logic families.

5

3.3

Compatible with ACT and HCT

CMOS, and with TTL. ICL32XX

outputs are incompatible with AC,

HC, and CD4000 CMOS inputs.

13

ICL3224E, ICL3226E, ICL3244E

o

Typical Performance Curves V = 3.3V, T = 25 C

CC

A

6

25

20

V

+

OUT

4

2

-SLEW

1 TRANSMITTER AT 250kbps

OTHER TRANSMITTERS AT 30kbps

0

15

10

5

+SLEW

-2

-4

V

-

OUT

-6

0

1000

2000

3000

4000

5000

0

1000

2000

3000

4000

5000

LOAD CAPACITANCE (pF)

FIGURE 15. TRANSMITTER OUTPUT VOLTAGE vs LOAD

CAPACITANCE

FIGURE 16. SLEW RATE vs LOAD CAPACITANCE

35

40

ICL3226E

ICL3224E

35

30

25

20

250kbps

30

25

120kbps

15

10

20

15

20kbps

4000

20kbps

5

0

10

5

0

1000

2000

3000

5000

0

1000

2000

3000

4000

5000

LOAD CAPACITANCE (pF)

FIGURE 18. SUPPLY CURRENT vs LOAD CAPACITANCE

WHEN TRANSMITTING DATA

FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE

WHEN TRANSMITTING DATA

3.5

45

NO LOAD

ALL OUTPUTS STATIC

ICL3244E

40

3.0

250kbps

35

2.5

2.0

1.5

1.0

0.5

0

30

120kbps

25

20

20kbps

15

10

4000

5000

2000

3000

1000

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

LOAD CAPACITANCE (pF)

SUPPLY VOLTAGE (V)

FIGURE 20. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 19. SUPPLY CURRENT vs LOAD CAPACITANCE

WHEN TRANSMITTING DATA

14

ICL3224E, ICL3226E, ICL3244E

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP)

GND

TRANSISTOR COUNT

ICL3224E: 937

ICL3226E: 825

ICL3244E: 1109

PROCESS

Si Gate CMOS

15

ICL3224E, ICL3226E, ICL3244E

Shrink Small Outline Plastic Packages (SSOP)

M20.209 (JEDEC MO-150-AE ISSUE B)

N

20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

M

B

0.25(0.010)

H

INCHES

MIN

MILLIMETERS

E

GAUGE

PLANE

SYMBOL

MAX

0.078

0.008’

0.070’

0.015

0.008

0.289

0.212

MIN

1.73

0.05

1.68

0.25

0.09

7.07

5.20’

MAX

1.99

0.21

1.78

0.38

0.20’

7.33

5.38

NOTES

-B-

A

A1

A2

B

0.068

0.002

0.066

0.010’

0.004

0.278

0.205

1

2

3

L

0.25

0.010

SEATING PLANE

A

9

-A-

C

D

E

D

3

4

-C-

α

e

0.026 BSC

0.65 BSC

A2

e

A1

C

H

L

0.301

0.025

0.311

0.037

7.65

0.63

7.90’

0.95

B

0.10(0.004)

6

7

M

S

B

0.25(0.010)

C

A

N

α

20

0 deg.

8 deg.

0 deg.

8 deg.

NOTES:

Rev. 3 11/02

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.20mm (0.0078 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.20mm (0.0078

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.13mm (0.005 inch) total in excess

of “B” dimension at maximum material condition.

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

16

ICL3224E, ICL3226E, ICL3244E

Dual-In-Line Plastic Packages (PDIP)

E20.3 (JEDEC MS-001-AD ISSUE D)

N

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1

INDEX

AREA

INCHES

MILLIMETERS

1

2

3

N/2

SYMBOL

MIN

MAX

0.210

-

MIN

-

MAX

5.33

-

NOTES

-B-

A

A1

A2

B

-

4

-A-

0.015

0.115

0.014

0.045

0.008

0.980

0.005

0.300

0.240

0.39

2.93

0.356

1.55

0.204

24.89

0.13

7.62

6.10

4

D

E

BASE

PLANE

0.195

0.022

0.070

0.014

1.060

-

4.95

0.558

1.77

0.355

26.9

-

A2

A

-C-

-

SEATING

PLANE

L

C

L

B1

C

8

D1

B1

-

e_A

A1

A

D1

e

D

5

e_C

C

B

e_B

D1

E

5

0.010 (0.25) M

C

B S

0.325

0.280

8.25

7.11

6

E1

e

5

NOTES:

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

-

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

e

6

A

B

-

0.430

0.150

-

10.92

3.81

7

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

L

0.115

2.93

4

9

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication No. 95.

N

20

4. Dimensions A, A1 and L are measured with the package seated in

Rev. 0 12/93

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

e

6. E and

dicular to datum

7. e and e are measured at the lead tips with the leads uncon-

are measured with the leads constrained to be perpen-

A

-C-

.

B

C

strained. e must be zero or greater.

C

8. B1 maximum dimensions do not include dambar protrusions. Dam-

bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

17

ICL3224E, ICL3226E, ICL3244E

Small Outline Plastic Packages (SSOP)

M16.209 (JEDEC MO-150-AC ISSUE B)

N

16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

GAUGE

PLANE

SYMBOL

MIN

MAX

0.078

-

MIN

-

MAX

2.00

-

NOTES

-B-

A

A1

A2

B

-

0.002

0.065

0.009

0.004

0.233

0.197

0.05

1.65

0.22

0.09

5.90

5.00

1

2

3

0.072

0.014

0.009

0.255

0.220

1.85

0.38

0.25

6.50

5.60

-

L

0.25

0.010

SEATING PLANE

A

9

-

-A-

C

D

E

D

3

4

-

-C-

α

µ

e

0.026 BSC

0.65 BSC

A2

e

A1

C

H

L

0.292

0.022

0.322

0.037

7.40

0.55

8.20

0.95

-

B

0.10(0.004)

6

7

-

0.25(0.010) M

C A M B S

N

α

16

o

0

8

0

8

NOTES:

Rev. 2 3/95

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-

sion at maximum material condition.

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

18

ICL3224E, ICL3226E, ICL3244E

Shrink Small Outline Plastic Packages (SSOP)

M28.209 (JEDEC MO-150-AH ISSUE B)

N

28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

GAUGE

PLANE

SYMBOL

MIN

MAX

0.078

-

MIN

-

MAX

2.00

-

NOTES

-B-

A

A1

A2

B

-

0.002

0.065

0.009

0.004

0.390

0.197

0.05

1.65

0.22

0.09

9.90

5.00

-

1

2

3

0.072

0.014

0.009

0.413

0.220

1.85

0.38

0.25

10.50

5.60

-

L

0.25

0.010

SEATING PLANE

A

9

-A-

C

D

E

-

D

3

-C-

4

α

µ

e

0.026 BSC

0.65 BSC

-

A2

e

A1

C

H

L

0.292

0.022

0.322

0.037

7.40

0.55

8.20

0.95

-

B

0.10(0.004)

6

0.25(0.010) M

C A M B S

N

α

28

7

o

NOTES:

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

Rev. 1 3/95

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.20mm (0.0078 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.20mm (0.0078 inch)

per side.

5. The chamfer on the body is optional. If it is not present, a visual in-

dex feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dam-

bar protrusion shall be 0.13mm (0.005 inch) total in excess of “B”

dimension at maximum material condition.

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

19

ICL3224E, ICL3226E, ICL3244E

Small Outline Plastic Packages (SOIC)

M28.3 (JEDEC MS-013-AE ISSUE C)

N

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

0.30

0.51

0.32

18.10

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.0200

0.0125

-

1

2

3

L

9

SEATING PLANE

A

0.0091

0.6969

0.2914

-

0.7125 17.70

3

-A-

o

h x 45

D

0.2992

7.40

4

0.05 BSC

1.27 BSC

-

-C-

α

H

h

0.394

0.01

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

0.016

6

0.25(0.010) M

C

A M B S

N

α

28

7

o

0

8

0

8

-

NOTES:

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

20

ICL3224E, ICL3226E, ICL3244E

Thin Shrink Small Outline Plastic Packages (TSSOP)

M28.173

N

28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

INCHES

MIN

MILLIMETERS

GAUGE

PLANE

SYMBOL

MAX

0.047

0.006

0.051

0.0118

0.0079

0.386

0.177

MIN

-

MAX

1.20

0.15

1.05

0.30

0.20

9.80

4.50

NOTES

A

A1

A2

b

-

1

2

3

0.002

0.031

0.0075

0.0035

0.378

0.169

0.05

0.80

0.19

0.09

9.60

4.30

-

L

-

0.25

0.010

0.05(0.002)

SEATING PLANE

A

9

-A-

D

c

-

D

3

-C-

E1

e

4

α

A2

e

A1

0.026 BSC

0.65 BSC

-

c

b

0.10(0.004)

E

0.246

0.256

6.25

0.45

6.50

0.75

-

0.10(0.004) M

C

A M B S

L

0.0177

0.0295

6

N

28

7

o

NOTES:

0

8

0

8

-

α

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AE, Issue E.

Rev. 0 6/98

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

21


型号：	ICL3244ECB-T
厂家：	Rochester Electronics
描述：	TRIPLE LINE TRANSCEIVER, PDSO28, PLASTIC, MS-013-AE, SOIC-28 驱动光电二极管接口集成电路驱动器
文件：	总22页 (文件大小：1193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICL3244ECB-T [ROCHESTER]

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