ILC7082AIM547X [ROCHESTER]
4.7V FIXED POSITIVE LDO REGULATOR, 0.3V DROPOUT, PDSO5, PLASTIC, SOT-23, 5 PIN;
| 型号： | ILC7082AIM547X |
| 厂家： | 
Rochester Electronics |
| 描述： | 4.7V FIXED POSITIVE LDO REGULATOR, 0.3V DROPOUT, PDSO5, PLASTIC, SOT-23, 5 PIN 光电二极管 输出元件 调节器 |
| 文件： | 总17页 (文件大小：887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
ILC7082
150mA SOT-23 Low Noise CMOS RF-LDO™
Regulator
Features
Description
• Ultra low 1mV dropout per 1mA load
• 1% output voltage accuracy
• Only 40µVRMS noise
• Uses low ESR ceramic output capacitor to minimize noise
and output ripple
• Only 100µA ground current at 100mA load
• Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz
• Excellent line and load transient response
• Over current / over temperature protection
• Guaranteed to 150mA output current
• Industry standard five lead SOT-23 package
• Fixed 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V,
3.2V, 3.3V, 3.6V, 4.5V, 4.7V, 5.0V and adjustable output
voltage options
The ILC7082 is a 150mA low dropout (LDO) voltage regu-
lator designed to provide a high performance solution to
low power systems. The device offers a typical combination
of low dropout and low quiescent current expected of
CMOS parts, while uniquely providing the low noise and
high ripple rejection characteristics usually only associated
with bipolar LDO regulators.
The device has been optimized to meet the needs of modern
wireless communications design: low noise, low dropout,
small size, high peak current, high noise immunity.
The ILC7082 is designed to make use of low cost ceramic
capacitors while outperforming other devices that require
tantalum capacitors.
• Metal mask option available for custom voltages between
2.5V and 5.1V
Applications
• Cellular phones
• Wireless communicators
• PDAs / palmtops / organizers
• Battery powered portable electronics
Typical Applications
VOUT
5
1
4
SOT-23-5
ILC7082
2
COUT
CNOISE
3
VIN
ON
CIN
OFF
REV. 1.6.2 11/17/04
ILC7082
Pin Assignments
Adjustable Voltage Option
Fixed Voltage Option
GND
ON/OFF
VIN
1
8
CNOISE
N/C
GND
ON/OFF
VIN
1
8
VADJ
N/C
VOUT
5
CNOISE
4
VOUT
5
VADJ
4
2
3
7
6
2
3
7
6
ILC7082-xx
ILC7082ADJ
VOUT
VOUT
VOUT
VOUT
1
2
3
1
2
3
VIN
4
5
VIN
4
5
VIN GND
VIN GND
ON/OFF
ON/OFF
SOT-23-5
SOT-23-5
SOIC-8
SOIC-8
Pin Description ILC7082-xx (Fixed voltage version)
Pin Number
SOIC-8 SOT-23-5 Pin Name
Pin Description
3 and 4
1
2
3
4
VIN
Connect directly to supply.
Ground pin. Local ground for CNOISE and COUT
By applying less than 0.6V to this pin the device will be turned off.
1
2
8
GND
.
ON/OFF
CNOISE
Optional noise bypass capacitor may be connected between this pin and
GND. Do not connect CNOISE directly to the main power ground plane.
5 and 6
7
5
–
VOUT
N/C
Output voltage. Connect COUT between this pin and GND.
Not connected
Pin Description ILC7082-ADJ (Adjustable voltage version)
Pin Number
SOIC-8 SOT-23-5 Pin Name
Pin Description
3 and 4
1
2
3
4
VIN
GND
Connect directly to supply.
1
2
8
Ground pin. Local ground for CNOISE and COUT.
ON/OFF
VADJ
By applying less than 0.6V to this pin the device will be turned off.
Voltage feedback pin to set the adjustable output voltage. Do not connect a
capacitor to this pin.
5 and 6
7
5
–
VOUT
N/C
Output voltage. Connect COUT between this pin and GND.
Not connected
2
REV. 1.6.2 11/17/04
ILC7082
Internal Block Diagram
VIN
INTERNAL V
DD
CNOISE
BANDGAP
REFERENCE
TRANS-
CONDUCTANCE
AMPLIFIER
ERROR
AMPLIFIER
V
REFD
VOUT
FEEDBACK
GND
ON/OFF
Absolute Maximum Ratings
Parameter
Symbol
VIN
VON/OFF
Ratings
Units
-0.3 to +13.5
Input Voltage
V
-0.3 to V
On/Off Input Voltage
IN
Output Current
I
Short circuit protected
mA
V
OUT
Output Voltage
V
-0.3 to V +0.3
OUT
IN
Package Power Dissipation (SOT-23-5)
Maximum Junction Temp Range
Storage Temperature
PD
TJ(max)
TSTG
TA
250 (Internally Limited)
-40 to +150
-40 to +125
-40 to +85
mW
°C
°C
Operating Ambient Temperature
Package Thermal Resistance
°C
θJA
333
°C/W
Recommended Operating Conditions
Parameter
Min.
Typ.
Max.
13
Units
V
Input Voltage
Operating Ambient Temperature
VOUT+VDO
VOUT+1
–40
+85
°C
REV. 1.6.2 11/17/04
3
ILC7082
Electrical Characteristics ILC7082AIM5
Unless otherwise specified, all limits are at TA=25°C; VIN = V
OUT(NOM)
+1V, Ι
= 1mA, C
= 1µF, VON/OFF = 2V.
OUT
OUT
Boldface type denotes specifications which apply over the specified operating temperature range.
Parameter
Input Voltage Range
Symbol
Conditions
Min
2
Typ
Max Units
13
VIN
V
Output Voltage
VOUT
-1
VOUT(NOM)
VOUT(NOM)
+1 %VOUT
(NOTM)
1mA < IOUT < 150mA
1mA < IOUT < 150mA
-1
-2
+1
+2
Feedback Voltage
(ADJ version)
Line Regulation
VADJ
1.215
1.202
1.240
0.007
1.265
1.278
0.014 %/V
0.032
V
∆VOUT
(VOUT*∆VIN)
/
VOUT(NOM) +1V < VIN < 12V
IOUT= 0mA (Note 4)
Dropout Voltage
(Note 3)
VDO
0.1
10
1
2
25
35
mV
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
IOUT = 0mA
50
75
100
100
150
95
150
200
225
300
200
220
Ground Pin Current
IGND
µA
IOUT = 10mA
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
VON/OFF = 0V
100
100
100
115
0.1
220
240
220
240
240
260
260
280
2
Shutdown (OFF) Current
ON/OFF Input Voltage
ION/OFF
µA
V
VON/OFF
High = Regulator On
Low = Regulator Off
1.5
0.6
ON/OFF Pin Input
Current
IIN(ON/OFF) VON/OFF = 0.6V, regulator OFF
VON/OFF = 2V, regulator ON
0.3
1
µA
Peak Output Current
(Note 4)
IOUT(peak)
VOUT > 0.95VOUT(NOM)
tpw = 2ms
,
400
500
mA
Output Noise Voltage
(RMS)
eN
BW = 300Hz to 50kHz, CIN = 1µF
CNOISE = 0.01µF, COUT = 2.2µF,
IOUT = 10mA
40
µVRMS
Ripple Rejection
∆VOUT/∆VIN COUT = 4.7µF, Freq. = 1kHz
85
70
60
14
dB
IOUT = 100mA
Freq. = 10kHz
Freq. = 1MHz
Dynamic Line Regulation
∆VOUT(line) VIN: VOUT(NOM) + 1V to
OUT(NOM) + 2V,
tr, tf = 2µs; IOUT = 150mA
Dynamic Load Regulation ∆VOUT(load) IOUT: 1mA to 150mA; tr, tf = 10µS
mV
V
40
mV
mA
600
Short Circuit Current
VOUT = 0V
ISC
Notes:
1. Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical
specifications do not apply when operating the device outside of its rated operating conditions.
2. Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods.
Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing.
3. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal
value measured with an IV differential.
4. Guaranteed by design
4
REV. 1.6.2 11/17/04
ILC7082
A block diagram of the regulator circuit used in the ILC7082
is shown in Figure 2, which shows the input-to-output isola-
tion and the cascaded sequence of amplifiers that implement
the pole-zero scheme previously outlined.
Operation
The ILC7082 LDO design is based on an advanced circuit
configuration for which patent protection has been applied.
Typically it is very difficult to drive a capacitive output with
an amplifier. The output capacitance produces a pole in the
feedback path, which upsets the carefully tailored dominant
pole of the internal amplifier. Traditionally the pole of the
output capacitor has been “eliminated” by reducing the
output impedance of the regulator such that the pole of the
output capacitor is moved well beyond the gain bandwidth
product of the regulator. In practice, this is difficult to do and
still maintain high frequency operation. Typically the output
impedance of the regulator is not simply resistive, such that
the reactive output impedance interacts with the reactive
impedance of the load resistance and capacitance. In addi-
tion, it is necessary to place the dominant pole of the circuit
at a sufficiently low frequency such that the gain of the regu-
lator has fallen below unity before any of the complex inter-
actions between the output and the load occur. The ILC7082
does not try to eliminate the output pole, but incorporates it
into the stability scheme. The load and output capacitor
forms a pole, which rolls off the gain of the regulator below
unity. In order to do this the output impedance of the regula-
tor must be high, looking like a current source. The output
stage of the regulator becomes a transconductance amplifier,
which converts a voltage to a current with a substantial
output impedance. The circuit which drives the transconduc-
tance amplifier is the error amplifier, which compares the
regulator output to the band gap reference and produces an
error voltage as the input to the transconductance amplifier.
The error amplifier has a dominant pole at low frequency and
a “zero” which cancels out the effects of the pole. The zero
allows the regulator to have gain out to the frequency where
the output pole continues to reduce the gain to unity. The
configuration of the poles and zero are shown in Figure 1.
Instead of powering the critical circuits from the unregulated
input voltage, the CMOS RF LDO powers the internal
circuits such as the bandgap, the error amplifier and most of
the transconductance amplifier from the boot strapped regu-
lated output voltage of the regulator. This technique offers
extremely high ripple rejection and excellent line transient
response.
VIN
INTERNAL VDD
CNOISE
BANDGAP
REFERENCE
VREFD
TRANS-
CONDUCTANCE
AMPLIFIER
ERROR
AMPLIFIER
VOUT
FEEDBACK
GND
ON/OFF
Figure 2. ILC7082 RF LDO Regulator Block Diagram
The ILC7082 is designed in a CMOS process with some
minor additions, which allow the circuit to be used at
input voltages up to 13V. The resulting circuit exceeds the
frequency response of traditional bipolar circuits. The
ILC7082 is very tolerant of output load conditions with the
inclusion of both short circuit and thermal overload protec-
tion. The device has a very low dropout voltage, typically a
linear response of 1mV per 1mA of load current, and none of
the quasi-saturation characteristics of a bipolar output
devices. All the features of the frequency response and
regulation are valid right to the point where the regulator
goes out of regulation in a 4mV transition region. Because
there is no base drive, the regulator is capable of providing
high current surges while remaining in regulation. This is
shown in the high peak current of 500mA which allows for
the ILC7082 to be used in systems that require short burst
mode operation.
Shutdown (ON/OFF) Operation
The ILC7082 output can be turned off by applying 0.6V or
less to the device’s ON/OFF pin. In shutdown mode, the
ILC7082 draws less than 1mA quiescent current. The output
of the ILC7082 is enabled by applying 1.5V to 13V at the
ON/OFF pin. In applications were the ILC7082 output will
always remain enabled, the ON/OFF pin may be connected
to VIN. The ILC7082’s shutdown circuitry includes hystere-
sis, as such the device will operate properly even if a slow
moving signal is applied to the ON/OFF pin.
Dominant Pole
85 dB
Output Pole
Short Circuit Protection
Compensating
Zero
The ILC7082 output can withstand momentary short circuit
to ground. Moreover, the regulator can deliver very high
output peak current due to its 1A instantaneous short circuit
current capability.
Unity Gain
Frequency
Figure 1. ILC7082 RF LDO Frequency Response
REV. 1.6.2 11/17/04
5
ILC7082
Thermal Protection
Maximum Output Current
The ILC7082 also includes a thermal protection circuit
which shuts down the regulator when die temperature
exceeds 170˚C due to overheating. In thermal shutdown,
once the die temperature cools to below 160˚C, the regulator
is enabled. If the die temperature is excessive due to high
package power dissipation, the regulator’s thermal circuit
will continue to pulse the regulator on and off. This is called
thermal cycling.
The maximum output current available from the ILC7082 is
limited by the maximum package power dissipation as well
as the device’s internal current limit. For a given ambient
temperature, TA, the maximum package power dissipation is
given by:
PD(MAX) = (TJ(MAX) - TA) / θJA
where TJ(MAX) = 150˚C is the maximum junction tempera-
ture and qJA = 333˚C/W is the package thermal resistance.
For example at TA = 85˚C ambient temperature, the maxi-
mum package power dissipation is;
Excessively high die temperature may occur due to high dif-
ferential voltage across the regulator or high load current or
high ambient temperature or a combination of all three.
Thermal protection protects the regulator from such fault
conditions and is a necessary requirement in today’s designs.
In normal operation, the die temperature should be limited to
under 150˚C.
PD(MAX) = 195mW
The maximum output current can be calculated from the
following equation:
Adjustable Output Voltage
Figure 3 shows how an adjustable output voltage can be
easily achieved using ILC7082-ADJ. The output voltage,
IOUT(MAX) < PD(MAX) / (VIN - VOUT
)
For example at VIN = 6V, VOUT = 5V and TA = 85˚C, the
maximum output current is IOUT(MAX) < 195mA. At higher
output current, the die temperature will rise and cause the
thermal protection circuit to be enabled.
V
OUT is given by the following equation:
VOUT = 1.24V x (R1/R2 + 1)
R1
R2
Application Hints
VOUT
Figure 4 shows the typical application circuit for the
ILC7082.
VADJ
SOT23-5
5
1
4
3
ILC7083-ADJ
COUT
VIN
CIN
VOUT
SOT23-5
5
1
4
3
CNOISE
2
ILC7082
COUT
VIN
CIN
ON
OFF
2
ON
Figure 3. Application Circuit for
Adjustable Output Voltage
OFF
For best results, a resistor value of 470kΩ or less may be
used for R2. The output voltage can be programmed from
2.5V to 12V.
Figure 4. Basic Application Circuit for Fixed
Output Voltage Versions
Input Capacitor
Note: An external capacitor should not be connected to
the adjustable feedback pin (pin 4). Connecting an exter-
nal capacitor to pin 4 may cause regulator instability and
lead to unwanted oscillations.
An input capacitor CIN of value 1µF or larger should be con-
nected from VIN to the main ground plane. This will help to
filter supply noise from entering the LDO. The input capaci-
tor should be connected as close to the LDO regulator input
pin as is practical. Using a high-value input capacitor will
offer superior line transient response as well as better power
supply ripple rejection. A ceramic or tantalum capacitor may
be used at the input of the LDO regulator.
6
REV. 1.6.2 11/17/04
ILC7082
Note that there is a parasitic diode from the LDO regulator
output to the input. If the input voltage swings below the
regulator’s output voltage by 200mV then the regulator may
be damaged. This condition must be avoided. In many appli-
cations a large value input capacitor, CIN, will hold VIN
higher than VOUT and decay slower than VOUT when the
LDO is powered off.
In applications where a high output surge current can be
expected, use a high value but low ESR output capacitor for
superior load transient response. The ILC7082 is stable with
no load.
Noise Bypass Capacitor
In low noise applications, the ILC7082’s noise can be
decreased further by connecting a capacitor from the
noise bypass pin to ground. The noise bypass pin is a high
impedance node, and as such, care should be taken in printed
circuit board layout to avoid noise pick-up from external
sources. Moreover, the noise bypass capacitor should have
low leakage.
Output Capacitor Selection
Fairchild strongly recommends the use of low ESR (equiva-
lent series resistance) ceramic capacitors for COUT and
C
NOISE The ILC7082 is stable with low ESR capacitor (as
low as zero Ω). The value of the output capacitor should be
1µF or higher. Either a ceramic chip or a tantalum capacitor
may be used at the output.
Noise bypass capacitors with a value as low as 470pF may
be used. However, for optimum performance, use a 0.01µF
or larger, ceramic chip capacitor. Note that the turn on and
turn off response of the ILC7082 is inversely proportional to
the value of the noise bypass capacitor. For fast turn on and
turn off, use a small value noise bypass capacitor. In appli-
cations were exceptionally low output noise is not required,
consider omitting the noise bypass capacitor altogether.
Use of ceramic chip capacitors offer significant advantages
over tantalum capacitors. A ceramic capacitor is typically
cheaper than a tantalum capacitor, it usually has a smaller
footprint, lower height, and lighter weight than a tantalum
capacitor. Furthermore, unlike tantalum capacitors which are
polarized and can be damaged if connected incorrectly,
ceramic capacitors are non-polarized. Low value ceramic
chip capacitors with X5R or X7R dielectric are available in
the 100pF to 4.7µF range. Beware of using ceramic capaci-
tors with Y5V dielectric since their ESR increases signifi-
cantly at cold temperatures. Table 1 shows a list of
recommended ceramic capacitors for use at the output of
ILC7082.
The Effects of ESR (Equivalent Series
Resistance)
The ESR of a capacitor is a measure of the resistance due to
the leads and the internal connections of the component.
Typically measured in mΩ (milli-ohms) it can increase to
ohms in some cases.
Note: If a tantalum output capacitor is used then for stable
operation we recommend a low ESR tantalum capacitor with
maximum rated ESR at or below 0.4Ω. Low ESR tantalum
capacitors, such as the TPS series from AVX Corporation
(www.avxcorp.com) or the T495 series from Kemet
(www.kemet.com) may be used.
Wherever there is a combination of resistance and current,
voltages will be present. The control functions of LDOs use
two voltages in order to maintain the output precisely; VOUT
and VREF
.
Table 1. Recommended Ceramic Output Capacitors
COUT
Capacitor Size
0805
IOUT
Dielectric
X5R
Part Number
C2012X5R1A105KT
GRM40X7R105K010
LMK212BJ105KG
GRM42-6X7R105K016
EMK316BJ105KL
TMK316BJ105KL
Capacitor Vendor
TDK
1µF
0 to 150mA
0805
X7R
muRata
0805
X7R
Taiyo-Yuden
muRata
1206
X7R
1206
X7R
Taiyo-Yuden
Taiyo-Yuden
1206
X5R
2.2µF
4.7µF
0805
0805
1206
0 to 150mA
0 to 150mA
X5R
X5R
X5R
GRM40X5R225K 6.3
C2012X5R0J225KT
EMK316BJ225ML
muRata
TDK
Taiyo-Yuden
1206
1206
X5R
X7R
GRM42-6X5R475K010
LMK316BJ475ML
muRata
Taiyo-Yuden
REV. 1.6.2 11/17/04
7
ILC7082
With reference to the block diagram in Figure 2, VOUT is fed
back to the error amplifier and is used as the supply voltage
for the internal components of the ILC7082. So any change
in VOUT will cause the error amplifier to try to compensate to
maintain VOUT at the set level and noise on VOUT will be
reflected into the supply of each internal component of the
ILC7082. The reference voltage, VREF, is influenced by the
CNOISE pin. Noise into this pin will add to the reference
voltage and be fed through the circuit. These factors will not
cause a problem if some simple steps are taken. Figure 5
shows where these added ESR resistances are present in the
typical LDO circuit.
IOUT
VOUT
RPCB
ESR
RPCB
I1
COUT
SOT-23-5
5
1
4
3
CNOISE
ILC7082
VIN
CIN
2
RPCB
RPCB
ON
OFF
IOUT
VOUT
R*
Figure 6. Inherent PCB resistance
IC
RC
SOT-23-5
ILC7082
2
5
1
4
3
Figure 7 shows the effects of poor grounding and PCB lay-
out magnified by the ESR and PCB resistances and the accu-
mulation of current flows.
COUT
CNOISE
Note that particularly during high output load current, the
LDO regulator’s ground pin and the ground return for COUT
and CNOISE are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between COUT, CNOISE and the LDO regulator’s ground pin
will degrade performance of the LDO.
VIN
RF LDOTM
Regulator
ON
R*
CIN
OFF
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground
current and noise bypass current return of the LDO regulator.
Note that the key difference here is that COUT and CNOISE are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
Figure 5. ESR Present in COUT and CNOISE
With this in mind, low ESR components will offer better per-
formance where the LDO may be subjected to large load
transients current. ESR is less of a problem with CIN as the
voltage fluctuations at the input will be filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of sev-
eral currents can develop detectable voltage ripple and will
be amplified by the LDO. In particular, the accumulation of
current flows in the ground plane can develop significant
voltages unless care is taken. With a degree of care, the
ILC7082 will yield outstanding performance.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
Note, the ground plane is the bottom layer of the PCB and
connects to top layer ground connections through vias.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full
advantage of any high performance LDO regulator requires
careful attention to grounding and printed circuit board
(PCB) layout.
8
REV. 1.6.2 11/17/04
ILC7082
VOUT
5
1
4
ILC7082
SOT-23-5
COUT
2
3
V
IN
ON/OFF
GND2
CIN
ICOUT
GND1
GND3
GND4
ILOAD
GND5
ILOAD
ILOAD
ILOAD
True GND
(0V)
+ICOUT
+ICNOISE
+ICOUT
+ICOUT
+ICNOISE
+IGND
Figure 7. Effects of Poor Circuit Layout
VOUT
CNOISE
5
4
3
COUT
ILC7082
SOT-23-5
ESR<0.5
1
2
V
IN
ON/OFF
DC/DC
VBATT
Converter
CIN
+
GND
Ground Plane
Ground Plane
Ground Plane
Ground Plane
Figure 8. Recommended Application Circuit Schematic
Fairchild Semiconductor - Eval. Board
Figure 9. Recommended Application Circuit Layout
(not drawn to scale)
REV. 1.6.2 11/17/04
9
ILC7082
Table 2. Evaluation Board Parts List For Printed Circuit Board Shown in Figure 9
Label
U1
Part Number
ILC7082AIM5-30
69190-405
Manufacturer
Fairchild Semiconductor
Berg
Description
150mA RF LDO™ regulator
J1
Connector, four position header
Cin
GRM40 Y5V 105Z16
ECU-V1H103KBV
GRM42-6X7R105K016
muRata
Ceramic capacitor, 1µF, 16V, SMT ( size 0805 )
Ceramic capacitor, 0.01µF, 16V, SMT ( size 0603 )
Ceramic capacitor, 1µF, 16V, SMT ( size 1206)
Cnoise
Cout
Panasonic
muRata
Grounding Recommendations
1. Connect CIN between VIN of the ILC7082 and the “GROUND PLANE”.
2. Keep the ground side of COUT and CNOISE connected to the “LOCAL GROUND” and not directly to the “GROUND
PLANE”.
3. On multilayer boards use component side copper for grounding around the ILC7082 and connect back to a “GROUND
PLANE” using vias.
4. If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the
control signals. The star should radiate from where the power supply enters the PCB.
Layout Considerations
1. Place all RF LDO related components; ILC7082, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor
COUT as close together as possible.
2. Keep the output capacitor COUT as close to the ILC7082 as possible with very short traces to the VOUT and GND pins.
3. The traces for the related components; ILC7082, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor
COUT can be run with minimum trace widths close to the LDO.
4. Maintain a separate “LOCAL GROUND” remote from the “GROUND PLANE” to ensure a quiet ground near the LDO.
Figure 9 shows how this circuit can be translated into a PCB layout.
10
REV. 1.6.2 11/17/04
ILC7082
Typical Performance Characteristics ILC7082
Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Dropout Characteristics
Output Voltage vsTemperature
3.4
3.3
3.2
3.1
3.015
VOUT = 3.3V
COUT = 1µF (Ceramic)
VOUT = 3.0V
COUT = 1µF (Ceramic)
3.01
3.005
3
IOUT = 0mA
IOUT = 10mA
IOUT = 50mA
2.995
2.99
IOUT = 100mA
IOUT = 150mA
3
2.985
3
3.2
3.4
3.6
-50
0
50
Temperature (°C)
100
150
VIN (V)
Dropout Voltage vsTemperature
Dropout Voltage vs IOUT
250
200
250
200
IOUT = 150mA
VOUT = 3.0V
VOUT = 3.0V
TA = 85°C
TA = 25°C
IOUT = 100mA
IOUT = 50mA
150
100
50
150
100
50
TA = –40°C
IOUT = 0mA
0
0
–40
25
85
0
50
100
150
Temperature (°C)
Output Current (mA)
Line Transient Response
Ground Current vs Input Voltage
6
5
150
VIN: tr/tf < 1 µs
VOUT = 3.0V
COUT = 2.2 µF (Ceramic)
VOUT = 3.0 V
COUT = 1µF (Ceramic)
IOUT = 50mA
IOUT = 10mA
125
100
75
IOUT = 150mA
IOUT = 100 mA
IOUT = 0mA
4
3.01
3.00
2.99
2.98
IOUT = 100mA
50
2
4
6
8
10
12
14
5µs/div
VIN (V)
REV. 1.6.2 11/17/04
11
ILC7082
Typical Performance Characteristics ILC7082
Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Load Transient Response
VOUT = 3.0V
Short Circuit Current
3.15
3.10
Thermal Cycling
VIN = 4V
Output Shorted to Gnd
t = 0
COUT = 1 µF || 0.47 µF (Ceramic)
at time,
1.5
1.0
3.05
3.00
2.95
0.5
0
100
1
100µs/div
t = 0
5ms/div
On/Off Transient Response
On/Off Transient Response
VOUT = 2.8V
15
15
10
5
VOUT = 2.8V
IOUT = 10mA
IOUT = 150mA
10
5
Without CNOISE Capacitor
Without CNOISE Capacitor
COUT = 1µF
COUT = 1µF
0
0
3
3
2
2
1
1
0
0
100µS/div
100µS/div
On/Off Transient Response
VOUT = 2.8V
IOUT = 10mA
CNOISE = 0.01µF, COUT = 1µF
On/Off Transient Response
VOUT = 2.8V
IOUT = 150mA
CNOISE = 0.01µF, COUT = 1µF
15
15
10
5
10
5
0
0
3
3
2
2
1
1
0
0
5mS/div
5mS/div
12
REV. 1.6.2 11/17/04
ILC7082
Typical Performance Characteristics ILC7082
Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Spectral Noise Density
Spectral Noise Density
10
10
VOUT = 2.8V
VOUT = 2.8V
I
OUT = 50mA
COUT = 2.2µF
CNOISE = 0.01µF
CNOISE = 0.01µF
1
0.1
1
0.1
COUT = 1µF (Ceramic)
IOUT = 50mA, 100mA or 150 mA
COUT = 2.2µF or 4.7µF (Ceramic)
COUT = 10µF (Ceramic)
0.01
0.001
0.01
0.001
IOUT = 1 mA
10M
10
100
1K
10K
Frequency (Hz)
1M
100K
1M
10
100
1K
10K
100K
Frequency (Hz)
Output Noise Voltage vs. CNOISE
Output Noise Voltage vs. CNOISE
90
90
80
70
VOUT = 3V
IOUT = 10mA
COUT = 2.2µF(Ceramic)
CNOISE = 1.2nF
VOUT = 3V
80
70
CNOISE = 1.2nF
I
OUT = 10mA
COUT = 4.7µF(Ceramic)
5.6nF
8.2nF
60
50
40
30
60
50
40
30
5.6nF
8.2nF
0.039µF
0.047µF
0.039µF
0.047µF
0.022µF
0.01µF
0.022µF
0.016µF
20
10
0
20
10
0
100 Hz–
50 KHz
100 Hz–
100 KHz
300 Hz–
50 KHz
300 Hz–
100 KHz
100 Hz–
50 KHz
100 Hz–
100 KHz
300 Hz–
50 KHz
300 Hz–
100 KHz
Freq Band
Ripple Rejection vs. Frequency
Freq Band
Ripple Rejection vs. Frequency
80
70
60
50
40
30
120
VOUT = 2.8V
IOUT = 150mA
VOUT = 3V
OUT = 10mA
I
COUT = 2.2µF
100
80
60
40
20
0
COUT = 4.7µF
COUT = 4.7µF
COUT = 10µF
COUT = 10µF
COUT = 1µF
COUT = 1µF
20
COUT = 2.2µF
10
0
10M
10
100
1K
10K
Frequency (Hz)
1M
100K
10M
10
100
1K
10K
1M
100K
Frequency (Hz)
REV. 1.6.2 11/17/04
13
ILC7082
Mechanical Dimensions
8-Lead Plastic Surface Mount (SOIC)
Notes:
Inches
Millimeters
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
A
.053
.004
.013
.0075
.189
.150
.069
.010
.020
.010
.197
.158
1.35
0.10
0.33
0.20
4.80
3.81
1.75
0.25
0.51
0.25
5.00
4.01
A1
B
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
C
D
E
5
2
2
e
.050 BSC
1.27 BSC
H
h
.228
.010
.016
.244
.020
.050
5.79
0.25
0.40
6.20
0.50
1.27
L
3
6
N
α
8
8
0°
8°
0°
8°
ccc
—
.004
—
0.10
8
5
E
H
1
4
h x 45°
D
C
A1
A
α
SEATING
PLANE
– C –
L
e
LEAD COPLANARITY
ccc C
B
14
REV. 1.6.2 11/17/04
ILC7082
5-Lead Plastic Surface Mount (SOT-23-5)
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Package outline exclusive of mold flash & metal burr.
2. Package outline exclusive of solder plating.
3. EIAJ Ref Number SC-74A.
Min.
Max.
A
A1
B
c
.035
.000
.008
.003
.106
.059
.057
.006
.020
.010
.122
.071
.90
.00
1.45
.15
.20
.50
.08
.25
D
E
e
2.70
1.50
3.10
1.80
.037 BSC
.075 BSC
.95 BSC
1.90 BSC
e1
H
L
.087
.126
.024
10°
2.20
3.20
.60
.004
.10
0°
0°
10°
α
e
B
L
E
H
e1
c
D
A
A1
REV. 1.6.2 11/17/04
15
ILC7082
SOT-23 Package Markings – ILC7082AIM5-XX
Output
Voltage (V)
2.5
*Package
Marking
EMXX
EWXX
ENXX
EAXX
EJXX
Order Information
ILC7082AIM525X
ILC7082AIM526X
ILC7082AIM527X
ILC7082AIM528X
ILC7082AIM5285X
ILC7082AIM529X
ILC7082AIM530X
ILC7082AIM531X
ILC7082AIM532X
ILC7082AIM533X
ILC7082AIM536X
ILC7082AIM545X
ILC7082AIM547X
ILC7082AIM550X
ILC7082AIM5ADJX
Supplied as:
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
2.6
2.7
2.8
2.85
2.9
EKXX
EBXX
EHXX
ELXX
3.0
3.1
3.2
3.3
ECXX
EDXX
EPXX
EGXX
EEXX
EFXX
3.6
4.5
4.7
5.0
ADJ
* Note: First two characters identify the product and the last two characters identify the manufacturing lot code
SOIC Package Markings – ILC7082AIK-xx
Output
Voltage (V)
Order Information
ILC7082AIK50X
ILC7082AIK50
Package Marking
7082AIK5
Supplied as:
2,500 Units on Tape and Reel
Tubes
5.0
5.0
7082AIK5
Ordering Information
Ordering Information (TA = -40°C to +85°C)
ILC7082AIM5xx
ILC7082AIM5ADJ
ILC7082AIKxx
150mA, fixed voltage
150mA, adjustable voltage
150mA, fixed voltage (soic-8)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11/17/04 0.0m 001
Stock#DS30007082
2004 Fairchild Semiconductor Corporation
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