ISL6406IR_技术文档

ISL6406

®

Data Sheet

January 16, 2007

FN9073.7

Single Synchronous Buck Pulse-Width

Modulation (PWM) Controller

Features

• Operates from 3.3V/5V Input

The ISL6406 is an adjustable frequency, synchronous buck

switching regulator optimized for generating lower voltages

for the distributed DC/DC architectures. The ISL6406 offers

an adjustable output voltage.

• 0.8V to V Output Range

IN

- 0.8V Internal Reference

- ±1.5% Reference Accuracy

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

Designed to drive N-Channel MOSFETs in synchronous

buck topology, the ISL6406 integrates the control, output

adjustment and protection functions into a single package.

• Fast Transient Response

- High-Bandwidth Error Amplifier

The ISL6406 provides simple, single feedback loop, voltage-

mode control with fast transient response. The output

voltage can be precisely regulated to as low as 0.8V. The

error amplifier features a 15MHz gain-bandwidth product

and 6V/μs slew rate which enables high converter bandwidth

for fast transient performance.

• Lossless, Programmable Overcurrent Protection

- Uses Upper MOSFET’s r

DS(on)

• Programmable Switching Frequency 100kHz to 700kHz

• External Frequency Synchronization

• Two Device Options Available

Protection from overcurrent conditions is provided by

- ISL6406 . . . . . . . . . . . . . . . . Adjustable Output Voltage

• Internal Soft-Start

monitoring the r

of the upper MOSFET to inhibit PWM

DS(ON)

operation appropriately. This approach simplifies the

implementation and improves efficiency by eliminating the

need for a current sense resistor.

• QFN Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

The wide programmable switching frequency range of

100kHz to 700kHz allows the use of small surface mount

inductors and capacitors. The device also provides external

frequency synchronization making it an ideal choice for

DC/DC converter applications.

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

- Designated with “Z” Suffix (Refer to Note)

Applications

• 3V/5V DC/DC Converter Modules

• Distributed DC/DC 3.3V, 2.5V and 1.8V Power

Architectures for DSP, Logic, and Memory

• Power Supplies for Microprocessors

- PCs

- Embedded Controllers

• Memory Supplies

• Personal Computer Peripherals

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6406

Pinouts

ISL6406,

(16 LD SOIC/TSSOP)

TOP VIEW

ISL6406,

(16 LD QFN)

TOP VIEW

GND

1

2

3

4

5

6

7

8

16 UGATE

LGATE

CPVOUT

OCSET

CT1

15 BOOT

14 PHASE

13 VCC

16 15 14 13

CPVOUT

OCSET

CT1

PHASE

VCC

1

2

3

4

12

11

10

9

12 CPGND

11 COMP

10 VOUT

CT2

CPGND

COMP

RT

CT2

9

FB

SYNC/EN

5

6

7

8

Ordering Information

PART NUMBER*

PART MARKING

ISL6406IB

6406IBZ

TEMP. RANGE (°C)

-40 to +85

PACKAGE

16 Ld SOIC

PKG. DWG. #

ISL6406IB

M16.15

L16.5x5B

ISL6406IBZ (See Note)

ISL6406IR

-40 to +85

16 Ld SOIC (Pb-free)

16 Ld 5x5 QFN

ISL 6406IR

ISL6406 IRZ

ISL64 06IV

6406 IVZ

-40 to +85

ISL6406IRZ (See Note)

ISL6406IV

-40 to +85

16 Ld 5x5 QFN (Pb-free) L16.5x5B

-40 to +85

16 Ld TSSOP

M16.173

ISL6406IVZ (See Note)

-40 to +85

16 Ld TSSOP (Pb-free)

*Add “-T” suffix to part number for tape and reel packaging.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN9073.7

January 16, 2007

2

ISL6406

Functional Block Diagram

VCC

CPVOUT

CT1

CHARGE

PUMP

SDWN

POWER-ON

RESET (POR)

CT2

CPGND

OCSET

BOOT

+

-

SOFTSTART

OC

UGATE

COMPARATOR

20μA

PHASE

PWM

COMPARATOR

ERROR

AMP

GATE

CONTROL

LOGIC

+

-

+

-

+

-

PWM

0.8V

SDWN

LGATE

FB

VOUT

COMP

OSCILLATOR

SYNC/ENRT

GND

FN9073.7

January 16, 2007

3

ISL6406

Typical Application Schematic for 5V Input

V

IN

5V ±10%

C

BULK

IN

VCC

OCSET

CPVOUT

BOOT

CT1

CT2

R

OCSET

NC

C

DCPL

D

C

BOOT

ISL6406

C

HF

RT

R

BOOT

CPGND

R

T

UGATE

PHASE

GND

Q

1

2

L

OUT

C

V

OUT

VOUT

VCC

LGATE

FB

OUT

SYNC/EN

COMP

C

I

R

FB

R

C

F

R

OFFSET

Typical Application Schematic for 3.3V Input

V

IN

3.3V ±10%

C

BULK

IN

VCC

OCSET

CPVOUT

BOOT

CT1

R

OCSET

C

PUMP

C

DCPL

D

C

BOOT

CT2

RT

ISL6406

C

HF

R

BOOT

CPGND

R

T

UGATE

PHASE

GND

Q

1

L

OUT

C

V

OUT

VOUT

VCC

LGATE

FB

OUT

SYNC/EN

COMP

2

C

I

R

FB

R

C

F

R

OFFSET

FN9073.7

January 16, 2007

4

ISL6406

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Absolute Boot Voltage, V . . . . . . . . . . . . . . . . . . . . . . . +15.0V

Thermal Resistance (Typical)

θ

(°C/W)

θ

(°C/W)

JC

JA

BOOT

Upper Driver Supply Voltage, V

SOIC (Note 2) . . . . . . . . . . . . . . . . . . .

TSSOP (Note 2). . . . . . . . . . . . . . . . . .

QFN (Notes 3, 4) . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

70

90

35

N/A

4.5

- V

. . . . . . . . . . . +6.0V

BOOT

PHASE

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Operating Conditions

Temperature Range

ISL6406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Please refer to the Typical Application Schematics (page 3) for 3.3V/5V input configuration.

2. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

Schematic. V

= +3.3V. Typical values are at T = +25°C.

A

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

SUPPLY

CC

Shutdown Supply Current

SYNC/EN = GND

-

20

50

μA

Operating Supply Current (Note 5)

REFERENCE VOLTAGE

RT = 64.9kΩ

7

9.8

11.5

mA

Nominal Reference Voltage

Reference Voltage Tolerance

-

0.8

-

V

-1.5

-1.8

-2.1

-

1.5

1.8

2.1

%

T

= 0°C to +70°C

A

T

= -40°C to +85°C

A

ERROR AMPLIFIER

Open Loop Voltage Gain (Note 6)

Gain-Bandwidth Product (Note 6)

Slew Rate (Note 5)

-

82

-

dB

14

MHz

V/μs

COMP = 10pF

4.65

6.0

9.2

CHARGE PUMP

Nominal Charge Pump Output

Charge Pump Output Regulation

POWER-ON RESET

V

= 3.3V, No Load

4.8

5.1

-

5.5

5.0

V

CC

-5.0

%

Rising CPVOUT POR Threshold

T

= 0°C to +70°C

4.20

4.1

4.35

0.5

4.5

4.6

0.9

V

A

T

= -40°C to +85°C

A

CPVOUT POR Threshold Hysteresis

OSCILLATOR

0.3

Gate Output Frequency Range

RT = 200kΩ

80

100

300

715

1.4

120

340

770

1.7

kHz

V

RT = 64.9kΩ

RT = 26.1kΩ

Peak-to-Peak ΔV

250

650

1.1

Sawtooth Amplitude

OSC

FN9073.7

January 16, 2007

5

ISL6406

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

Schematic. V

= +3.3V. Typical values are at T = +25°C. (Continued)

A

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Sync. Frequency Range (Note 6)

1.1 Times the natural switching

frequency.

110

-

770

kHz

Minimum Sync Pulse Width (Note 6)

PWM Maximum Duty Cycle

GATE DRIVER OUTPUT (Note 6)

Upper Gate Source Current

Upper Gate Sink Current

Lower Gate Source Current

Lower Gate Sink Current

SOFT-START

-

40

96

100

-

ns

%

V

- V

= 5V, V = 4V

UGATE

-

-1

1

-

A

BOOT

PHASE

= 3.3V, V

= 4V

LGATE

-1

2

VCC

Soft-Start Slew Rate

f = 300kHz, T = 0°C to +70°C

6.2

-

6.7

7.3

7.6

-

ms

A

f = 300kHz, T = -40°C to +85°C

A

Internal Digital Circuit Clock Count

(Soft-start time varies with frequency)

2048

Clk Cycles

OVERCURRENT

OCSET Current Source

T

= 0°C to +70°C

18

16

20

22

23

μA

A

T

= -40°C to +85°C

A

NOTES:

5. This is the V

current consumed when the device is active but not switching.

CC

6. Guaranteed by design.

Typical Performance Curve

0.81

0.805

0.8

0.795

0.79

0.785

0.78

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE

FN9073.7

January 16, 2007

6

ISL6406

Pin Descriptions

CPVOUT - This pin represents the output of the charge

pump. The voltage at this pin is the bias voltage for the IC.

Connect a decoupling capacitor from this pin to ground. The

value of the decoupling capacitor should be at least 10x the

value of the charge pump capacitor. This pin may be tied to

the bootstrap circuit as the source for creating the BOOT

voltage.

BOOT - This pin provides ground referenced bias voltage to

the upper MOSFET driver. A bootstrap circuit is used to

create a voltage suitable to drive a logic-level N-Channel

MOSFET. A large (~1MΩ) resistor should be connected from

this pin to GND. The purpose of this resistor is to discharge

the BOOT pin during a shutdown condition, SYNC/EN =

LOW so that the gate drivers are quickly powered off by this

bleed resistor.

CT1 and CT2 - These pins are the connections for the

external charge pump capacitor. A minimum of a 0.1μF

ceramic capacitor is recommended for proper operation of

the IC.

UGATE - Connect this pin to the upper MOSFET’s gate. This

pin provides the PWM-controlled gate drive for the upper

MOSFET. This pin is also monitored by the adaptive shoot-

through protection circuitry to determine when the upper

MOSFET has turned off.

OCSET - Connect a resistor (R

) from this pin to the

, an internal 20μA

), and the upper MOSFET

OCSET

drain of the upper MOSFET (V ). R

IN OCSET

current source (I

OCSET

GND - This pin represents the signal and power ground for

the IC. Tie this pin to the ground island/plane through the

lowest impedance connection available.

on-resistance (r

) set the converter overcurrent (OC)

DS(ON)

trip point according to Equation 1:

LGATE - Connect this pin to the lower MOSFET’s gate. This

pin provides the PWM-controlled gate drive for the lower

MOSFET. This pin is also monitored by the adaptive shoot-

through protection circuitry to determine when the lower

MOSFET has turned off.

(I

)(R

)

OCSET

(EQ. 1)

OCSET

I

= -------------------------------------------------------

PEAK

r

DS(ON)

An overcurrent trip cycles the soft-start function.

VOUT - This pin provides the external switcher output

COMP and FB - COMP and FB are the available external

pins of the error amplifier. The FB pin is the inverting input of

the internal error amplifier and the COMP pin is the error

amplifier output. These pins are used to compensate the

control feedback loop of the converter.

voltage to the IC as feedback for the 1.8V fixed output

voltage option. Leave this pin open on the ISL6406 for the

adjustable output voltage option.

VCC - This pin provides bias supply for the ISL6406.

Connect a well-coupled 3.3V supply to this pin.

CPGND - This pin represents the signal and power ground

for the charge pump. Tie this pin to the ground island/plane

through the lowest impedance connection available.

PHASE - Connect this pin to the upper MOSFET’s source.

This pin is used to monitor the voltage drop across the upper

MOSFET for overcurrent protection.

SYNC/EN - This is a dual-function pin. To synchronize with

an external clock, apply a clock with a frequency 1.1 to 2.0

times higher than the part’s natural frequency to this pin. The

device may be disabled by tying this pin to ground. In this

shutdown mode, all functions are disabled and the device

will draw <50μA supply current.

RT - Connect an external resistor from this pin to ground for

frequency selection. Refer to RT vs Frequency curve of

Figure 3.

FN9073.7

January 16, 2007

7

ISL6406

Functional Description

200

180

160

140

120

100

80

Initialization

The ISL6406 automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary.

The Power-On Reset (POR) function continually monitors the

the output voltage of the charge pump. During POR, the charge

pump operates on a free running oscillator. Once the POR level

is reached, the charge pump oscillator is synched to the PWM

oscillator. The POR function also initiates the soft-start

operation after the charge pump output voltage exceeds its

POR threshold.

60

40

20

Soft-Start

50 100 150 200 250 300 350 400 450 500 550 600 650 700 750

FREQUENCY (kHz)

The POR function initiates the digital soft-start sequence.

The PWM error amplifier reference is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s). This

method provides a rapid and controlled output voltage rise.

The soft start sequence typically takes about 6.5ms.

FIGURE 3. RT vs FREQUENCY

Shoot-Through Protection

A shoot-through condition occurs when both the upper

MOSFET and lower MOSFET are turned on simultaneously,

effectively shorting the input voltage to ground. To protect

the regulator from a shoot-through condition, the ISL6406

incorporates specialized circuitry which insures that the

MOSFETs are not ON simultaneously.

(1V/DIV)

CPVOUT (5V)

The adaptive shoot-through protection utilized by the

ISL6406 looks at the lower gate drive pin, LGATE, and the

upper gate drive pin, UGATE, to determine whether a

MOSFET is ON or OFF. If the voltage from UGATE or from

LGATE to GND is less than 0.8V, then the respective

MOSFET is defined as being OFF and the other MOSFET is

turned ON. This method of shoot-through protection allows

the regulator to sink or source current.

VCC (3.3V)

V

(2.50V)

OUT

0V

Since the voltage of the lower MOSFET gate and the upper

MOSFET gate are being measured to determine the state of

the MOSFET, the designer is encouraged to consider the

repercussions of introducing external components between

the gate drivers and their respective MOSFET gates before

actually implementing such measures. Doing so may

interfere with the shoot-through protection.

t3

t0

t1

t2

TIME

FIGURE 2. SOFT-START INTERVAL

Figure 2 shows the soft-start sequence for a typical

application. At t0, the +3.3V VCC voltage starts to ramp. At

time t1, the Charge Pump begins operation and the +5V

CPVOUT IC bias voltage starts to ramp up. Once the voltage

on CPVOUT crosses the POR threshold at time t2, the

output begins the soft-start sequence. The triangle waveform

from the PWM oscillator is compared to the rising error

amplifier output voltage. As the error amplifier voltage

increases, the pulse-width on the UGATE pin increases to

reach the steady-state duty cycle at time t3.

Output Voltage Selection

The output voltage can be programmed to any level between

V

and the internal reference, 0.8V. An external resistor

IN

divider is used to scale the output voltage relative to the

reference voltage and feed it back to the inverting input of

the error amplifier, see Figure 4. However, since the value of

R1 affects the values of the rest of the compensation

components, it is advisable to keep its value less than 5K.

R4 can be calculated based on Equation 2:

Frequency Selection

The ISL6406 offers adjustable frequency from 100kHz to

700kHz by changing external resistor connected at pin RT.

Figure 3 shows the typical RT vs Frequency variation curve.

(R1)(0.8V)

(EQ. 2)

R4 = ------------------------------------------

V

– (0.8V)

OUT1

If the output voltage desired is 0.8V, simply route the output

back to the FB pin through R1, but do not populate R4.

FN9073.7

January 16, 2007

8

ISL6406

.

converter’s efficiency and reduces cost by eliminating a

+3.3V

current sensing resistor. The over current function cycles the

soft-start function in a hiccup mode to provide fault

protection. A resistor (R

trip level (see Typical Application diagrams). An internal

20µA (typical) current sink develops a voltage across

) programs the over current

OCSET

VIN

VCC

CPVOUT

BOOT

R

that is referenced to V . When the voltage across

OCSET

IN

D1

C4

the upper MOSFET (also referenced to V ) exceeds the

voltage across R

soft-start sequence.

IN

, the over current function initiates a

OCSET

Q1

UGATE

PHASE

L

OUT

V

OUT

ISL6406,

Q2

LGATE

+

C

V

(2.5V)

OUT

FB

C1

R1

C3

COMP

R3

C2

R2

R4

0V

INTERNAL SOFT-START FUNCTION

DELAY INTERVAL

FIGURE 4. OUTPUT VOLTAGE SELECTION

Frequency Synchronization and Enable

The external frequency synchronization and enable

functions are combined in SYNC/EN pin. This pin is TTL

compatible for VCC = 3.3V or 5V. The device is disabled if

the input to this pin is TTL LOW for more than 40μs (typ.); it

is enabled if the input is TTL HIGH without delay. When

disabling the IC, the charge pump is turned off and the

BOOT pin is left charged at ~5V. In some cases this charge

will inadvertant leak through the upper gate driver and can

possibly turn on the upper FET. To avoid this, it is

t0

t1

t2

TIME

FIGURE 5. OVERCURRENT PROTECTION RESPONSE

Figure 5 illustrates the protection feature responding to an

overcurrent event. At time t0, an overcurrent condition is

sensed across the upper MOSFET. As a result, the regulator

is quickly shutdown and the internal soft-start function begins

producing soft-start ramps. The delay interval seen by the

output is equivalent to three soft-start cycles. The fourth

internal soft-start cycle initiates a normal soft-start ramp of the

output, at time t1. The output is brought back into regulation

by time t2, as long as the overcurrent event has cleared. Had

the cause of the over current still been present after the delay

interval, the over current condition would be sensed and the

regulator would be shut down again for another delay interval

of three soft-start cycles. The resulting hiccup mode style of

protection would continue to repeat indefinitely.

recommended that a 1MΩ ‘bleed’ resistor be connected from

the BOOT pin to GND. This resistor is shown in the typical

application schematic in page 4 as R

.

BOOT

The SYNC/EN pin is monitored by the internal timer. The

timer allows SYNC pulses (TTL LOW level) to pass through,

as long as the pulses are shorter than 22μs. The minimum

SYNC pulse width is 40ns (typ.).

The oscillator can SYNC to an external frequency of

between 1.1 times and 2.0 times the free-running frequency.

Loop acquisition time is about 200 clock cycles. The timing

resistor (RT) is always required, regardless of whether

SYNC pulses are being used or not.

The overcurrent function will trip at a peak inductor current

(I

) determined by Equation 3:

peak

For instance, if RT is selected such that the switching

frequency is 100kHz then the ISL6406 can be synchronized

to a switching frequency from 110kHz to 200kHz.

(I

)(R

)

OCSET

(EQ. 3)

I

= -------------------------------------------------------

PEAK

r

DS(ON)

Overcurrent Protection

where I

is the internal OCSET current source (20µA

OCSET

The overcurrent function protects the converter from a

shorted output by using the upper MOSFET on-resistance,

typical). The OC trip point varies mainly due to the MOSFET

variations. To avoid overcurrent tripping in the

r

DS(ON)

r

, to monitor the current. This method enhances the

DS(ON)

FN9073.7

January 16, 2007

9

ISL6406

normal operating load range, find the R

Equation 3 with:

resistor from

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress.

OCSET

1. The maximum r

temperature.

at the highest junction

Careful component layout and printed circuit board design

minimizes the voltage spikes in the converters. As an example,

consider the turn-off transition of the PWM MOSFET. Prior to

turn-off, the MOSFET is carrying the full load current. During

turn-off, current stops flowing in the MOSFET and is picked up

by the lower MOSFET. Any parasitic inductance in the switched

current path generates a large voltage spike during the

switching interval. Careful component selection, tight layout of

the critical components, and short, wide traces minimizes the

magnitude of voltage spikes.

DS(ON)

2. The minimum I

3. Determine I

from the specification table.

OCSET

for, I

> I

+ (ΔI/2)

OUT(MAX)

PEAK

where ΔI is the output inductor ripple current.

For an equation for the ripple current see the section under

Component Selection Guidelines titled “Output Inductor

Selection” on page 12. A small ceramic capacitor should be

placed in parallel with R

to smooth the voltage across

in the presence of switching noise on the input

OCSET

R

OCSET

voltage.

There are two sets of critical components in a DC/DC

converter using the ISL6406. The switching components are

the most critical because they switch large amounts of

energy, and therefore tend to generate large amounts of

noise. Next, are the small signal components which connect

to sensitive nodes or supply critical bypass current and

signal coupling.

When the controller enters hiccup mode the differential

voltage across the error amplifier forces the COMP pin to rail

HIGH to approximately 5V. When the controller begins a new

soft start sequence out of hiccup mode the COMP pin will

need to discharge down to approximately 1.2V near the

beginning of the PWM ramp in order to start up correctly. To

ensure the controller can discharge the COMP pin fast

enough the R and C from COMP to FB must not have too

high a time constant. For time constant recommendations

refer to the Feedback Compensation section below.

A multi-layer printed circuit board is recommended. Figure 6

shows the connections of the critical components in the

+3.3V V

IN

Current Sinking

ISL6406

VCC

The ISL6406 incorporates a MOSFET shoot-through

protection method which allows a converter to sink current

as well as source current. Care should be exercised when

designing a converter with the ISL6406 when it is known that

the converter may sink current. When the converter is

sinking current, it is behaving as a boost converter that is

regulating its input voltage. This means that the converter is

boosting current into the input rail of the regulator. If there is

nowhere for this current to go, such as to other distributed

loads on the rail or through a voltage limiting protection

device, the capacitance on this rail will absorb the current.

This situation will allow the voltage level of the input rail to

increase. If the voltage level of the rail is boosted to a level

that exceeds the maximum voltage rating of any

C

VCC

CPVOUT

C

BP

C

IN

GND

D1

BOOT

C

BOOT

Q1

UGATE

PHASE

L

OUT

V

PHASE

OUT

components attached to the input rail, then those

Q2

C

LGATE

COMP

OUT

components may experience an irreversible failure or

experience stress that may shorten their lifespan. Ensuring

that there is a path for the current to flow other than the

capacitance on the rail will prevent this failure mode.

C

2

C

1

R

2

R

1

FB

Application Guidelines

C

R

3

R4

Layout Considerations

Layout is very important in high frequency switching

converter design. With power devices switching, the

resulting current transitions from one device to another

cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 6. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

FN9073.7

January 16, 2007

10

ISL6406

converter. Note that capacitors C and C

IN

could each

OUT

represent numerous physical capacitors.

V

IN

DRIVER

OSC

PWM

Dedicate one solid layer, usually a middle layer of the PC

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into

smaller islands of common voltage levels. Keep the metal

runs from the PHASE terminals to the output inductor short.

The power plane should support the input power and output

power nodes. Use copper-filled polygons on the top and

bottom circuit layers for the phase nodes. Use the remaining

printed circuit layers for small signal wiring. The wiring traces

from the GATE pins to the MOSFET gates should be kept

short and wide enough to easily handle the 1A of drive

current. The switching components should be placed close

to the ISL6406 first. Minimize the length of the connections

L

O

COMPARATOR

V

OUT

-

PHASE

+

ΔV

C

O

OSC

ESR

(PARASITIC)

Z

FB

V

E/A

Z

-

IN

+

REFERENCE

ERROR

AMP

DETAILED COMPENSATION COMPONENTS

Z

FB

V

OUT

C

1

Z

IN

between the input capacitors, C , and the power switches

IN

C

R

3

2

3

2

by placing them nearby. Position both the ceramic and bulk

input capacitors as close to the upper MOSFET drain and

islands as possible. Position the output inductor and output

capacitors between the upper and lower MOSFETs and the

load.

R

1

COMP

FB

-

+

The critical small signal components include any bypass

capacitors, feedback components, and compensation

ISL6406

REFERENCE

components. Position the bypass capacitor, C , close to

BP

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

the VCC pin with a via directly to the ground plane. Place

the PWM converter compensation components close to the

FB and COMP pins. The feedback resistors for both

regulators should also be located as close as possible to

the relevant FB pin with vias tied straight to the ground

plane as required.

Modulator Break Frequency Equations

1

f

= -----------------------------

(EQ. 4)

(EQ. 5)

LC

2Π

L C

O O

Feedback Compensation

1

f

= ----------------------------------------

ESR

2Π(ESR)(C

)

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

O

The compensation network consists of the error amplifier

(internal to the ISL6406) and the impedance networks Z

(V

) is regulated to the Reference voltage level. The error

OUT

IN

amplifier (Error Amp) output (V ) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with a peak amplitude of V at the

PHASE node. The PWM wave is smoothed by the output

E/A

and Z .The goal of the compensation network is to provide

FB

a closed-loop transfer function with the highest 0dB crossing

frequency (f 0dB ) and adequate phase margin. Phase

margin is the difference between the closed loop phase at

f 0dB and 180°.

IN

filter (L and C ).The modulator transfer function is the

O

small-signal transfer function of V

/V . This function is

OUT E/A

dominated by a DC Gain and the output filter (L and C ),

The equations below relate the compensation network’s

poles, zeros and gain to the components (R , R , R , C , C

2

O

with a double pole break frequency at F and a zero at

LC

1

2

3

1

F

. The DC Gain of the modulator is simply the input

and C ) in Figure 7. Use these guidelines for locating the

ESR

3

voltage (V ) divided by the peak-to-peak oscillator voltage,

poles and zeros of the compensation network:

IN

V

.

OSC

1. Pick gain (R /R ) for desired converter bandwidth.

2

1

2. Place first zero below filter’s double pole (~75% F ).

LC

3. Place second zero at filter’s double pole.

4. Place first pole at the ESR zero.

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin—repeat if necessary.

FN9073.7

January 16, 2007

11

ISL6406

During overcurrent hiccup mode the COMP pin will rail HIGH

IC from 3.3V. Selecting the proper capacitance value is

important so that the bias current draw and the current

required by the MOSFET gates do not overburden the

capacitor. A conservative approach is presented in

Equation 6.

to about 5V. When the soft start sequence is initiated out of

hiccup mode the COMP pin will have to discharge from 5V to

about 1.2V, the beginning of the PWM ramp in order to start

up properly. Use of a small COMP to FB Rs and Cs as

possible is recommended. The recommended value for C2

in Figure 7 is 4700pF or less.

I

+ I

GATE

(f )

S

BIAS

V

(EQ. 6)

C

= -------------------------------------- (1 . 5 )

PUMP

CC

Compensation Break Frequency

Equations

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

Figure 8 shows an asymptotic plot of the DC/DC converter’s

gain vs frequency. The actual Modulator Gain has a high

gain peak due to the high Q factor of the output filter and is

not shown in Figure 8. Using the above guidelines should

give a Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the compensation

gain. Check the compensation gain at F with the

P2

Modern digital ICs can produce high transient load slew

rates. High-frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

capabilities of the error amplifier. The Closed Loop Gain is

constructed on the graph of Figure 8 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer

function to the compensation transfer function and plotting

the gain. The compensation gain uses external impedance

networks Z and Z to provide a stable, high bandwidth

FB IN

High-frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. Use only specialized

low-ESR capacitors intended for switching-regulator

applications for the bulk capacitors. The bulk capacitor’s

ESR will determine the output ripple voltage and the initial

voltage drop after a high slew-rate transient. An aluminum

electrolytic capacitor’s ESR value is related to the case size

with lower ESR available in larger case sizes. However, the

Equivalent Series Inductance (ESL) of these capacitors

increases with case size and can reduce the usefulness of

the capacitor to high slew-rate transient loading.

(BW) overall loop. A stable control loop has a gain crossing

with -20dB/decade slope and a phase margin greater than

45 degrees. Include worst-case component variations when

determining phase margin.

OPEN LOOP

ERROR AMP GAIN

F

P1

F

Z1

Z2

P2

100

80

V

⎛

⎜

⎝

⎞

⎟

⎠

IN

---------------

20log

V

OSC

60

40

COMPENSATION

GAIN

20

0

R2

-------

⎛

⎝

⎞

⎠

20log

R1

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case

size perform better than a single large case capacitor.

-20

-40

-60

MODULATOR

GAIN

LOOP GAIN

10M

F

ESR

LC

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Output Inductor Selection

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by Equations 7 and 8:

Component Selection Guidelines

V

- V

V

OUT

IN

OUT

(EQ. 7)

ΔI =

Charge Pump Capacitor Selection

x

f x L

V

s

IN

A capacitor across pins CT1 and CT2 is required to create

the proper bias voltage for the ISL6406 when operating the

FN9073.7

January 16, 2007

12

ISL6406

The maximum RMS current required by the regulator may be

closely approximated through Equation 11:

(EQ. 8)

ΔV

= ΔI x ESR

OUT

2

V_OUT

-------------

V_IN

V_IN– V_OUTV_OUT

2

1

12

⎛

⎞ ⎞

------ ---------------------------- -------------

I_RMS

=

× I_OUT

+

×

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

⎝

⎠ ⎠

V_IN

L × f_s

MAX

(EQ. 11)

For a through hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These capacitors

must be capable of handling the surge-current at power-up.

Some capacitor series available from reputable manufacturers

are surge current tested.

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6406 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MOSFET Selection/Considerations

The ISL6406 requires two N-Channel power MOSFETs.

These should be selected based upon r

, gate supply

DS(ON)

requirements, and thermal management requirements.

The response time to a transient is different for the

application of load and the removal of load. Equations 9 and

10 give the approximate response time interval for

application and removal of a transient load:

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed between

the two MOSFETs according to duty factor.

L x I

TRAN

- V

OUT

t

=

(EQ. 9)

RISE

V

IN

The switching losses seen when sourcing current will be

different from the switching losses seen when sinking current.

When sourcing current, the upper MOSFET realizes most of

the switching losses. The lower switch realizes most of the

switching losses when the converter is sinking current (see

equations on next page). These equations assume linear

voltage-current transitions and do not adequately model power

loss due the reverse-recovery of the upper and lower

MOSFET’s body diode.

L x I

TRAN

(EQ. 10)

t

=

FALL

V

OUT

where: I

is the transient load current step, t

is the

TRAN

RISE

is the

response time to the application of load, and t

FALL

response time to the removal of load. The worst case

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

The gate-charge losses are dissipated by the ISL6406 and

don't heat the MOSFETs. However, large gate-charge

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q turns on. Place the

small ceramic capacitors physically close to the MOSFETs

increases the switching interval, t which increases the

SW

MOSFET switching losses. Ensure that both MOSFETs are

within their maximum junction temperature at high ambient

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate heatsink

may be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

1

and between the drain of Q and the source of Q .

1

2

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

Losses while Sourcing current

2

1

2

--

× D + ⋅ Io × V × t

P

= Io × r

× f

UPPER

DS(ON)

IN SW s

2

= Io x r

x (1 - D)

DS(ON)

LOWER

Losses while Sinking current

2

P

= Io x r

x D

DS(ON)

UPPER

2

1

2

--

× (1 – D) + ⋅ Io × V × t

P

= Io × r

× f

s

LOWER

DS(ON)

IN SW

Where: D is the duty cycle = V

/ V ,

OUT IN

t

is the combined switch ON and OFF time, and

SW

f is the switching frequency.

(EQ. 12)

s

FN9073.7

January 16, 2007

13

ISL6406

Given the reduced available gate bias voltage (5V), logic-

level or sub-logic-level transistors should be used for both

N-MOSFETs. Caution should be exercised with devices

The minimum bootstrap capacitance can be calculated by

rearranging Equation 13 and solving for C

.

BOOT

Q

GATE

(EQ. 14)

----------------------------------------------------

=

C

exhibiting very low V

characteristics. The shoot-

BOOT

GS(ON)

V

– V

BOOT1

BOOT2

through protection present aboard the ISL6406 may be

circumvented by these MOSFETs if they have large parasitic

impedances and/or capacitances that would inhibit the gate

of the MOSFET from being discharged below its threshold

level before the complementary MOSFET is turned on.

Typical gate charge values for MOSFETs considered in

these types of applications range from 20nC to 100nC.

Since the voltage drop across Q

is negligible,

- V . A schottky diode is

LOWER

V

is simply V

CPVOUT

BOOT1

D

recommended to minimize the voltage drop across the

bootstrap capacitor during the on-time of the upper

Bootstrap Component Selection

External bootstrap components, a diode and capacitor, are

required to provide sufficient gate enhancement to the upper

MOSFET. The internal MOSFET gate driver is supplied by

the external bootstrap circuitry as shown in Figure 9. The

MOSFET. Initial calculations with V

no less than 4V

BOOT2

will quickly help narrow the bootstrap capacitor range.

For example, consider an upper MOSFET is chosen with a

boot capacitor, C

, develops a floating supply voltage

BOOT

maximum gate charge, Q , of 100nC. Limiting the voltage

g

referenced to the PHASE pin. This supply is refreshed each

cycle, when D conducts, to a voltage of CPVOUT less

drop across the bootstrap capacitor to 1V results in a value

of no less than 0.1μF. The tolerance of the ceramic capacitor

should also be considered when selecting the final bootstrap

capacitance value.

BOOT

the boot diode drop, V , plus the voltage rise across

D

Q

.

LOWER

A fast recovery diode is recommended when selecting a

bootstrap diode to reduce the impact of reverse recovery

CPVOUT

D

BOOT

+

V

-

V

IN

charge loss. Otherwise, the recovery charge, Q , would

RR

D

ISL6406

have to be added to the gate charge of the MOSFET and

taken into consideration when calculating the minimum

bootstrap capacitance.

BOOT

C

BOOT

UGATE

PHASE

Q

UPPER

LOWER

NOTE:

= V

V

-V

D

G-S

CC

LGATE

-

+

NOTE:

_G-S= V

V

CC

GND

FIGURE 9. UPPER GATE DRIVE BOOTSTRAP

Just after the PWM switching cycle begins and the charge

transfer from the bootstrap capacitor to the gate capacitance

is complete, the voltage on the bootstrap capacitor is at its

lowest point during the switching cycle. The charge lost on

the bootstrap capacitor will be equal to the charge

transferred to the equivalent gate-source capacitance of the

upper MOSFET as shown:

(EQ. 13)

Q

= C

× (V

– V

)

BOOT2

GATE

BOOT

BOOT1

where Q

GATE

is the maximum total gate charge of the upper

is the bootstrap capacitance, V is

MOSFET, C

BOOT

BOOT1

the bootstrap voltage immediately before turn-on, and

V

is the bootstrap voltage immediately after turn-on.

BOOT2

The bootstrap capacitor begins its refresh cycle when the gate

drive begins to turn-off the upper MOSFET. A refresh cycle

ends when the upper MOSFET is turned on again, which

varies depending on the switching frequency and duty cycle.

FN9073.7

January 16, 2007

14

ISL6406

ISL6406 DC/DC Converter Application Circuit

The circuit below shows the device as it is configured on the

ISL6406 evaluation board. Detailed information on the

circuit, including a complete Bill-of-Materials and circuit

board description, can be found in Application Note AN1031.

3.3V

P

1

C

3

C

1A-B

C

2

GND

U

13

VCC

1

P

2

TP

1

4

3

5

6

7

OCSET

CT1

CT2

RT

R

C

R

1

4

TP

3

6

CPVOUT

BOOT

D

1

7

C

5

12

1

C

6

CPGND

GND

15

ISL6406

R

7

C

16

R

UGATE

PHASE

8

L

1

2.5V @ 5A

10

8

14

2

VOUT

P

3

P

C

5

8A-C

SYNC/EN

LGATE

Q

1

COMP

11

FB

9

C

10

R

3

GND

C

R

P

11

2

4

R

C

9

4

R

5

6

JP1

NOTE: Remove R3, R4, C9, and R5 from the board.

FN9073.7

January 16, 2007

15

ISL6406

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

0.0688

0.0098

0.020

MIN

1.35

0.10

0.33

0.19

9.80

3.80

MAX

1.75

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

-

1

2

3

0.25

-

L

0.51

9

SEATING PLANE

A

0.0075

0.3859

0.1497

0.0098

0.3937

0.1574

0.25

-

-A-

10.00

4.00

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

16

7

0°

8°

0°

8°

-

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

FN9073.7

January 16, 2007

16

ISL6406

Thin Shrink Small Outline Plastic Packages (TSSOP)

M16.173

N

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

MIN

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

GAUGE

PLANE

SYMBOL

MAX

0.043

0.006

0.037

0.012

0.008

0.201

0.177

MIN

-

MAX

1.10

0.15

0.95

0.30

0.20

5.10

4.50

NOTES

A

A1

A2

b

-

0.002

0.033

0.0075

0.0035

0.193

0.169

0.05

0.85

0.19

0.09

4.90

4.30

-

1

2

3

-

L

0.25

0.010

0.05(0.002)

SEATING PLANE

A

9

-A-

c

-

D

3

-C-

E1

e

4

α

0.026 BSC

0.65 BSC

-

A2

e

A1

c

E

0.246

0.020

0.256

0.028

6.25

0.50

6.50

0.70

-

b

0.10(0.004)

L

6

0.10(0.004) M

C

A M B S

N

16

7

o

0

8

0

8

-

α

NOTES:

Rev. 1 2/02

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.15mm (0.006

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact. (Angles in degrees)

FN9073.7

January 16, 2007

17

ISL6406

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.5x5B

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

0.80

0.90

-

A1

A2

A3

b

-

9

0.20 REF

9

0.28

2.95

0.33

0.40

3.25

5, 8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7, 8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7, 8

0.80 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

16

4

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9073.7

January 16, 2007

18


型号：	ISL6406IR
厂家：	Rochester Electronics
描述：	SWITCHING CONTROLLER, 770kHz SWITCHING FREQ-MAX, PQCC16, PLASTIC, MO-220-VHHB, MLFP, QFN-16 开关
文件：	总19页 (文件大小：1066K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6406IR [ROCHESTER]

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