ISL6700IR-T [ROCHESTER]
1.4 A HALF BRDG BASED MOSFET DRIVER, PQCC12, 4 X 4 MM, PLASTIC, MLFP-12;
| 型号： | ISL6700IR-T |
| 厂家： | 
Rochester Electronics |
| 描述： | 1.4 A HALF BRDG BASED MOSFET DRIVER, PQCC12, 4 X 4 MM, PLASTIC, MLFP-12 驱动 |
| 文件： | 总9页 (文件大小：911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6700
®
Data Sheet
December 29, 2004
FN9077.6
80V/1.25A Peak, Medium Frequency, Low
Cost, Half-Bridge Driver
Features
• Drives 2 N-Channel MOSFETs in Half-Bridge
Configuration
The ISL6700 is an 80V/1.25A peak, medium frequency, low
cost, half-bridge driver IC available in 8-lead SOIC and
12-lead QFN plastic packages. The low-side and high-side
gate drivers are independently controlled and matched to
25ns. This gives the user maximum flexibility in dead-time
selection and driver protocol. Undervoltage protection on
both the low-side and high-side supplies force the outputs
low. Non-latching, level-shift translation is used to control the
upper drive circuit. Unlike some competitors, the high-side
output returns to its correct state after a momentary
undervoltage of the high-side supply.
• Space Saving SO8 and Low R
C-S
QFN Packages
• Phase Supply Max Voltage to 80VDC
• Bootstrap Supply Max Voltage to 96VDC
• Drives 1000pF Load with Rise and Fall Times Typ. 15ns
• TTL/CMOS Compatible Input Thresholds
• Independent Inputs for Non-Half-Bridge Topologies
• No Start-Up Problems
• Low Power Consumption
Ordering Information
• Wide Supply Range
PART
TEMP. RANGE
• Supply Undervoltage Protection
NUMBER
(°C)
PACKAGE
8 Ld SOIC
PKG. DWG. #
M8.15
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN
- Quad Flat No Leads - Package Outline
ISL6700IB
-40 to 125
-40 to 125
ISL6700IBZ
(See Note)
8 Ld SOIC
(Pb-free)
M8.15
ISL6700IR
-40 to 125
-40 to 125
12 Ld 4x4 QFN
L12.4x4
L12.4x4
• Pb-Free Available (RoHS Compliant)
ISL6700IRZ
(See Note)
12 Ld 4x4 QFN
(Pb-free)
Applications
• Telecom/Datacom Power Supplies
Add “-T” suffix to part number for tape and reel packaging.
• Half-Bridge Converters
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• Two-Switch Forward Converters
• Active Clamp Forward Converters
Pinouts
ISL6700IB (SOIC)
ISL6700IR (QFN)
TOP VIEW
TOP VIEW
V
1
2
3
4
8
7
6
5
DD
HI
LI
HB
HO
HS
LO
12
11
10
HI
NC
LI
9
8
7
HO
NC
HS
1
2
3
V
SS
EPAD
4
5
6
NOTE: EPAD = Exposed PAD.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL6700
Application Block Diagram
+12V
V
+48V
SECONDARY
CIRCUIT
HB
DD
DRIVE
HI
HO
HS
LO
HI
LI
PWM
CONTROLLER
DRIVE
LO
REFERENCE
AND
ISL6700
ISOLATION
V
SS
Functional Block Diagram
HB
LEVEL
U/V
HO
HS
SHIFT
HI
LI
TURN-ON
DELAY
LO
DETECTOR
UNDERVOLTAGE
V
DD
V
SS
EPAD (QFN PACKAGE ONLY)
FN9077.6
2
December 29, 2004
ISL6700
+48V
+12V
SECONDARY
CIRCUIT
ISL6700
PWM
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
ISL6700
PWM
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
FN9077.6
3
December 29, 2004
ISL6700
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical)
SOIC (Note 3) . . . . . . . . . . . . . . . . . . .
QFN (Note 4) . . . . . . . . . . . . . . . . . . . .
Supply Voltage, V
(Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to 16V
θ
(°C/W)
95
49
θ
(°C/W)
JC
N/A
7
DD
JA
LI and HI Voltages (Note 1) . . . . . . . . . . . . . . . . -0.3V to V
+0.3V
DD
Voltage on HS (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Voltage on HB (Note 1) . . . . . . . . . . . . . . . . V -0.3V to V +V
HS HS DD
SS DD
Max Power Dissipation at 25°C in Free Air (SOIC, Note 3). 1.316W
Max Power Dissipation at 25°C in Free Air (QFN, Note 4) . .2.976W
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature Range . . . . . . . . .-40°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Voltage on LO (Note 1) . . . . . . . . . . . . . . . . . V -0.3 to V +0.3V
Voltage on HO (Note 1) . . . . . . . . . . . . . . . . V -0.3V to V +0.3V
HS
HB
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Maximum Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 15V
DD
For Recommended soldering conditions see Tech Brief TB389.
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 75V
Voltage on HS (Note 2) . . . . . . . . . .(Repetitive Transient) -1V to 80V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . V +7.5V to V +V
HS
HS DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
1. All voltages referenced to V unless otherwise specified.
SS
2. Based on V =15V. The magnitude of the allowable negative transient on the HS pin is a function of the V
DD
supply voltage. V <15.6V-
HS
DD
is the magnitude of the allowable negative transient and V is the forward voltage drop of the bootstrap diode.
V
+V , where V
F HS
DD
F
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ , the
JA
JC
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, No Load on LO or HO, Unless Otherwise Specified
HS
DD
HB
T = -40°C TO
J
T
= 25°C
125°C
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
SUPPLY CURRENTS & UNDERVOLTAGE PROTECTION
V
V
V
Quiescent Current
Operating Current
Operating Current
I
LI = 0 or V
f = 50kHz
-
-
-
-
-
-
-
-
1.9
2.0
2.5
1.25
170
1.45
2.4
-
2.2
2.2
3.0
1.5
240
1.8
2.8
1
-
-
-
-
-
-
-
-
2.4
2.5
4.0
1.8
250
2.0
3.0
1
mA
mA
mA
mA
µA
DD
DD
DD
DD
DD
I
I
DDO
DDO
f = 500kHz
HI = 0
HB Off Quiescent Current
HB On Quiescent Current
HB Operating Current
HB Operating Current
HS Leakage Current
I
HBL
HBH
HBO
HBO
I
HI = V
DD
f = 50kHz, C = 1000pF
I
I
mA
mA
µA
L
f = 500kHz, C = 1000pF
L
I
V
V
= 80V
= 96V
HLK
HS
HB
V
V
Rising Undervoltage Threshold
Falling Undervoltage Threshold
V
6.8
6.5
7.6
7.1
8.25
7.8
6.5
6.25
0.15
4.0
8.5
8.1
V
V
V
V
DD
DD
DDUV+
V
DDUV-
Undervoltage Hysteresis
HB Undervoltage Threshold
INPUT PINS: LI and HI
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
Low Level Input Current
High Level Input Current
UVHYS
VHBUV
0.17
4.8
0.45
5.3
0.75
6.5
0.90
7.5
Referenced to HS
V
Full Operating Conditions
Full Operating Conditions
0.8
-
1.6
1.7
100
-60
115
-
0.8
-
-
V
V
IL
V
2.2
-
2.2
-
IH
-
-
mV
µA
µA
I
V
V
= 0V, Full Operating Conditions
= 5V, Full Operating Conditions
-70
30
-30
130
-80
30
-30
145
IL
IN
IN
I
IH
FN9077.6
4
December 29, 2004
ISL6700
Electrical Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
SS HS
DD
HB
T = -40°C TO
J
T
= 25°C
125°C
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
GATE DRIVER OUTPUT PINS: LO & HO
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
V
I
I
= 0A
= 0A
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
V
V
A
A
OL
-V
OUT
OUT
V
-
DD OH
I +
V
V
= 0V
1.4
1.3
O
OUT
OUT
Peak Pulldown Current
I -
= 12V
-
-
O
Switching Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified
SS HS
DD
HB
T
= -40°C
J
T
= 25°C
TO 125°C
J
TEST
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX MIN MAX UNITS
Lower Turn-off Propagation Delay
(LI Falling to LO Falling)
t
-
-
-
-
45
60
75
70
50
75
82
75
-
-
-
-
65
90
95
95
ns
ns
ns
ns
LPHL
Upper Turn-off Propagation Delay
(HI Falling to HO Falling)
t
t
HPHL
Lower Turn-on Propagation Delay
(LI Rising to LO Rising)
t
LPLH
HPLH
Upper Turn-on Propagation Delay
(HI Rising to HO Rising)
Deadtime, (t
Deadtime, (t
Rise Time
Fall Time
- t
)
)
DHt
LI, HI switched simultaneously
0
0
-
24
17
5
-
0
0
-
-
ns
ns
ns
ns
ns
ns
HPLH LPHL
ON
- t
LPLH HPHL
DLt
-
-
ON
t
20
20
20
25
25
25
25
30
R
t
-
5
-
F
Delay Matching: Lower Turn-On and Upper Turn-Off
Delay Matching: Lower Turn-Off and Upper Turn-On
t
-
8
-
MON
t
-
-15
-
MOFF
Pin Descriptions
SYMBOL
DESCRIPTION
V
Positive supply to control logic and lower gate drivers. De-couple this pin to V . Connect anode of bootstrap diode to this pin.
SS
DD
HI
LI
Logic level input that controls the HO output.
Logic level input that controls the LO output.
V
Chip negative supply, generally will be ground.
Low-side output. Connect to gate of low-side power MOSFET.
SS
LO
HS
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HO
HB
High-side output. Connect to gate of high-side power MOSFET.
High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive
side of bootstrap capacitor to this pin.
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
FN9077.6
5
December 29, 2004
ISL6700
Timing Diagrams
LI
HI
HI,
LI
t
,
t
t
,
HPLH
HPHL
LPHL
LO
HO
t
LPLH
t
t
MOFF
MON
HO,
LO
FIGURE 4.
FIGURE 3.
FN9077.6
6
December 29, 2004
ISL6700
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L12.4x4
12 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
0.80
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
1.95
1.95
0.28
0.38
2.25
2.25
5, 8
D
4.00 BSC
-
D1
D2
E
3.75 BSC
9
2.10
7, 8
4.00 BSC
-
E1
E2
e
3.75 BSC
9
2.10
7, 8
0.80 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
12
3
3
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 1 5/03
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9077.6
7
December 29, 2004
ISL6700
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9077.6
8
December 29, 2004
相关型号：
©2020 ICPDF网 联系我们和版权申明