ISL84052IA-T [ROCHESTER]
DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, PLASTIC, SSOP-16;
| 型号： | ISL84052IA-T |
| 厂家： | 
Rochester Electronics |
| 描述： | DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, PLASTIC, SSOP-16 光电二极管 |
| 文件： | 总19页 (文件大小：1266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84051, ISL84052, ISL84053
®
Data Sheet
October 8, 2010
FN6047.9
Low Voltage, Single and Dual Supply,
8-to-1 Multiplexer, Dual 4-to-1 Multiplexer
and a Triple SPDT Analog Switch
Features
• Drop-in Replacements for MAX4051/MAX4051A,
MAX4052/MAX4052A and MAX4053/MAX4053A
The Intersil ISL84051, ISL84052, ISL84053 devices are
precision, bidirectional, analog switches configured as a
8-Channel multiplexer/demultiplexer (ISL84051), a dual
differential 4-Channel multiplexer/demultiplexer (ISL84052)
and a triple single pole/double throw (SPDT) switch
(ISL84053) designed to operate from a single +2V to +12V
supply or from a ±2V to ±6V supply. All devices have an inhibit
pin to simultaneously open all signal paths.
• Pin Compatible with MAX4581, MAX4582, MAX4583 and
with Industry Standard 74HC4051, 74HC4052 and
74HC4053
• ON-Resistance (r ) Max, V = ±5V. . . . . . . . . . . . 100Ω
ON
S
• ON-Resistance (r ) Max, V = +5V. . . . . . . . . . . . 225Ω
ON
S
• r
ON
Matching Between Channels . . . . . . . . . . . . . . . . . . <6Ω
• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2pC
• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V
• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . ±2V to ±6
ON-resistance is 60Ω with a ±5V supply and 125Ω with a
single +5V supply. Each switch can handle rail to rail analog
signals. The off-leakage current is only 5nA at +85°C with a
±5V supply.
• Fast Switching Action (V = +5V)
S
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single +3.3V
and +5V supply or dual ±5V supplies.
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns
OFF
• Guaranteed Max Off-leakage @ V = ±5V. . . . . . . . . . 5nA
S
The ISL84051 is a 8-to-1 multiplexer device. The ISL84052 is
a dual 4-to-1 multiplexer device. The ISL84053 is a committed
triple SPDT, which is perfect for use in 2-to-1 multiplexer
applications.
• Break-Before-Make
• TTL, CMOS Compatible
• Pb-Free Available (RoHS Compliant)
Table 1 summarizes the performance of this family.
Applications
TABLE 1. FEATURES AT A GLANCE
• Portable Equipment
ISL84051
ISL84052
ISL84053
• Communications Systems
- Radios
DUAL
4:1 Mux
TRIPLE
SPDT
CONFIGURATION
±5V r
8:1 Mux
60Ω
- Telecom Infrastructure
- ADSL, VDSL Modems
60Ω
50ns/40ns
125Ω
60Ω
50ns/40ns
125Ω
ON
±5V t /t
50ns/40ns
125Ω
ON OFF
• Test Equipment
5V r
ON
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners (MRI)
- ATE
5V t /t
90ns/60ns
250Ω
90ns/60ns
250Ω
90ns/60ns
250Ω
ON OFF
3V r
ON
3V t /t
180ns/100ns 180ns/100ns 180ns/100ns
ON OFF
Packages
- Electrocardiograph
16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
16 Ld QSOP 16 Ld QSOP 16 Ld QSOP
16 Ld TSSOP 16 Ld TSSOP
• Audio and Video Signal Routing
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004, 2006, 2007, 2010. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL84051, ISL84052, ISL84053
Pinouts
ISL84051
(16 LD SOIC, QSOP, TSSOP)
TOP VIEW
ISL84052
(16 LD SOIC, QSOP, TSSOP)
TOP VIEW
NO1
NO3
COM
NO7
NO5
INH
1
2
3
4
5
6
7
8
16 V+
NO0B
1
2
3
4
5
6
7
8
16 V+
15 NO2
14 NO4
13 NO0
12 NO6
11 ADDC
10 ADDB
NO1B
COMB
NO3B
NO2B
INH
15 NO1A
14 NO2A
13 COMA
12 NO0A
11 NO3A
10 ADDB
LOGIC
V-
V-
LOGIC
9
ADDA
GND
9
ADDA
GND
ISL84053
(16 LD SOIC, QSOP)
TOP VIEW
NOB
NCB
NOA
COMA
NCA
INH
1
2
3
4
5
6
7
8
16 V+
15 COMB
14 COMC
13 NOC
12 NCC
11 ADDC
10 ADDB
V-
9
ADDA
GND
NOTE:
1. Switches Shown for Logic “0” Inputs.
Pin Description
PIN NUMBER
PIN NAME
V+
ISL84051
ISL84052
ISL84053
FUNCTION
16
7
16
7
16
7
Positive Power Supply Input
V-
Negative Power Supply Input. Connect to GND for Single Supply Configurations.
Ground Connection
GND
INH
8
8
8
6
6
6
Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn
all switches off.
COM
COMA
COMB
COMC
3
Analog Switch Common Pin
13
3
4
15
14
NO1, NO3,
NO7, NO5,
NO6, NO4,
NO2
1, 2,
4, 5,
12, 14,
15
Analog Switch Normally Open Pin
FN6047.9
October 8, 2010
2
ISL84051, ISL84052, ISL84053
Pin Description (Continued)
PIN NUMBER
PIN NAME
ISL84051
ISL84052
ISL84053
FUNCTION
NO0B, NO1B,
NO3B, NO2B,
NO3A, NO0A,
NO2A,
1
2
4
Analog Switch Normally Open Pin
5
NO1A
11
12
14
15
NOB, NOA,
NOC
1, 3
13
NCB, NCA,
NCC
2, 5
12
Analog Switch Normally Closed Pin
ADDA, ADDB,
ADDC
9
10
11
9
10
-
9
10
11
Address Input Pin
Ordering Information
PART NUMBER
PART MARKING
84051IB
84051IBZ
TEMP. RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
16 Ld SOIC
PKG. DWG. #
M16.15
ISL84051IB (Note 2)
ISL84051IBZ (Notes 2, 4, 5)
ISL84051IA (Note 2)
16 Ld SOIC (Pb-free)
16 Ld QSOP
M16.15
84051 IA
84051 IAZ
84051 IVZ
84052IB
M16.15A
M16.15A
M16.173
M16.15
ISL84051IAZ (Notes 2, 4, 5)
ISL84051IVZ (Notes 2, 4, 5)
ISL84052IB (Note 2)
16 Ld QSOP (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld SOIC
ISL84052IBZ (Notes 2, 4, 5)
ISL84052IA (Note 2)
84052IBZ
84052 IA
84052 IAZ
84052 IVZ
84053IBZ
84053 IA
84053 IAZ
16 Ld SOIC (Pb-free)
16 Ld QSOP
M16.15
M16.15A
M16.15A
M16.173
M16.15
ISL84052IAZ (Notes 2, 4, 5)
ISL84052IVZ (Notes 2, 4, 5)
ISL84053IBZ (Notes 2, 4, 5)
ISL84053IA-T (Note 3)
ISL84053IAZ (Notes 2, 4, 5)
NOTES:
16 Ld QSOP (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld QSOP
M16.15A
M16.15A
16 Ld QSOP (Pb-free)
2. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL84051, ISL84052, ISL84053. For more information on MSL
please see techbrief TB363.
FN6047.9
October 8, 2010
3
ISL84051, ISL84052, ISL84053
Truth Tables
ISL84052
ISL84051
INH
ADDB
ADDA
SWITCH ON
None
SWITCH
INH
1
ADDC
ADDB
ADDA
ON
None
NO0
NO1
NO2
NO3
NO4
NO5
NO6
NO7
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
NO0
0
NO1
0
NO2
0
NO3
0
0
ISL84053
0
INH
1
ADD
X
ADD
X
ADD
A
SWITCH ON
C
B
0
X
0
None
0
0
X
X
NC
NO
NC
NO
A
A
B
B
C
C
0
X
X
1
0
X
0
X
X
X
X
0
X
1
0
0
X
NC
NO
0
1
X
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and
10V. X = Don’t Care.
FN6047.9
October 8, 2010
4
ISL84051, ISL84052, ISL84053
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V
Input Voltages
Thermal Resistance (Typical, Notes 7, 8)
θ
(°C/W)
θ
(°C/W)
JA
JC
16 Ld SOIC Package . . . . . . . . . . . . . .
16 Ld QSOP Package . . . . . . . . . . . . .
16 Ld TSSOP Package . . . . . . . . . . . .
75
95
110
39
56
33
INH, NO, NC, ADD (Note 6). . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V)
Output Voltages
COM (Note 6). . . . . . . . . . . . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA
Peak Current NO, NC, or COM
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±100mA
ESD Rating
HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >2kV
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
6. Signals on NC, NO, COM, ADD, or INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current
ratings.
7. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
8. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications - 5V Supply
Test Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
INH
= 2.4V, V
= 0.8V (Note 9),
INL
SUPPLY
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -
40°C to +85°C.
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
+25
Full
+25
Full
+25
Full
+25
Full
+25
Full
+25
Full
+25
Full
V-
-
V+
100
125
6
V
Ω
ON-Resistance, r
ON
V
= ±5V, I
COM
= 1mA, V
= 1mA, V
= 1mA, V
or V
or V
or V
= ±3V
-
60
S
NO
NO
NO
NC
NC
NC
(see Figure 5)
-
-
Ω
r
Matching Between Channels,
V
= ±5V, I
= ±3V
-
-
Ω
ON
Δr
S
COM
COM
(Note 12)
ON
-
-
12
10
15
-
Ω
r
Flatness, r
FLAT(ON)
V
= ±5V, I
= ±3V, 0V
-
-
Ω
ON
S
(Note 13)
-
-
-
Ω
NO or NC OFF Leakage Current,
or I
V
= ±5.5V, V
COM
= ±4.5V, V
= ±4.5V, V
= ±4.5V, V
or V
or V
or V
= ±4.5V
= ±4.5V
= ±4.5V
0.002
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
S
NO
NO
NO
NC
NC
NC
I
(Note 13)
NO(OFF)
NC(OFF)
-5
-
-
5
COM OFF Leakage Current,
, (ISL84051)
V
= ±5.5V, V
0.002
-
S
COM
COM
COM
COM
I
(Note 13)
COM(OFF)
-5
-
-
5
COM OFF Leakage Current,
, (ISL84052, ISL84053)
V
= ±5.5V, V
0.002
-
S
I
(Note 13)
COM(OFF)
-2.5
-
-
2.5
-
COM ON Leakage Current,
, (ISL84051)
V
= ±5.5V, V
= V
or V
= ±4.5V
0.002
S
NO
NO
NC
NC
I
(Note 13)
COM(ON)
-5
-
-
0.002
-
5
COM ON Leakage Current,
, (ISL84052, ISL84053)
V
= ±5.5V, V
= V
or V
= ±4.5V (Note 13) +25
Full
-
S
I
COM(ON)
-2.5
2.5
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V , V
Full
Full
2.4
-
-
-
-
0.8
1
V
V
INH ADDH
Input Voltage Low, V , V
INL ADDL
Input Current, I
, I , I
,
V
= ±5.5V, V
, V
= 0V or V+
Full
-1
0.03
µA
INH INL ADDH
S INH ADD
I
ADDL
FN6047.9
October 8, 2010
5
ISL84051, ISL84052, ISL84053
Electrical Specifications - 5V Supply
Test Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
INH
= 2.4V, V
= 0.8V (Note 9),
INL
SUPPLY
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -
40°C to +85°C. (Continued)
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
V
C
= ±4.5V, V
NO
or V
= ±3V, R = 300Ω,
+25
Full
+25
Full
+25
-
-
-
-
-
50
60
40
50
75
-
-
-
-
-
ns
ns
ns
ns
ns
ON
S
NC
L
= 35pF, V = 0V to 3V (see Figure 1)
L
IN
Inhibit Turn-OFF Time, t
V
C
= ±4.5V, V
NO
or V
= ±3V, R = 300Ω,
NC L
OFF
S
= 35pF, V = 0V to 3V (see Figure 1)
L
IN
Address Transition Time, t
Break-Before-Make Time, t
Charge Injection, Q
V
C
= ±4.5V, V
NO
or V
= ±3V, R = 300Ω,
NC L
TRANS
S
= 35pF, V = 0V to 3V (see Figure 1)
L
IN
V
C
= ±5.5V, V
NO
or V
= 3V, R = 300Ω,
+25
-
10
-
ns
BBM
S
NC
L
= 35pF, V = 0V to 3V (see Figure 3)
L
IN
C
= 1.0nF, V = 0V, R = 0Ω (see Figure 2)
+25
-
-
-
-
-
-
-
-
-
-
2
3
-
-
-
-
-
-
-
-
-
-
pC
pF
pF
pF
pF
pF
pF
pF
dB
dB
L
G
G
NO/NC OFF-Capacitance, C
f = 1MHz, V
or V
= V = 0V (see Figure 7) +25
COM
OFF
NO
NC
COM OFF-Capacitance, C
f = 1MHz, V
(see Figure 7)
or V
= V
= 0V
ISL84051
ISL84052
ISL84053
ISL84051
ISL84052
ISL84053
+25
+25
+25
+25
+25
+25
+25
+25
21
12
9
OFF
NO
NC
COM
COM ON-Capacitance, C
OFF Isolation
f = 1MHz, V
or V
= V
= 0V
26
18
14
<90
< -90
COM(ON)
NO
(see Figure 7)
NC
COM
R
V
= 50Ω, C = 15pF, f = 100kHz
L
L
or V
= 1V
(see Figures 4 and 6)
NO
NC
RMS
Crosstalk, (Note 9) (ISL84052,
ISL84053 Only)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
+25
Full
25
±2
-1
-
0.1
-
±6
1
V
Positive Supply Current, I+
V
Off
= ±5.5V, V
, V
INH ADD
= 0V or V+, Switch On or
µA
µA
µA
µA
S
-10
-1
10
1
Negative Supply Current, I-
0.1
-
Full
-10
10
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
INH
Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
= 2.4V, V
= 0.8V (Note 9),
INL
-40°C to +85°C.
MIN
MAX
(Notes 10,
11)
TEMP (Notes 10,
PARAMETER
TEST CONDITIONS
(°C)
11)
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
+25
Full
+25
Full
+25
Full
0
-
V+
225
280
-
V
ON-Resistance, r
V+ = 5V, I
= 1.0mA, V
or V = 3.5V
NC
-
-
125
Ω
ON
COM
(see Figure 5)
NO
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 5.5V, V
(Note 13)
= 0V, 4.5V, V
= 0V, 4.5V, V
or V
= 4.5V, 0V
-
0.002
nA
nA
nA
nA
COM
NO
NO
NC
NC
I
NO(OFF)
NC(OFF)
-10
-
-
0.002
-
10
-
COM OFF Leakage Current,
, (ISL84051)
V+ = 5.5V, V
(Note 13)
or V
= 4.5V, 0V
COM
I
COM(OFF)
-10
10
FN6047.9
October 8, 2010
6
ISL84051, ISL84052, ISL84053
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
= 2.4V, V
= 0.8V (Note 9),
INL
INH
-40°C to +85°C. (Continued)
MIN
MAX
(Notes 10,
11)
TEMP (Notes 10,
PARAMETER
TEST CONDITIONS
(°C)
+25
Full
+25
Full
11)
TYP
0.002
-
UNITS
nA
COM OFF Leakage Current,
, (ISL84052, ISL84053)
V+ = 5.5V, V
(Note 13)
= 0V, 4.5V, V
or V
NC
= 4.5V, 0V
-
-
5
COM
NO
I
COM(OFF)
-5
-
nA
COM ON Leakage Current,
V+ = 5.5V, V
COM
= V
or V
4.5V (Note 13)
0.002
-
-
nA
NO
NC =
I
COM(ON)
-10
10
nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V , V
Full
Full
Full
2.4
-
-
-
-
0.8
1
V
V
INH ADDH
Input Voltage Low, V , V
INL ADDL
, I , I
Input Current, I
INH INL ADDH
,
V+ = 5.5V, V
, V
INH ADD
= 0V or V+
-1
0.03
µA
I
ADDL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
V+ = 4.5V, V
NO
or V
= 3V, R = 300Ω,
+25
Full
+25
Full
+25
-
-
-
-
-
90
100
60
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NC
L
C
= 35pF, V = 0 to 3V (see Figure 1)
L
IN
Inhibit Turn-OFF Time, t
OFF
V+ = 4.5V, V
NO
or V
= 3V, R = 300Ω, C = 35pF,
L L
NC
= 0V to 3V (see Figure 1)
V
IN
70
Break-Before-Make Time, t
V+ = 5.5V, V
NO
or V
= 3V, R = 300Ω, C = 35pF,
30
BBM
NC
= 0V to 3V (see Figure 3)
L
L
V
C
R
IN
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0Ω (see Figure 2)
+25
+25
+25
-
-
-
2
-
-
-
pC
dB
dB
L
G
G
= 50Ω, C = 15pF, f = 100kHz
<90
<-90
L
L
V
or V
= 1V
(see Figures 4 and 6)
NO
NC
RMS
Crosstalk, (Note 9) (ISL84052,
ISL840533 Only)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
+25
Full
2
-
-
-
12
1
V
Positive Supply Current, I+
V+ = 5.5V, V- = 0V, V
Switch On or Off
, V
INH ADD
= 0V or V+,
-1
µA
µA
-10
10
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified. Boldface limits apply over the operating temperature
= 2.4V, V
= 0.8V (Note 9),
INL
INH
range, -40°C to +85°C.
MIN
MAX
(Notes 10,
11)
TEMP (Notes 10,
PARAMETER
TEST CONDITIONS
(°C)
11)
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
+25
Full
+25
Full
+25
Full
0
-
250
270
0.002
-
V+
-
V
ON-Resistance, r
V+ = 3V, I
= 1.0mA, V
or V = 1.5V
NC
-
-
Ω
ON
COM
NO
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 3.6V, V
(Note 13)
= 0V, 3V, V
or V
= 3V, 0V
-
-
nA
nA
nA
nA
COM
NO
NO
NC
I
NO(OFF)
NC(OFF)
-10
-
10
-
COM OFF Leakage Current,
, (ISL84051)
V+ = 3.6V, V
(Note 13)
= 0V, 3V, V
or V
= 3V, 0V
0.002
-
COM
NC
I
COM(OFF)
-10
10
FN6047.9
October 8, 2010
7
ISL84051, ISL84052, ISL84053
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified. Boldface limits apply over the operating temperature
= 2.4V, V
= 0.8V (Note 9),
INL
INH
range, -40°C to +85°C. (Continued)
MIN
MAX
(Notes 10,
11)
TEMP (Notes 10,
PARAMETER
TEST CONDITIONS
(°C)
+25
Full
+25
Full
11)
TYP
0.002
-
UNITS
nA
COM OFF Leakage Current,
, (ISL84052, ISL84053)
V+ = 3.6V, V
(Note 13)
= 0V, 3V, V
NO
or V
NC
= 3V, 0V
-
-
5
COM
I
COM(OFF)
-5
-
nA
COM ON Leakage Current,
V+ = 3.6V, V
= V
or V
3V (Note 13)
NC =
0.002
-
-
nA
COM
NO
I
COM(ON)
-10
10
nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V , V
Full
Full
Full
2.4
-
-
-
-
0.8
1
V
V
INH ADDH
Input Voltage Low, V , V
INL ADDL
Input Current, I
INH INL ADDH
, I , I
,
V+ = 3.6V, V
, V
INH ADD
= 0V or V+
-1
0.03
µA
I
ADDL
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t
V+ = 3V, V
NO
or V
= 1.5V, R = 300Ω, C = 35pF,
+25
Full
+25
Full
+25
-
-
-
-
-
180
280
100
200
90
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NC
= 0V to 3V (see Figure 1)
L
L
V
IN
Inhibit Turn-OFF Time, t
OFF
V+ = 3V, V
NO
or V
= 1.5V, R = 300Ω, C = 35pF,
L L
NC
= 0V to 3V (see Figure 1)
V
IN
Break-Before-Make Time, t
V+ = 3.6V, V
or V
= 1.5V, R = 300Ω,
NC L
BBM
NO
= 35pF, V = 0V to 3V (see Figure 3)
C
C
R
L
IN
Charge Injection, Q
OFF Isolation
= 1.0nF, V = 0V, R = 0Ω (see Figure 2)
+25
+25
+25
-
-
-
1
-
-
-
pC
dB
dB
L
G
G
= 50Ω, C = 15pF, f = 100kHz
<90
<-90
L
L
V
or V
= 1V
, (see Figures 4 and 6)
NO
NC
RMS
Crosstalk, (Note 9) (ISL84052,
ISL84053 Only)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
+25
Full
2
-
-
-
12
1
V
Positive Supply Current, I+
V+ = 3.6V, V- = 0V, V
Switch On or Off
, V
INH ADD
= 0V or V+
-1
µA
µA
-10
10
NOTES:
9. V = Input voltage to perform proper function.
IN
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
12. Δr
ON
= r
ON
(MAX) - r
(MIN).
ON
13. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
14. Between any two switches.
FN6047.9
October 8, 2010
8
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms
V+
V-
C
C
C
C
C
V+
NO0
ISL84051
V
OUT
COM
NO1-NO7
INH
ADDA-C
GND
C
35pF
L
R
300Ω
LOGIC
INPUT
L
V+
C
V-
C
V+
NO0
ISL84052
V
OUT
COM
NO1-NO3
INH
ADDA-B
GND
C
35pF
L
R
300Ω
LOGIC
INPUT
L
V+
C
V-
C
V+
NC
X
3V
t < 20ns
r
t < 20ns
f
ISL84053
COM
V
OUT
LOGIC
INPUT
50%
NO
X
X
0V
INH
t
ON
ADD
GND
X
C
35pF
L
R
300Ω
L
LOGIC
INPUT
V
OUT
90%
90%
SWITCH
OUTPUT
0V
Repeat test for other switches. C includes fixture and stray
L
t
OFF
capacitance.
R
L
-----------------------
V
= V
Logic input waveform is inverted for switches that have the opposite
logic sense.
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1A. INHIBIT t /t
ON OFF
MEASUREMENT POINTS
FIGURE 1B. INHIBIT t /t
ON OFF
TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FN6047.9
October 8, 2010
9
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms (Continued)
V+
V-
C
C
C
V+
NO0
NO7
ISL84051
COM
V
V-
OUT
C
NO1-NO6
ADDA-C
INH
GND
C
35pF
L
R
300Ω
L
LOGIC
INPUT
V+
V-
C
C
C
V+
NO0
ISL84052
COM
V
V-
OUT
NO3
C
NO1-NO2
ADDA-B
INH
GND
C
35pF
L
R
300Ω
L
LOGIC
INPUT
V+
V-
3V
0V
t < 20ns
r
t < 20ns
f
C
C
C
LOGIC
INPUT
50%
t
TRANS
V+
NC
ISL84053
COM
X
V
OUT
V-
NO
X
X
C
V
OUT
VNOX
0V
90%
ADD
X
INH
GND
C
35pF
L
R
300Ω
SWITCH
OUTPUT
LOGIC
INPUT
L
10%
VNOX
Repeat test for other switches. C includes fixture and stray
L
t
TRANS
capacitance.
R
L
-----------------------
V
= V
Logic input waveform is inverted for switches that have the opposite
logic sense.
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1C. ADDRESS t
MEASUREMENT POINTS
FIGURE 1D. ADDRESS t
TEST CIRCUIT
TRANS
TRANS
FIGURE 1. SWITCHING TIMES (Continued)
FN6047.9
October 8, 2010
10
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms (Continued)
V+
V-
C
C
3V
0V
V
R
OUT
OFF
OFF
G
LOGIC
INPUT
COM
INH
ON
NO or NC
ADDX
0Ω
SWITCH
OUTPUT
V
GND
G
ΔV
OUT
C
L
1nF
V
OUT
LOGIC
INPUT
Q = ΔV
x C
L
OUT
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2A. Q MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
V-
C
C
C
C
C
V
OUT
NO0-NO7
ADDA-C
COM
V+
C
L
R
L
300Ω
35pF
ISL84051
LOGIC
INPUT
INH
GND
V+
C
V-
C
V
OUT
NO0-NO3
ADDA-B
COM
V+
C
L
R
L
300Ω
35pF
ISL84052
LOGIC
INPUT
INH
GND
V+
C
V-
C
V
OUT
t < 20ns
r
NO
X
V+
COM
t < 20ns
X
f
3V
0V
C
L
35pF
R
L
300Ω
LOGIC
INPUT
NC
X
ISL84053
ADD
X
INH
GND
LOGIC
INPUT
80%
SWITCH
OUTPUT
V
OUT
Repeat test for other switches. C includes fixture and stray
L
capacitance.
0V
t
BBM
FIGURE 3B. t
TEST CIRCUIT
BBM
FIGURE 3A. t
BBM
MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6047.9
October 8, 2010
11
ISL84051, ISL84052, ISL84053
Test Circuits and Waveforms (Continued)
V+
V-
V+
V-
C
C
C
C
r
= V /1mA
1
ON
SIGNAL
GENERATOR
NO or NC
NO or NC
V
NX
0V OR V+
1mA
0V OR V+
0V OR V+
V
1
ADDX
ADDX
COM
ANALYZER
COM
INH
GND INH
GND
R
L
FIGURE 5. r
TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
ON
V+
V-
V+
C
V-
C
C
C
SIGNAL
GENERATOR
50Ω
NO OR NC
NO or NC
COM
A
A
A
ISL84052
AND
ISL84053
0V OR V+
ADDX
ADDX
IMPEDANCE
ANALYZER
0V OR V+
NO or NC
NC
COM
B
B
GND
INH
ANALYZER
COM
B
INH
GND
R
L
FIGURE 7. CAPACITANCE TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 8). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
Detailed Description
The ISL84051, ISL84052, ISL84053 analog switches offer
precise switching capability from a bipolar ±2V to ±6V or a
single 2V to 12V supply with low on-resistance (60Ω) and
high speed operation (t
= 50ns, t = 40ns). The devices
ON
OFF
are especially well suited to portable battery powered
equipment thanks to the low operating supply voltage (2V),
low power consumption (3μW), low leakage currents (5nA
max). High frequency applications also benefit from the wide
bandwidth, and the very high off isolation and crosstalk
rejection.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
FN6047.9
October 8, 2010
12
ISL84051, ISL84052, ISL84053
purpose of using a low r
switch, so two small signal
Logic-Level Thresholds
ON
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.7V
to 10V. At 12V the V level is about 3.5V. This is still below
IH
the CMOS guaranteed high output minimum level of 4V, but
noise margin is reduced. For best results with a 12V supply,
use a logic family that provides a V
greater than 4V.
OH
OPTIONAL
PROTECTION
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
OPTIONAL PROTECTION
DIODE
RESISTOR
FOR LOGIC
INPUTS
V+
1kΩ
LOGIC
High-Frequency Performance
V
V
In 50Ω systems, signal response is reasonably flat even past
100MHz (see Figure 17). Figure 17 also illustrates that the
frequency response is very consistent over varying analog
signal levels.
NO OR NC
COM
V-
OPTIONAL PROTECTION
DIODE
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off isolation is the
resistance to this feed through, while crosstalk indicates the
amount of feed through from one switch to another.
Figure 18 details the high off isolation and crosstalk rejection
provided by this family. At 10MHz, off isolation is about 55dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8405x construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL8405x 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
This family of switches performs equally well when operated
with bipolar or single voltage supplies. The minimum
recommended supply voltage is 2V or ±2V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specification” tables beginning on page 5 and
“Typical Performance Curves” beginning on page 14 for
details.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
FN6047.9
October 8, 2010
13
ISL84051, ISL84052, ISL84053
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
225
200
70
60
50
40
30
V
= (V+) - 1V
I
= 1mA
V- = -5V
COM
= 1mA
COM
I
COM
175
150
+85°C
+85°C
+25°C
-40°C
125
100
+25°C
-40°C
V+ = 2.7V
V- = 0V
75
160
140
120
100
80
20
400
V- = 0V
+85°C
+25°C
-40°C
300
200
100
0
V+ = 3.3V
V- = 0V
60
100
90
80
70
60
50
40
+85°C
V+ = 5V
V- = 0V
+25°C
+85°C
1
+25°C
-40°C
-40°C
0
2
3
4
5
3
4
5
6
7
8
9
10
11
12
2
V
(V)
COM
V+ (V)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
2
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE
120
110
100
90
V
= ±2V
S
I
= 1mA
COM
+85°C
80
70
60
+25°C
-40°C
1
50
90
80
70
60
50
40
30
V
= ±3V
0
S
+85°C
V+ = 5V
V- = 0V
+25°C
-40°C
-1
V
= ±5V
S
60
50
40
30
20
V
= ±5V
-2
-3
S
+85°C
+25°C
-40°C
-4
-5
-2.5
0
2.5
5
-5
-3
-2
-1
0
1
2
3
4
5
V
(V)
COM
V
(V)
COM
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
500
200
V
= (V+) - 1V
COM
V- = -5V
-40°C
+25°C
V
= (V+) - 1V
V- = -5V
COM
400
300
200
100
150
100
50
-40°C
+25°C
+25°C
+85°C
+25°C
+85°C
-40°C
0
-40°C
0
250
100
V- = 0V
V- = 0V
80
60
40
20
0
+85°C
200
150
100
50
+85°C
+25°C
+25°C
-40°C
3
-40°C
3
0
2
4
5
6
7
8
9
10
11
12
2
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 14. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE
FIGURE 13. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE
FN6047.9
October 8, 2010
14
ISL84051, ISL84052, ISL84053
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
300
250
200
150
100
50
250
200
150
100
50
V
= (V+) - 1V
COM
V
= (V+) - 1V
COM
V- = 0V
+25°C
+25°C
+85°C
+85°C
7
-40°C
-40°C
0
0
2
3
4
5
6
2
3
4
5
6
8
9
10
11
12
13
V± (V)
V+ (V)
FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY
VOLTAGE
FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY
VOLTAGE
-10
10
20
30
40
50
60
70
80
90
V
= ±5V
V+ = 3V TO 12V or
S
V
= 0.2V
TO 5V
P-P P-P
IN
-20
-30
-40
-50
-60
-70
-80
-90
V
R
= ±2V TO ±5V
= 50Ω
S
L
3
0
ISL84053
GAIN
ISL84051
ISL84052
-3
ISL84053
0
ISOLATION
PHASE
45
90
ISL84051
ISL84052
CROSSTALK
135
180
-100
-110
100
110
R
= 50Ω
L
1M
10M
100M
600M
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 18. CROSSTALK AND OFF ISOLATION
FIGURE 17. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL84051: 193
ISL84052: 193
ISL84053: 193
PROCESS:
Si Gate CMOS
FN6047.9
October 8, 2010
15
ISL84051, ISL84052, ISL84053
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
0.25
-
L
0.51
9
SEATING PLANE
A
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
0.25
-
-A-
10.00
4.00
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN6047.9
October 8, 2010
16
ISL84051, ISL84052, ISL84053
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
-
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06
0.25
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN6047.9
October 8, 2010
17
ISL84051, ISL84052, ISL84053
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
INDEX
M
M
B
0.25(0.010)
H
AREA
E
INCHES
MILLIMETERS
GAUGE
PLANE
-B-
SYMBOL
MIN
MAX
MIN
1.55
0.102
1.40
0.20
0.191
4.80
3.81
MAX
1.73
0.249
1.55
0.31
0.249
4.98
3.99
NOTES
A
A1
A2
B
0.061
0.004
0.055
0.008
0.0075
0.189
0.150
0.068
0.0098
0.061
0.012
0.0098
0.196
0.157
-
1
2
3
-
L
-
0.25
0.010
SEATING PLANE
A
9
-A-
D
h x 45°
C
D
E
-
3
-C-
4
α
A2
e
A1
e
0.025 BSC
0.635 BSC
-
C
B
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
-
0.10(0.004)
M
M
S
B
0.17(0.007)
C
A
5
L
6
NOTES:
N
α
16
16
7
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
0°
8°
0°
8°
-
Rev. 2 6/04
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6047.9
October 8, 2010
18
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