ISPLSI2096-100LQ [ROCHESTER]
EE PLD, 13 ns, PQFP128, PLASTIC, QFP-128;
| 型号： | ISPLSI2096-100LQ |
| 厂家： | 
Rochester Electronics |
| 描述： | EE PLD, 13 ns, PQFP128, PLASTIC, QFP-128 时钟 输入元件 可编程逻辑 |
| 文件： | 总13页 (文件大小：1102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Lead-
ee
Fr
Package
®
Options
vailable!
ispLSI 2096/A
A
In-System Programmable High Density PLD
Features
Functional Block Diagram
• ENHANCEMENTS
— ispLSI 2096A is Fully Form and Function Compatible
to the ispLSI 2096, with Identical Timing
Specifcations and Packaging
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C3 C2 C1 C0
C7
C6
C5
C4
A0
A1
A2
A3
B7
B6
B5
B4
— ispLSI 2096A is Built on an Advanced 0.35 Micron
D
D
D
D
Q
Q
Q
Q
E2CMOS® Technology
Logic
Array
• HIGH DENSITY PROGRAMMABLE LOGIC
Global Routing Pool
(GRP)
GLB
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
A4
A5
A6
A7
B0
B1
B2
B3
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
Description
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
The ispLSI 2096 and 2096A are High Density Program-
mable Logic Devices. The devices contain 96 Registers,
96 Universal I/O pins, six Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2096 and 2096A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2096 and 2096A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…C7
(Figure1). Thereareatotalof24GLBsintheispLSI2096
and 2096A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/ExclusiveORarray, andfouroutputswhichcan
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
— Complete Programmable Device Can Combine
Glue Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Copyright©2006LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
2096_09
1
Specifications ispLSI 2096/A
Functional Block Diagram
Figure 1. ispLSI 2096/A Functional Block Diagram
Input Bus
Input Bus
Output Routing Pool (ORP)
Megablock
Output Routing Pool (ORP)
Generic Logic
Blocks (GLBs)
C7
C6
C5
C4
C3
C2
C1
C0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 63
I/O 62
I/O 61
I/O 60
A0
A1
A2
A3
B7
B6
B5
B4
Global
Routing
Pool
I/O 4
I/O 5
I/O 6
I/O 7
I/O 59
I/O 58
I/O 57
I/O 56
I/O 8
I/O 9
I/O 10
I/O 11
I/O 55
I/O 54
I/O 53
I/O 52
(GRP)
I/O 12
I/O 13
I/O 14
I/O 15
I/O 51
I/O 50
I/O 49
I/O 48
SDI/IN 0
MODE/IN 1
A4
A5
A6
A7
B0
B1
B2
B3
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
SDO
RESET
ispEN
0917
The devices also have 96 I/O cells, each of which is The GRP has as its inputs, the outputs from all of the
directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells.
individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the
output or bi-directional I/O pin with 3-state control. The GLBs. Delays through the GRP have been equalized to
signal levels are TTL compatible voltages and the output minimize timing skew.
drivers can source 4 mA or sink 8 mA. Each output can
Clocks in the ispLSI 2096 and 2096A devices are se-
be programmed independently for fast or slow output
lected using the dedicated clock pins. Three dedicated
slew rate to minimize overall output switching noise.
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
Eight GLBs, 32 I/O cells, two dedicated inputs and two selected on a GLB basis. The asynchronous or Product
ORPs are connected together to make a Megablock TermclockcanbegeneratedinanyGLBforitsownclock.
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI2096and2096AdevicecontainsthreeMegablocks.
2
Specifications ispLSI 2096/A
1
Absolute Maximum Ratings
Supply Voltage V ...................................-0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Commercial
Industrial
MIN.
4.75
4.5
0
MAX.
5.25
5.5
UNITS
V
V
V
V
T = 0°C to + 70°C
A
Vcc
Supply Voltage
T = -40°C to + 85°C
A
Input Low Voltage
Input High Voltage
0.8
VIL
VIH
2.0
V +1
cc
Table 2 - 0005/2096
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
VCC = 5.0V, VI/O, IN = 2.0V
I/O and Dedicated Input Capacitance
Clock Capacitance
8
pf
pf
C1
C2
15
VCC= 5.0V, VY= 2.0V
Table 2-0006a
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
MAXIMUM
UNITS
Years
Cycles
–
–
Erase/Reprogram Cycles
10000
Table 2-0008A-isp
3
Specifications ispLSI 2096/A
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
+ 5V
-125
Others
≤ 2 ns
≤ 3 ns
Input Rise and Fall Time
10% to 90%
R
1
2
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
1.5V
Device
Output
Test
Point
See Figure 2
Table 2-0003/2096
3-state levels are measured 0.5V from
steady-state active level.
R
C *
L
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
470Ω
∞
R2
CL
*C includes Test Fixture and Probe Capacitance.
L
0213/2096
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
Active High
Active Low
470Ω
Active High to Z
∞
390Ω
390Ω
5pF
5pF
at VOH-0.5V
C
Active Low to Z
at VOL+0.5V
470Ω
Table 2-0004/2096
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL= 8 mA
MIN.
–
TYP. MAX. UNITS
–
–
0.4
–
V
VOL
VOH
IIL
IOH = -4 mA
2.4
–
V
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
0V ≤ V ≤ V (Max.)
–
-10
10
μA
μA
μA
μA
mA
mA
mA
IN
IL
3.5V ≤ V ≤ V
–
–
IIH
IN
CC
0V ≤ V ≤ V (Max.)
–
–
-150
-150
-200
295
–
IIL-isp
IIL-PU
IOS1
ICC2, 4
IN
IL
0V ≤ V ≤ V
–
–
IN
IL
Output Short Circuit Current
V = 5V, VOUT = 0.5V
–
–
CC
–
150
150
Commercial
Industrial
V = 0.0V, V = 3.0V
IL
IH
Operating Power Supply Current
fCLOCK = 1 MHz
–
Table 2-0007/2096
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at VCC= 5V and T = 25°C.
A
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC
.
4
Specifications ispLSI 2096/A
External Timing Parameters
Over Recommended Operating Conditions
TEST4
COND.
-125
-100
-80
2
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback3
–
–
7.5
10.0
–
–
–
10.0
13.0
–
–
–
15.0
18.5
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
2
3
4
5
6
7
8
9
pd2
125
100
125
5.0
–
100
77.0
100
6.5
–
81.0
57.0
83.0
9.0
–
MHz
MHz
MHz
ns
max
1
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
–
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
–
A
–
4.0
–
5.0
–
6.5
–
ns
co1
0.0
6.0
–
0.0
8.0
–
0.0
11.0
–
ns
h1
–
–
–
–
ns
su2
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
4.5
–
6.0
–
8.0
–
ns
co2
–
0.0
–
0.0
–
0.0
–
ns
h2
A
–
10.0
–
13.5
–
17.0
–
ns
r1
5.0
–
6.5
–
10.0
–
ns
rw1
B
C
B
C
–
14 Product Term OE, Enable
12.0
12.0
7.0
7.0
–
15.0
15.0
9.0
9.0
–
18.0
18.0
12.0
12.0
–
ns
ptoeen
ptoedis
goeen
goedis
wh
15 Product Term OE, Disable
–
–
–
ns
16 Global OE, Enable
–
–
–
ns
17 Global OE, Disable
–
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
4.0
4.0
5.0
5.0
6.0
6.0
ns
–
–
–
–
ns
wl
Table 2-0030/2096
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
Specifications ispLSI 2096/A
Internal Timing Parameters1
Over Recommended Operating Conditions
-125
MIN. MAX. MIN. MAX. MIN. MAX.
-100
-80
2
PARAMETER
#
DESCRIPTION
UNITS
Inputs
20 Input Buffer Delay
–
–
0.2
1.5
–
–
0.5
2.2
–
–
1.8
4.4
ns
ns
t
t
io
21 Dedicated Input Delay
din
GRP
22 GRP Delay
–
1.3
–
1.7
–
2.6
ns
t
grp
GLB
23 4 Product Term Bypass Comb. Path Delay
24 4 Product Term Bypass Reg. Path Delay
–
–
–
4.5
5.0
5.7
–
–
–
5.8
5.8
6.8
–
–
–
8.1
6.8
8.0
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
1 Product Term/XOR Path Delay
25
26
27
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay3
–
–
6.0
6.5
0.5
–
–
–
7.3
8.0
0.5
–
–
–
8.8
9.8
1.3
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20ptxor
xoradj
gbp
28 GLB Register Bypass Delay
29
–
–
–
GLB Register Setup Time before Clock
0.8
3.0
–
1.2
4.0
–
1.4
6.0
–
gsu
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
–
–
–
gh
0.2
1.1
4.8
7.3
0.3
1.3
6.1
8.6
0.4
1.6
8.6
9.0
gco
32
33
GLB Register Reset to Output Delay
–
–
–
gro
GLB Product Term Reset to Register Delay
–
–
–
ptre
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
–
–
–
ptoe
ptck
3.3 5.6
4.1 7.1 5.6 10.2
ORP
36 ORP Delay
–
–
0.8
0.3
–
–
1.4
0.4
–
–
2.0
0.5
ns
ns
t
t
orp
37 ORP Bypass Delay
orpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
1.2
10.0
3.2
–
–
–
–
–
1.6
10.0
4.2
–
–
–
–
–
2.0
10.0
4.6
ns
ns
ns
ns
ns
t
t
t
t
t
ob
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
3.2
4.2
4.6
3.8
4.8
7.4
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. Clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3 2.3
2.3 2.3
2.7 2.7
2.7 2.7
3.6 3.6
3.6 3.6
ns
ns
t
t
gy0
gy1/2
Global Reset
45 Global Reset to GLB
–
6.9
–
9.2
–
11.4
Table 2-0036/2096
ns
t
gr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Specifications ispLSI 2096/A
ispLSI 2096/A Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0,1
0491/2000
Derivations of
t
su,
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (
= (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
3.5 ns = (0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
= Clock (max) + Reg h - Logic
= ( io + grp + ptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
th and tco from the Product Term Clock
t
t
t
su
t
t
t
t
tio + tgrp + tptck(min))
h
t
t
t
= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
2.6 ns = (0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
co
= Clock (max) + Reg co + Output
= ( io + grp + ptck(max)) + ( gco) + (
= (#20+ #22+ #35) + (#31) + (#36 + #38)
9.3 ns = (0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
t
t
t
t
torp + tob)
Note: Calculations are based upon timing specifications for the ispLSI 2096/A-125L.
Table 2-0042B/2096
7
Specifications ispLSI 2096/A
Power Consumption
Power consumption in the ispLSI 2096 and 2096A de- used. Figure 4 shows the relationship between power
vices depends on two primary factors: the speed at which and operating speed.
the device is operating and the number of Product Terms
Figure 4. Typical Device Power Consumption vs fmax
300
250
200
150
100
50
ispLSI 2096/A
0
20
40 60
80 100 120 140
f
max (MHz)
Notes: Configuration of six 16-bit counters
Typical current at 5V, 25°C
I
I
can be estimated for the ispLSI 2096/A using the following equation:
CC
CC
(mA) = 20 + (# of PTs 0.67) + (# of nets Max freq 0.011)
*
*
*
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of two GLB loads
CC
CC
on average exists. These values are for estimates only. Since the value of I
and the program in the device, the actual I
is sensitive to operating conditions
CC
should be verified.
CC
0127/2096
8
Specifications ispLSI 2096/A
Pin Description
NAME
PQFP & TQFP PIN NUMBERS
DESCRIPTION
24,
30,
25,
31,
26
32
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
23,
29,
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
36,
37,
38,
39
43,
44,
45
42,
55,
56,
57
54,
61,
62,
63
60,
69,
70,
71
68,
75,
76,
77
74,
88,
89,
90
87,
94,
95,
96
93,
101,
107,
120,
126,
5,
102,
108,
121,
127,
6,
103
109
122
128
7
100,
106,
119,
125,
4,
104, 105,
117, 118,
123, 124,
2,
8,
3,
9,
11,
12,
13
10,
GOE 0, GOE 1
Global Output Enables input pins.
Dedicated input pins to the device.
64, 114
IN 2, IN 4, IN 5
ispEN
51,
18
84,
110
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
2
SDI/IN 0
20
46
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN0 also is used as one of the two control pins for the isp state
machine. When ispEN is high, it functions as a dedicated input pin.
2
MODE/IN 1
Input - This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the isp state machine.
When ispEN is high, it functions as a dedicated input pin.
SDO
50
78
Output - When ispEN is logic low, it functions as an output pin to read
serial shift register data.
2
SCLK/IN 3
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
RESET
19
15
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Y0, Y1, Y2
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
83,
17,
80
1,
33,
49,
65,
81,
GND
VCC
Ground (GND)
97, 112
V
16,
14,
48,
47,
82,
79,
113
CC
1
NC
No Connect.
111,
115,
116
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Table 2-0002-2096
9
Specifications ispLSI 2096/A
Pin Configuration
ispLSI 2096/A 128-pin PQFP and TQFP Pinout Diagram
GND
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
1NC
1
2
3
4
5
96
95
94
93
92
91
90
89
88
87
86
85
84
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
6
7
8
9
10
11
12
13
14
Y1
VCC
GND
83
82
Y0
VCC
GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ispLSI 2096/A
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Y2
NC1
Top View
ispEN
RESET
2SDI/IN 0
I/O 0
SCLK/IN 32
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
GND
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
0124A-2096
10
Specifications ispLSI 2096/A
Part Number Description
ispLSI XXXXX – XXX X
X
X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
Device Number
20961
2096A
T = TQFP
Q = PQFP
Speed
TN = Lead-Free TQFP
QN = Lead-Free PQFP
125 = 125 MHz
100 = 100 MHz
80 = 81 MHz fmax
f
f
max
max
Power
L = Low
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
ispLSI 2096/A Ordering Information
Conventional Packaging
COMMERCIAL
FAMILY
fmax (MHz)
125
tpd (ns)
7.5
ORDERING NUMBER
ispLSI 2096A-125LQ128
ispLSI 2096A-125LT128
ispLSI 2096A-100LQ128
ispLSI 2096A-100LT128
ispLSI 2096A-80LQ128
ispLSI 2096A-80LT128
PACKAGE
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
125
7.5
100
100
81
10
10
15
15
81
ispLSI
125
125
7.5
7.5
ispLSI 2096-125LQ1
ispLSI 2096-125LT1
ispLSI 2096-100LQ1
ispLSI 2096-100LT1
ispLSI 2096-80LQ1
ispLSI 2096-80LT1
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
128-Pin PQFP
128-Pin TQFP
100
100
81
10
10
15
15
81
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
15
ORDERING NUMBER
ispLSI 2096A-80LQ128I
ispLSI 2096A-80LT128I
PACKAGE
128-Pin PQFP
128-Pin TQFP
81
81
15
81
81
15
15
ispLSI 2096-80LQI1
ispLSI 2096-80LTI1
128-Pin PQFP
128-Pin TQFP
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
11
Specifications ispLSI 2096/A
ispLSI 2096/A Ordering Information (Cont.)
Lead-Free Packaging
COMMERCIAL
FAMILY
fmax (MHz)
125
tpd (ns)
7.5
ORDERING NUMBER
ispLSI 2096A-125LQN128
ispLSI 2096A-125LTN128
ispLSI 2096A-100LQN128
ispLSI 2096A-100LTN128
ispLSI 2096A-80LQN128
ispLSI 2096A-80LTN128
PACKAGE
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
125
7.5
100
100
81
10
10
15
15
ispLSI
81
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
15
ORDERING NUMBER
ispLSI 2096A-80LQN128I
ispLSI 2096A-80LTN128I
PACKAGE
81
81
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
15
Revision History
Date
—
Version
Change Summary
Previous Lattice release.
08
August 2006
09
Updated for lead-free package options.
12
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