LP38842S-0.8/NOPB [ROCHESTER]
0.8V FIXED POSITIVE LDO REGULATOR, 0.315V DROPOUT, PSSO5, TO-263, 5 PIN;
| 型号： | LP38842S-0.8/NOPB |
| 厂家： | 
Rochester Electronics |
| 描述： | 0.8V FIXED POSITIVE LDO REGULATOR, 0.315V DROPOUT, PSSO5, TO-263, 5 PIN 输出元件 调节器 |
| 文件： | 总12页 (文件大小：1327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2006
LP38842
1.5A Ultra Low Dropout Linear Regulators
Stable with Ceramic Output Capacitors
General Description
Features
n Ideal for conversion from 1.8V or 1.5V inputs
n Designed for use with low ESR ceramic capacitors
n 0.8V, 1.2V and 1.5V standard voltages available
The LP38842 is a high current, fast response regulator
which can maintain output voltage regulation with minimum
input to output voltage drop. Fabricated on a CMOS process,
the device operates from two input voltages: Vbias provides
voltage to drive the gate of the N-MOS power transistor,
while Vin is the input voltage which supplies power to the
load. The use of an external bias rail allows the part to
operate from ultra low Vin voltages. Unlike bipolar regula-
tors, the CMOS architecture consumes extremely low quies-
cent current at any output load current. The use of an
N-MOS power transistor results in wide bandwidth, yet mini-
mum external capacitance is required to maintain loop sta-
bility.
@
n Ultra low dropout voltage (115mV 1.5A typ)
n 1.5% initial output accuracy
n Load regulation of 0.1%/A (typical)
n 30nA quiescent current in shutdown (typical)
n Low ground pin current at all loads
n Over temperature/over current protection
n Available in 5 lead TO220 and TO263 packages
n −40˚C to +125˚C junction temperature range
The fast transient response of these devices makes them
suitable for use in powering DSP, Microcontroller Core volt-
ages and Switch Mode Power Supply post regulators. The
parts are available in TO-220 and TO-263 packages.
Applications
n ASIC Power Supplies In:
- Desktops, Notebooks, and Graphics Cards, Servers
- Gaming Set Top Boxes, Printers and Copiers
n Server Core and I/O Supplies
@
Dropout Voltage: 115 mV (typ) 1.5A load current.
Quiescent Current: 30 mA (typ) at full load.
n DSP and FPGA Power Supplies
n SMPS Post-Regulator
Shutdown Current: 30 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature accu-
racy.
Typical Application Circuit
20103001
* Minimum value required if Tantalum capacitor is used (see Application Hints).
© 2006 National Semiconductor Corporation
DS201030
www.national.com
Connection Diagrams
20103002
20103003
TO-220, Top View
TO-263, Top View
Pin Descriptions
Pin Name
Description
BIAS
The bias pin is used to provide the low current bias voltage to the chip which operates the internal
circuitry and provides drive voltage for the N-FET.
OUTPUT
GND
The regulated output voltage is connected to this pin.
This is both the power and analog ground for the IC. Note that both pin three and the tab of the
TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together
using the PC board copper trace material and connected to circuit ground.
The high current input voltage which is regulated down to the nominal output voltage must be
connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input
voltage can be as low as a few hundered millivolts above the output voltage.
This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if
this function is not used.
INPUT
SHUTDOWN
Ordering Information
Order Number
LP38842S-0.8
Package Type
TO263-5
TO263-5
TO220-5
TO220-5
TO263-5
TO263-5
TO220-5
TO220-5
TO263-5
TO263-5
TO220-5
TO220-5
Package Drawing
TS5B
Supplied As
Rail
LP38842SX-0.8
LP38842T-0.8
TS5B
Tape and Reel
T05A
Rail
LP38842T-0.8 LB03
LP38842S-1.2
T05D
Rail
TS5B
Rail
Tape and Reel
Rail
LP38842SX-1.2
LP38842T-1.2
TS5B
T05A
LP38842T-1.2 LB03
LP38842S-1.5
T05D
Rail
TS5B
Rail
LP38842SX-1.5
LP38842T-1.5
TS5B
Tape and Reel
Rail
T05A
LP38842T-1.5 LB03
T05D
Rail
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2
Block Diagram
20103024
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
IOUT (Survival)
Internally Limited
−0.3V to +6V
Output Voltage (Survival)
Junction Temperature
−40˚C to +150˚C
Storage Temperature Range
Lead Temp. (Soldering, 5 seconds)
ESD Rating
−65˚C to +150˚C
260˚C
Operating Ratings
VIN Supply Voltage
Shutdown Input Voltage
IOUT
(VOUT + VDO) to 5.5V
0 to +5.5V
Human Body Model (Note 3)
Machine Model (Note 9)
2 kV
200V
1.5A
Operating Junction
Temperature Range
VBIAS Supply Voltage
VOUT
−40˚C to +125˚C
Power Dissipation (Note 2)
VIN Supply Voltage (Survival)
VBIAS Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
Internally Limited
−0.3V to +6V
−0.3V to +7V
−0.3V to +7V
4.5V to 5.5V
0.8V to 1.5V
Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN
10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical
correlation, or design.
=
Typ
(Note 4)
Symbol
VO
Parameter
Conditions
Min
Max
Units
<
<
Output Voltage Tolerance
10 mA IL 1.5A
0.788
0.776
1.182
1.164
1.478
1.455
0.812
0.824
1.218
1.236
1.523
1.545
0.8
VO(NOM) + 1V ≤ VIN ≤ 5.5V
4.5V ≤ VBIAS ≤ 5.5V
1.2
1.5
0.01
0.1
115
30
V
∆VO/∆VIN
∆VO/∆IL
VDO
Output Voltage Line Regulation
(Note 6)
VO(NOM) + 1V ≤ VIN ≤ 5.5V
%/V
%/A
mV
mA
µA
<
<
Output Voltage Load Regulation 10 mA IL 1.5A
0.4
1.1
175
315
35
40
1
(Note 7)
Dropout Voltage (Note 8)
IL = 1.5A
<
<
IQ(VIN
)
Quiescent Current Drawn from
VIN Supply
10 mA IL 1.5A
V
≤ 0.3V
S/D
0.06
2
30
4
<
<
IQ(VBIAS
)
Quiescent Current Drawn from
VBIAS Supply
10 mA IL 1.5A
mA
6
V
≤ 0.3V
1
S/D
0.03
4
µA
A
30
ISC
Short-Circuit Current
VOUT = 0V
Shutdown Input
VSDT
Output Turn-off Threshold
Output = ON
Output = OFF
RLOAD X COUT
RLOAD X COUT
V S/D =1.3V
0.7
0.7
20
15
1
1.3
V
µs
0.3
<<
<<
Td (OFF)
Td (ON)
IS/D
Turn-OFF Delay
Turn-ON Delay
S/D Input Current
Td (OFF)
Td (ON)
µA
V
≤ 0.3V
−1
65
35
S/D
θJ-A
Junction to Ambient Thermal
Resistance
TO-220, No Heatsink
˚C/W
TO-263, 1 sq.in Copper
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4
Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN
=
10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical
correlation, or design. (Continued)
Typ
(Note 4)
Symbol
Parameter
Conditions
Min
Max
Units
AC Parameters
PSRR (VIN
)
Ripple Rejection for VIN Input
Voltage
VIN = VOUT +1V, f = 120 Hz
80
65
58
VIN = VOUT + 1V, f = 1 kHz
dB
PSRR
Ripple Rejection for VBIAS
Voltage
VBIAS = VOUT + 3V, f = 120 Hz
(VBIAS
)
VBIAS = VOUT + 3V, f = 1 kHz
f = 120 Hz
58
1
en
Output Noise Density
Output Noise Voltage
VOUT = 1.5V
µV/root−Hz
µV (rms)
BW = 10 Hz − 100 kHz
BW = 300 Hz − 300 kHz
150
90
Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θ
for TO-220
J-A
devices is 65˚C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θ
value of 4˚C/W can be assumed. θ
for TO-263 devices is
J-S
J-A
approximately 35˚C/W if soldered down to a copper plane which is at least 1 square inches in area. If power dissipation causes the junction temperature to exceed
specified limits, the device will go into thermal shutdown.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.
Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.
Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.
Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.
Note 9: The machine model is a 220 pF capacitor discharged directly into each pin.
5
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Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, CIN = 10 µF CER,
COUT = 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V.
VBIAS Transient Response
Load Transient Response
20103036
20103037
Load Transient Response
Dropout Voltage Over Temperature
20103038
20103039
VOUT vs Temperature
VBIAS PSRR
20103040
20103041
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6
Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, CIN = 10 µF CER, COUT
= 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT
1V. (Continued)
+
VBIAS PSRR
VIN PSRR
20103042
20103051
Output Noise Voltage
20103043
7
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POWER DISSIPATION/HEATSINKING
Application Hints
A heatsink may be required depending on the maximum
power dissipation and maximum ambient temperature of the
application. Under all possible conditions, the junction tem-
perature must be within the range specified under operating
conditions. The total power dissipation of the device is given
by:
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are
required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
PD = (VIN−VOUT)IOUT+ (VIN)IGND
An output capacitor is required on the LP3884X devices for
loop stability. The minimum value of capacitance necessary
depends on type of capacitor: if a solid Tantalum capacitor is
used, the part is stable with capacitor values as low as 4.7µF.
If a ceramic capacitor is used, a minimum of 22 µF of
capacitance must be used (capacitance may be increased
without limit). The reason a larger ceramic capacitor is re-
quired is that the output capacitor sets a pole which limits the
loop bandwidth. The Tantalum capacitor has a higher ESR
than the ceramic which provides more phase margin to the
loop, thereby allowing the use of a smaller output capacitor
because adequate phase margin can be maintained out to a
higher crossover frequency. The tantalum capacitor will typi-
cally also provide faster settling time on the output after a
fast changing load transient occurs, but the ceramic capaci-
tor is superior for bypassing high frequency noise.
where IGND is the operating ground current of the device.
The maximum allowable temperature rise (TRmax) depends
on the maximum ambient temperature (TAmax) of the appli-
cation, and the maximum allowable junction temperature
(TJmax):
TRmax = TJmax− TAmax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θJA, can be calculated using the formula:
θJA = TRmax / PD
These parts are available in TO-220 and TO-263 packages.
The thermal resistance depends on amount of copper area
or heat sink, and on air flow. If the maximum allowable value
of θJA calculated above is ≥ 60 ˚C/W for TO-220 package
and ≥ 60 ˚C/W for TO-263 package no heatsink is needed
since the package can dissipate enough heat to satisfy these
requirements. If the value for allowable θJA falls below these
limits, a heat sink is required.
The output capacitor must be located less than one centi-
meter from the output pin and returned to a clean analog
ground. Care must be taken in choosing the output capacitor
to ensure that sufficient capacitance is provided over the full
operating temperature range. If ceramics are selected, only
X7R or X5R types may be used because Z5U and Y5F types
suffer severe loss of capacitance with temperature and ap-
plied voltage and may only provide 20% of their rated ca-
pacitance in operation.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θJA will
be same as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
INPUT CAPACITOR
The input capacitor is also critical to loop stability because it
provides a low source impedance for the regulator. The
minimum required input capacitance is 10 µF ceramic (Tan-
talum not recommended). The value of CIN may be in-
creased without limit. As stated above, X5R or X7R must be
used to ensure sufficient capacitance is provided. The input
capacitor must be located less than one centimeter from the
input pin and returned to a clean analog ground.
θHA≤ θJA − θCH − θJC
.
In this equation, θCH is the thermal resistance from the case
to the surface of the heat sink and θJC is the thermal resis-
tance from the junction to the surface of the case. θJC is
about 3˚C/W for a TO220 package. The value for θCH de-
pends on method of attachment, insulator, etc. θCH varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
BIAS CAPACITOR
HEATSINKING TO-263 PACKAGE
The 0.1µF capacitor on the bias line can be any good quality
capacitor (ceramic is recommended).
The TO-263 package uses the copper plane on the PCB as
a heatsink. The tab of this package is soldered to the copper
plane for heat sinking. The graph below shows a curve for
the θJA of TO-263 package for different copper area sizes,
using a typical PCB with 1 ounce copper and no solder mask
over the copper area for heat sinking.
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get
gate drive for the N-FET pass transistor. Bias voltage must
be in the range of 4.5 - 5.5V to assure proper operation of
the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
regulator output from turning on if the bias voltage is below
approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regula-
tor. Pin S/D must be actively terminated through a pull-up
resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin
is driven from a source that actively pulls high and low (such
as a CMOS rail to rail comparator), the pull-up resistor is not
required. This pin must be tied to VBIAS if not used.
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8
Figure 2 shows the maximum allowable power dissipation
for TO-263 packages for different ambient temperatures,
assuming θJA is 35˚C/W and the maximum junction tempera-
ture is 125˚C.
Application Hints (Continued)
20103025
20103026
FIGURE 1. θJA vs Copper (1 Ounce) Area for TO-263
package
FIGURE 2. Maximum power dissipation vs ambient
temperature for TO-263 package
As shown in the graph below, increasing the copper area
beyond 1 square inch produces very little improvement. The
minimum value for θJA for the TO-263 package mounted to a
PCB is 32˚C/W.
9
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Physical Dimensions inches (millimeters) unless otherwise noted
TO220 5-lead, Molded, Stagger Bend Package (TO220-5)
NS Package Number T05D
TO220 5-lead, Molded, Straight Lead Package (TO220-5)
NS Package Number T05A
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
TO263 5-Lead, Molded, Surface Mount Package (TO263-5)
NS Package Number TS5B
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
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