MAX1036MEKA
更新时间:2024-09-18 15:04:38
品牌:ROCHESTER
描述:4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MO-178, SOT-23, 8 PIN
MAX1036MEKA 概述
4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MO-178, SOT-23, 8 PIN 模数转换器
MAX1036MEKA 规格参数
生命周期: | Active | 零件包装代码: | SOIC |
包装说明: | LSSOP, | 针数: | 8 |
Reach Compliance Code: | unknown | 风险等级: | 5.66 |
最大模拟输入电压: | 2.048 V | 最小模拟输入电压: | -2.048 V |
最长转换时间: | 6.1 µs | 转换器类型: | ADC, SUCCESSIVE APPROXIMATION |
JESD-30 代码: | R-PDSO-G8 | 长度: | 2.9 mm |
最大线性误差 (EL): | 0.3906% | 模拟输入通道数量: | 4 |
位数: | 8 | 功能数量: | 1 |
端子数量: | 8 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 输出位码: | BINARY, 2'S COMPLEMENT BINARY |
输出格式: | SERIAL | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | LSSOP | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE, LOW PROFILE, SHRINK PITCH | 采样速率: | 0.188 MHz |
采样并保持/跟踪并保持: | TRACK | 座面最大高度: | 1.45 mm |
标称供电电压: | 5 V | 表面贴装: | YES |
技术: | BICMOS | 温度等级: | INDUSTRIAL |
端子形式: | GULL WING | 端子节距: | 0.65 mm |
端子位置: | DUAL | 宽度: | 1.625 mm |
Base Number Matches: | 1 |
MAX1036MEKA 数据手册
通过下载MAX1036MEKA数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载19-2442; Rev 1; 10/02
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
General Description
Features
o High-Speed I2C-Compatible Serial Interface
The MAX1036–MAX1039 low-power, 8-bit, multichannel,
analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. Auto-
Shutdown™ powers down the devices between conver-
sions reducing supply current to less than 1µA at low
throughput rates. The MAX1036/MAX1037 have four ana-
log input channels each, while the MAX1038/MAX1039
have twelve analog input channels. The analog inputs are
software configurable for unipolar or bipolar and single-
ended or pseudo-differential operation.
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single Supply
2.7V to 3.6V (MAX1037/MAX1039)
4.5V to 5.5V (MAX1036/MAX1038)
o Internal Reference
2.048V (MAX1037/MAX1039)
4.096V (MAX1036/MAX1038)
o External Reference: 1V to V
DD
o Internal Clock
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V . The MAX1037/
DD
MAX1039 feature a 2.048V internal reference and the
MAX1036/MAX1038 feature a 4.096V internal reference.
o 4-Channel Single-Ended or 2-Channel Pseudo-
Differential (MAX1036/MAX1037)
o 12-Channel Single-Ended or 6-Channel Pseudo-
Differential (MAX1038/MAX1039)
The MAX1036/MAX1037 are available in 8-pin SOT23
packages. The MAX1038/MAX1039 are available in 16-
pin QSOP packages. The MAX1036–MAX1039 are guar-
anteed over the extended industrial temperature range
(-40°C to +85°C). Refer to MAX1136–MAX1139 for 10-bit
devices and to the MAX1236–MAX1239 for 12-bit
devices.
o Internal FIFO with Channel-Scan Mode
o Low Power
350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode
Applications
o Software Configurable Unipolar/Bipolar
Hand-Held Portable Applications
o Small Packages
Medical Instruments
8-Pin SOT23 (MAX1036/MAX1037)
16-Pin QSOP (MAX1038/MAX1039)
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Pin Configurations and Typical Operating Circuit appear
at end of data sheet.
Ordering Information
TUE
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
TOP
MARK
PART
TEMP RANGE
PIN-PACKAGE
MAX1036EKA-T
MAX1037EKA-T
MAX1038AEEE
MAX1039AEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 SOT23-8
8 SOT23-8
16 QSOP
16 QSOP
±2
±2
±1
±1
4
4
4.096
2.048
4.096
2.048
AAJE
AAJG
—
12
12
—
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
AIN0–AIN11, REF to
GND ......................-0.3V to the lower of (V
+ 0.3V) and +6V
DD
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin......................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW
16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 3.6V (MAX1037/MAX1039), V
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
= 2.048V
REF
DD
DD
(MAX1037/MAX1039), V
= 4.096V (MAX1036/MAX1038). External clock, f
= 1.7MHz, T = T
to T
, unless otherwise
REF
SCL
A
MIN
MAX
noted. Typical values are at T = +25°C.)
A
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
Bits
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Offset Error
INL
(Note 2)
No missing codes over temperature
1
1
DNL
1.5
Offset Error Temperature
Coefficient
3
ppm/°C
Gain Error
(Note 3)
1
LSB
Gain Temperature Coefficient
1
ppm/°C
MAX1036/MAX1037
0.5
0.5
2
1
Total Unadjusted Error
TUE
LSB
LSB
LSB
dB
MAX1038A/MAX1039A
Channel-to-Channel Offset
Matching
0.1
0.5
75
Channel-to-Channel Gain
Matching
Input Common-Mode Rejection
Ratio
CMRR
Pseudo-differential input mode
DYNAMIC PERFORMANCE (f
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Full-Power Bandwidth
= 25kHz, V = V
, f
= 188ksps, R = 100Ω)
IN(sinewave)
IN
REF(P-P) SAMPLE
IN
SINAD
49
-69
69
dB
dB
THD
Up to the 5th harmonic
SFDR
dB
(Note 4)
75
dB
-3dB point
SINAD > 49dB
2.0
200
MHz
kHz
Full-Linear Bandwidth
CONVERSION RATE
Internal clock
External clock
6.1
Conversion Time (Note 5)
t
µs
CONV
4.7
2
_______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1037/MAX1039), V
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
= 2.048V
REF
DD
DD
(MAX1037/MAX1039), V
= 4.096V (MAX1036/MAX1038). External clock, f
= 1.7MHz, T = T
to T
, unless otherwise
REF
SCL
A
MIN
MAX
noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal clock, SCAN[1:0] = 01
(MAX1036/MAX1037)
76
Throughput Rate
f
ksps
SAMPLE
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX1038/MAX1039)
77
External clock
188
Track/Hold Acquisition Time
Internal Clock Frequency
588
ns
2.25
45
MHz
External clock, fast mode
Aperture Delay
t
ns
V
AD
External clock, high-speed mode
30
ANALOG INPUT (AIN0–AIN11)
Unipolar
Bipolar
0
V
REF
Input Voltage Range, Single
Ended and Differential (Note 6)
V
/ 2
REF
On/off-leakage current, V _= 0 or V
AIN
DD,
Input Multiplexer Leakage Current
0.01
18
1
µA
pF
no clock, f
= 0
SCL
Input Capacitance
C
IN
INTERNAL REFERENCE (Note 7)
MAX1037/MAX1039
MAX1036/MAX1038
1.925
3.850
2.048
4.096
2.171
4.342
Reference Voltage
V
T
= +25°C
A
V
REF
Reference Temperature
Coefficient
TC
120
ppm/°C
REF
Reference Short-Circuit Current
Reference Source Impedance
EXTERNAL REFERENCE
Reference Input Voltage Range
REF Input Current
10
mA
(Note 8)
(Note 9)
675
Ω
V
1.0
V
V
REF
DD
I
f
= 188ksps
14
15
30
µA
REF
SAMPLE
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
V
0.7 x V
0.1 x V
V
V
IH
DD
DD
V
0.3 x V
DD
IL
V
V
HYST
I
V
= 0 to V
DD
10
µA
pF
V
IN
IN
Input Capacitance
Output Low Voltage
C
IN
V
I
= 3mA
0.4
OL
SINK
_______________________________________________________________________________________
3
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1037/MAX1039), V
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
= 2.048V
REF
DD
DD
(MAX1037/MAX1039), V
= 4.096V (MAX1036/MAX1038). External clock, f
= 1.7MHz, T = T
to T
, unless otherwise
REF
SCL
A
MIN
MAX
noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
MAX1037/MAX1039
MAX1036/MAX1038
2.7
4.5
3.6
5.5
650
Supply Voltage (Note 10)
V
V
DD
Internal REF, external clock
External REF, external clock
External REF, external clock
External REF, internal clock
External REF, external clock
External REF, internal clock
External REF, external clock
External REF, internal clock
350
250
110
150
8
f
=
=
=
=
SAMPLE
188ksps
f
SAMPLE
75ksps
Supply Current
I
µA
DD
f
SAMPLE
10ksps
10
2
f
SAMPLE
1ksps
2.5
1
Power-down
(Note 11)
10
1
Power-Supply Rejection Ratio
PSRR
0.25
LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1A and 2)
Serial Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
BUF
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
t
0.6
1.3
0.6
µs
µs
µs
HD, STA
t
LOW
t
HIGH
Setup Time for a Repeated START
Condition (Sr)
0.6
µs
SU, STA
Data Hold Time
Data Setup Time
t
(Note 12)
0
150
ns
ns
HD, DAT
t
100
SU, DAT
Rise Time of Both SDA and SCL
Signals, Receiving
t
(Note 13)
(Note 13)
20 + 0.1C
300
300
ns
R
B
B
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
20 + 0.1C
0.6
ns
µs
pF
ns
F
t
SU, STO
C
400
50
B
t
SP
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1B and 2)
Serial Clock Frequency
f
(Note 14)
1.7
MHz
ns
SCLH
Hold Time (Repeated) Start
Condition
t
160
HD, STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
320
120
ns
ns
LOW
t
HIGH
4
_______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX1037/MAX1039), V
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
= 2.048V
REF
DD
DD
(MAX1037/MAX1039), V
= 4.096V (MAX1036/MAX1038). External clock, f
= 1.7MHz, T = T
to T
, unless otherwise
REF
SCL
A
MIN
MAX
noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for a Repeated START
Condition (Sr)
t
,
160
ns
SU STA
Data Hold Time
Data Setup Time
t
,
(Note 12)
0
150
ns
ns
HD DAT
t
,
10
SU DAT
Rise Time of SCL Signal
(Current Source Enabled)
t
(Note 13)
(Note 13)
20
20
80
ns
ns
RCL
Rise Time of SCL Signal After
Acknowledge Bit
t
160
RCL1
Fall Time of SCL Signal
t
(Note 13)
(Note 13)
(Note 13)
20
20
80
ns
ns
ns
ns
pF
ns
FCL
Rise Time of SDA Signal
t
160
160
RDA
Fall Time of SDA Signal
t
20
FDA
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
,
160
SU STO
C
400
10
B
t
0
SP
Note 1: The MAX1036/MAX1038 are tested at V
= 5V and the MAX1037/MAX1039 are tested at V
= 3V. All devices are config-
DD
DD
ured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground ON channel; sine wave applied to all OFF channels.
Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V
.
DD
Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV
.
P-P
Note 10: Electrical characteristics are guaranteed from V
Operating Characteristics.
to V
. For operation beyond this range, see the Typical
DD(max)
DD(min)
Note 11: Power-supply rejection ratio is measured as:
N
2
V
3.3V − V 2.7V
×
(
)
(
)
]
[
FS
FS
V
REF
3.3V − 2.7V
, for the MAX1037/MAX1039 where N is the number of bits (8) and V
Power-supply rejection ratio is measured as:
= 2.048V.
= 2.048V.
REF
N
2
V
5.5V − V 4.5V
×
(
)
(
)
]
[
FS
FS
V
REF
5.5V − 4.5V
, for the MAX1036/MAX1038 where N is the number of bits (8) and V
REF
Note 12: A master device must provide a data hold time for SDA (referred to V of SCL) in order to bridge the undefined region of
IL
SCL’s falling edge (Figure 1).
Note 13: C = total capacitance of one bus line in pF. t and t measured between 0.3V
and 0.7V . Minimum specification is
DD
B
R
F
DD
tested at +25°C with C = 400pF.
B
Note 14: f
must meet the minimum clock low time plus the rise/fall times.
SCLH
_______________________________________________________________________________________
5
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Typical Operating Characteristics
(V = 3.3V (MAX1037/MAX1039), V = 5V (MAX1036/MAX1038), f
= 1.7MHz, external clock (33% duty cycle), f
= 188ksps,
SAMPLE
DD
DD
SCL
single ended, unipolar, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
450
400
350
300
250
200
150
450
400
350
300
250
200
150
5
4
3
2
1
0
SDA = SCL = V
DD
A) INTERNAL 4.096V
B) INTERNAL 2.048V
REF
REF
C) EXTERNAL 4.096V
REF
REF
A
B
INTERNAL 4.096V
D) EXTERNAL 2.048V
REF
INTERNAL 2.048V
REF
C
EXTERNAL 4.096V
REF
D
EXTERNAL 2.048V
REF
35
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
60
85
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
(V)
TEMPERATURE (°C)
V
DD
DD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
AVERAGE SUPPLY CURRENT VS.
CONVERSION RATE (EXTERNAL CLOCK)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (INTERNAL CLOCK)
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
5
4
3
2
1
0
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
SDA = SCL = V
DD
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
A
A
B
B
C
C
V
= 5V
DD
100
50
0
INTERNAL CLOCK MODE
EXTERNAL CLOCK MODE
f
= 1.7MHz
V
= 3.3V
10
SCL
f
= 1.7MHz
DD
SCL
0
-40
-15
35
60
85
0
10
20
30
40
50
60
0
50
100
150
200
TEMPERATURE (°C)
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
NORMALIZED 4.096V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.0100
INTERNAL 4.096V REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL 2.048V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.0100
1.0075
1.0050
1.0025
1.0000
0.9975
0.9950
0.9925
0.9900
1.0075
1.0050
1.0025
1.0000
0.9975
0.9950
0.9925
0.9900
4.00 4.25 4.50 4.75 5.00 5.25 5.50
(V)
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
TEMPERATURE (°C)
V
DD
DD
6
_______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(V = 3.3V (MAX1037/MAX1039), V = 5V (MAX1036/MAX1038), f
= 1.7MHz, external clock (33% duty cycle), f
= 188ksps,
SAMPLE
DD
DD
SCL
single ended, unipolar, T = +25°C, unless otherwise noted.)
A
INTERNAL 2.048V REFERENCE VOLTAGE
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
0.5
0.4
0.5
0.4
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-40
-15
10
35
60
85
0
50
100
150
200
250
300
0
50
100
150
200
250
300
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
FFT PLOT
OFFSET ERROR vs. SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-20
V
= 2.048V
f
REF
SAMPLE = 188ksps
f
IN = 25kHz
-40
-60
-80
-100
-120
0
20k
40k
60k
80k
100k
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
FREQUENCY (Hz)
V
DD
GAIN ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
V
V
= 3.3V
DD
V
= 2.048V
REF
= 2.048V
REF
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
TEMPERATURE (°C)
V
DD
_______________________________________________________________________________________
7
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
MAX1036/
MAX1037
MAX1038/
MAX1039
1, 2, 3
—
8, 7, 6
AIN0–AIN2
AIN3–AIN7
AIN8–AIN10
5, 4, 3, 2, 1
16, 15, 14
Analog Inputs
—
Analog Input 3/Reference Input or Output. Selected in the setup
register.
4
—
AIN3/REF
Analog Input 11/Reference Input or Output. Selected in the setup
register.
—
13
AIN11/REF
5
6
7
8
9
SCL
SDA
GND
Clock Input
10
11
12
Data Input/Output
Ground
V
Positive Supply. Bypass to GND with a 0.1µF capacitor.
DD
The MAX1036–MAX1039 input configuration is pseudo-
Detailed Description
differential in that only the signal at the ‘+’ analog input
is sampled with the T/H circuitry. The ‘-’ analog input
signal must remain stable within 0.5LSB ( 0.1LSB for
best results) with respect to GND during a conversion.
To accomplish this, connect a 0.1µF capacitor from ‘-’
analog input to GND. See the Single-Ended/Pseudo-
Differential Input section.
The MAX1036–MAX1039 ADCs use successive-
approximation conversion techniques and input T/H cir-
cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX1036/MAX1037 are
4-channel ADCs, and the MAX1038/MAX1039 are 12-
channel ADCs. These devices feature a high-speed 2-
wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional dia-
gram for the MAX1038/MAX1039.
During the acquisition interval, the T/H switches are in
the track position and C
charges to the analog input
T/H
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
Power Supply
The MAX1036–MAX1039 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX1037/MAX1039 feature a 2.048V internal
reference and the MAX1036/MAX1038 feature a 4.096V
internal reference. All devices can be configured for
on C
as a sample of the input signal.
T/H
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva-
use with an external reference from 1V to V
.
DD
lent to transferring a charge of 18pF ✕ (V + - V -)
IN
IN
from C
to the binary weighted capacitive DAC form-
ing a digital representation of the analog input signal.
T/H
Analog Input and Track/Hold
The MAX1036–MAX1039 analog input architecture con-
tains an analog input multiplexer (MUX), a T/H capaci-
tor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.
In single-ended mode, the analog input multiplexer con-
nects C
to the analog input selected by CS[3:0] (see
T/H
the Configuration/Setup Bytes (Write Cycle) section). The
charge on C is referenced to GND when converted. In
T/H
pseudo-differential mode, the analog input multiplexer
connects C to the ‘+’ analog input selected by
T/H
CS[3:0]. The charge on C
log input when converted.
is referenced to the ‘-’ ana-
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge
T/H
8
_______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
2
A. F/S-MODE I C SERIAL INTERFACE TIMING
t
R
t
t
F
SDA
t
SU.DAT
t
HD.DAT
t
t
BUF
HD.STA
t
LOW
t
t
SU.STA
SU.STO
SCL
t
HD.STA
t
HIGH
t
R
t
F
S
Sr
A
P
S
2
B. HS-MODE I C SERIAL INTERFACE TIMING
t
t
RDA
FDA
SDA
t
t
HD.DAT
SU.DAT
t
t
BUF
HD.STA
t
LOW
t
t
SU.STO
SU.STA
SCL
t
t
HIGH
HD.STA
t
t
FCL
t
RCL
RCL1
S
Sr
A
S
HS-MODE
F/S-MODE
2
Figure 1. I C Serial Interface Timing
of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or series of conversions are
then internally clocked (eight clock cycles per conver-
sion) and the MAX1036–MAX1039 hold SCL low. When
operating in external clock mode, the T/H circuitry
enters track mode on the seventh falling edge of a valid
slave address byte. Hold mode is then entered on the
falling edge of the eighth clock cycle. The conversion is
performed during the next eight clock cycles.
V
DD
I
= 3mA
OL
V
SDA
OUT
400pF
I
= 0mA
OH
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
Figure 2. Load Circuit
between conversions. The acquisition time (t
) is the
ACQ
minimum time needed for the signal to be acquired. It
is calculated by:
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select R
,
SOURCE
t
≥ 6.25 ✕ (R
+ R ) ✕ C
IN IN
ACQ
SOURCE
allow 625ns for t
in internal clock mode to account
ACQ
for clock frequency variations.
where R
IN
is the analog input source impedance,
SOURCE
= 2.5kΩ, and C = 18pF. t
R
is 1/f for external
SCL
IN
ACQ
_______________________________________________________________________________________
9
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
SDA
SCL
INPUT SHIFT REGISTER
V
DD
INTERNAL
OSCILLATOR
CONTROL
LOGIC
SETUP REGISTER
GND
CONFIGURATION REGISTER
AIN0
AIN1
OUTPUT SHIFT
REGISTER AND
12-BYTE RAM
8-BIT
ADC
AIN2
T/H
AIN3
AIN4
ANALOG
INPUT
MUX
AIN5
AIN6
REF
AIN7
AIN8
REFERENCE
4.096V (MAX1038)
2.048V (MAX1039)
MAX1038
MAX1039
AIN9
AIN10
AIN11/REF
Figure 3. MAX1038/MAX1039 Simplified Functional Diagram
ANALOG INPUT MUX
REF
C
T/H
AIN0
CAPACITIVE
DAC
AIN1
AIN2
AIN3/REF
GND
MAX1036
MAX1037
Figure 4. Equivalent Input Circuit
Analog Input Bandwidth
The MAX1036–MAX1039 feature input tracking circuitry
with a 2MHz small signal-bandwidth. The 2MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
and GND. These diodes allow the analog inputs to
V
DD
swing from (GND - 0.3V) to (V
+ 0.3V) without caus-
DD
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above V . If the analog input exceeds V
by more
DD
DD
than 50mV, the input current should be limited to 2mA.
10 ______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Table 1. Setup Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
7
NAME
REG
DESCRIPTION
Register bit. 1 = Setup Byte, 0 = Configuration Byte (Table 2).
6
SEL2
SEL1
SEL0
CLK
Three bits select the reference voltage and the state of AIN_/REF (Table 6). Default to 000 at
power-up.
5
4
3
1 = External clock, 0 = Internal clock. Defaulted to zero at power-up.
2
BIP/UNI
1 = Bipolar, 0 = Unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section).
1 = No action, 0 = Resets the configuration register to default. Setup register remains
unchanged.
1
0
RST
X
Don’t care, can be set to 1 or 0.
Single-Ended/Pseudo-Differential Input
The SGL/DIF bit of the configuration byte configures the
MAX1036–MAX1039 analog input circuitry for single-
ended or pseudo-differential inputs (Table 2). In single-
ended mode (SGL/DIF = 1), the digital conversion results
are the difference between the analog input selected by
CS[3:0] and GND (Table 3). In pseudo-differential mode
(SGL/DIF = 0), the digital conversion results are the differ-
ence between the ‘+’ and the ‘-’ analog inputs selected
by CS[3:0] (Table 4). The ‘-’ analog input signal must
remain stable within 0.5LSB ( 0.1LSB for best results)
with respect to GND during a conversion.
Digital Interface
The MAX1036–MAX1039 feature a 2-wire interface con-
sisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX1036–MAX1039 and the master
at rates up to 1.7MHz. The MAX1036–MAX1039 are
slaves that transmit and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates SCL to permit that transfer.
SDA and SCL must be pulled high. This is typically
done with pullup resistors (500Ω or greater) (see
Typical Operating Circuit). Series resistors (R ) are
S
optional. They protect the input architecture of the
MAX1036–MAX1039 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
Unipolar/Bipolar
When operating in pseudo-differential mode, the BIP/
UNI bit of the setup byte (Table 1) selects unipolar or
bipolar operation. Unipolar mode sets the differential
analog input range from zero to V
. A negative differ-
REF
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data in or out of the MAX1036–MAX1039. The data on
SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are
control signals (see the START and STOP Conditions
section). Both SDA and SCL idle high when the bus is
not busy.
ential analog input in unipolar mode causes the digital
output code to be zero. Selecting bipolar mode sets the
differential input range to
V
REF
/2, with respect to the
negative input. The digital output code is binary in
unipolar mode and two’s complement binary in bipolar
mode (see the Transfer Functions section).
In single-ended mode, the MAX1036–MAX1039 always
operate in unipolar mode regardless of the BIP/UNI
setting, and the analog inputs are internally referenced
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA, while
to GND with a full-scale input range from zero to V
.
REF
______________________________________________________________________________________ 11
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
SCL is high (Figure 5). A repeated START condition (Sr)
S
Sr
P
can be used in place of a STOP condition to leave the
bus active and in its current timing mode (see the HS-
Mode section).
SDA
SCL
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX1036–MAX1039 (slave) generate
acknowledge bits. To generate an “acknowledge,” the
receiving device must pull SDA low before the rising
edge of the acknowledge related clock pulse (ninth
pulse) and keep it low during the high period of the clock
pulse (Figure 6). To generate a “not acknowledge,” the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge related clock pulse and leaves
it high during the high period of the clock pulse.
Figure 5. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
8 9
1
2
SCL
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication at a later time.
Figure 6. Acknowledge Bits
code 0000 1XXX (X = Don’t care). After successfully
receiving the HS-mode master code, the MAX1036–
MAX1039 issues a not acknowledge, allowing SDA to be
pulled high for one clock cycle (Figure 8). After the not
acknowledge, the MAX1036–MAX1039 are in HS-mode.
The master must then send a repeated START followed
by a slave address to initiate HS-mode communication. If
the master generates a STOP condition, the
MAX1036–MAX1039 return to F/S-mode.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX1036–MAX1039 con-
tinuously wait for a START condition followed by their
slave address. When the MAX1036–MAX1039 recog-
nize their slave address, they are ready to accept or
send data. The slave address has been factory pro-
grammed and is always 1100100 for the MAX1036/
MAX1037, and 1100101 for MAX1038/ MAX1039
(Figure 7). The least significant bit (LSB) of the address
byte (R/W) determines whether the master is writing to
or reading from the MAX1036–MAX1039 (R/W = zero
selects a write condition. R/W = 1 selects a read condi-
tion). After receiving the address, the MAX1036–
MAX1039 (slave) issue an acknowledge by pulling SDA
low for one clock cycle.
Configuration/Setup Bytes (Write Cycle)
Write cycles begin with the master issuing a START
condition followed by 7 address bits (Figure 7) and 1
write bit (R/W = zero). If the address byte is successful-
ly received, the MAX1036–MAX1039 (slave) issue an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the
MSB is zero, the slave recognizes that byte as the con-
figuration byte (Table 2). The master can write either 1
or 2 bytes to the slave in any order (setup byte then
configuration byte; configuration byte then setup byte;
setup byte only; configuration byte only; Figure 9). If the
slave receives bytes successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS-mode, a STOP condition returns the
bus to F/S-mode (see the HS-Mode section).
Bus Timing
At power-up, the MAX1036–MAX1039 bus timing
defaults to fast mode (F/S-mode) allowing conversion
rates up to 44ksps. The MAX1036–MAX1039 must
operate in high-speed mode (HS-mode) to achieve
conversion rates up to 188ksps. Figure 1 shows the bus
timing for the MAX1036–MAX1039’s 2-wire interface.
HS-Mode
At power-up, the MAX1036–MAX1039 bus timing is set
for F/S-mode. The master selects HS-mode by address-
ing all devices on the bus with the HS-mode master
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
12 ______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
DEVICE
SLAVE ADDRESS
1100100
MAX1036/MAX1037
MAX1038/MAX1039
1100101
SLAVE ADDRESS
S
1
1
0
0
1
0
0
R/W
A
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7. MAX1036/MAX1037 Slave Address Byte
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S-MODE
HS-MODE
Figure 8. F/S-Mode to HS-Mode Transfer
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX1036–MAX1039 (slave) issue an
acknowledge. The master then reads from the slave.
After the master has received the results, it can issue
an acknowledge if it wants to continue reading or a not
acknowledge if it no longer wishes to read. If the
MAX1036–MAX1039 receive a not acknowledge, they
release SDA allowing the master to generate a STOP
or repeated START. See the Clock Mode and Scan
Mode sections for detailed information on how data is
obtained and converted.
Clock Mode
The clock mode determines the conversion clock, the
acquisition time, and the conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s CLK bit determines the clock mode (Table
1). At power-up, the MAX1036–MAX1039 default to
internal clock mode (CLK = zero).
Internal Clock
When configured for internal clock mode (CLK = zero),
the MAX1036–MAX1039 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX1036–MAX1039 begin tracking analog input on the
ninth falling clock edge of a valid slave address byte.
Two internal clock cycles later, the analog signal is
acquired and the conversion begins. While tracking
and converting the analog input signal, the
MAX1036–MAX1039 hold SCL low (clock stretching).
After the conversion completes, the results are stored
______________________________________________________________________________________ 13
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. 1-BYTE WRITE CYCLE
1
7
1
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS W A
A
P OR Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. 2-BYTE WRITE CYCLE
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS W A
A
A
P OR Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
in random access memory (RAM). If the scan mode is
set for multiple conversions, they all happen in succes-
sion with each additional result being stored in RAM.
The MAX1036/MAX1037 contain 8 bytes of RAM, and
the MAX1038/MAX1039 contain 12 bytes of RAM. Once
all conversions are complete, the MAX1036–MAX1039
release SCL, allowing it to be pulled high. The master
can now clock the results out of the output shift register
at a clock rate of up to 1.7MHz. SCL is stretched for a
maximum acquisition and conversion time of 7.6µs per
channel (Figure 10).
External Clock
When configured for external clock mode (CLK = 1),
the MAX1036–MAX1039 use SCL as the conversion
clock. In external clock mode, the MAX1036–MAX1039
begin tracking the analog input on the seventh falling
clock edge of a valid slave address byte. One SCL
clock cycle later, the analog signal is acquired and the
conversion begins. Unlike internal clock mode, convert-
ed data is available immediately after the slave-address
acknowledge bit. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to readdress the
device with a read command to obtain new conversion
results (Figure 11).
The device RAM contains all of the conversion results
when the MAX1036–MAX1039 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. RAM contents can be read contin-
uously. If reading continues past the last result stored in
RAM, the pointer wraps around and points to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The conversion must complete in 9ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 1ms.
The MAX1036–MAX1039 must operate in external clock
mode for conversion rates up to 188ksps.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded
from a multichannel scan.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the master
(typically a microcontroller) from the burden of running
the conversion clock.
14 ______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Table 2. Configuration Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
SGL/DIF
BIT
7
NAME
REG
DESCRIPTION
Register bit. 1 = Setup Byte (Table 1), 0 = Configuration Byte.
6
SCAN1
SCAN0
CS3
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at
power-up.
5
4
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3, 4). Default to 0000 at power-up. For MAX1036/MAX1037, CS3 and CS2 are internally
set to 0.
3
CS2
2
CS1
1
CS0
1 = single-ended, 0 = pseudo-differential (Tables 3, 4). Default to 1 at power-up (see the Single-
Ended/Pseudo-Differential Input section).
0
SGL/DIF
Automatic shutdown results in dramatic power savings,
Applications Information
particularly at slow conversion rates. For example, at a
conversion rate of 10ksps, the average supply current
for the MAX1036 is 8µA and drops to 2µA at 1ksps.
At 0.1ksps the average supply current is just 1µA (see
Average Supply Current vs. Conversion Rate in the
Typical Operating Characteristics section).
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel con-
version on AIN0 using the internal clock with V
as the
DD
reference and AIN_/REF configured as an analog input.
The RAM contents are unknown after power-up.
Reference Voltage
SEL[2:0] of the setup byte (Table 1) controls the refer-
ence and the AIN_/REF configuration (Table 6). When
AIN_/REF is configured to be a reference input or refer-
ence output (SEL1 = 1), conversions on AIN_/REF
appear as if AIN_/REF is connected to GND (see Note
2 of Tables 3 and 4).
Automatic Shutdown
SEL[2:0] of the setup byte (Tables 1 and 6) controls the
state of the reference and AIN_/REF. If automatic shut-
down is selected (SEL[2:0] = 100), shutdown occurs
between conversions when the MAX1036–MAX1039 are
idle. When operating in external clock mode, a STOP
condition must be issued to place the devices in idle
mode and benefit from automatic shutdown. A STOP
condition is not necessary in internal clock mode to ben-
efit from automatic shutdown because power-down
occurs once all contents are written to memory (Figure
10). All analog circuitry is inactive in shutdown and sup-
ply current is less than 1µA. The digital conversion
results are maintained in RAM during shutdown and are
available for access through the serial interface at any
time prior to a STOP or repeated START condition.
Internal Reference
The internal reference is 4.096V for the MAX1036/
MAX1038 and 2.048V for the MAX1037/MAX1039. SEL1
of the setup byte controls whether AIN_/REF is used for
an analog input or a reference (Table 6). When
AIN_/REF is configured to be an internal reference out-
put (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.01µF capacitor. Due to the decoupling capacitor and
the 675Ω reference source impedance, allow 80µs for
the reference to stabilize during initial power-up. Once
powered up, the reference always remains on until
reconfigured. The reference should not be used to sup-
ply current for external circuitry.
When idle, the MAX1036–MAX1039 wait for a START
condition followed by their slave address (see the
Slave Address section). Upon reading a valid address
byte, the MAX1036–MAX1039 power up. The analog
circuits do not require any wakeup time from shutdown,
whether using external or internal reference.
______________________________________________________________________________________ 15
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
R
A
CLOCK STRETCH
RESULT
A
P or Sr
t
t
CONV
ACQ
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
1
1
8
8
1
1
1
8
1
NUMBER OF BITS
S
SLAVE ADDRESS
R
A
CLOCK STRETCH
t
CLOCK STRETCH RESULT 1
A
RESULT 2
A
RESULT N
A
P OR Sr
t
t
ACQ1
ACQ2
ACQN
t
t
t
CONV1
CONV2
CONVN
NOTE: t
+ t
≤ 7.6µs PER CHANNEL.
ACQ CONV
Figure 10. Internal Clock Mode Read Cycles
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1
1
8
1
1
NUMBER OF BITS
S
R
A
A
SLAVE ADDRESS
RESULT
P OR Sr
t
t
CONV
ACQ
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
1
1
8
1
8
1
8
1
1
NUMBER OF BITS
S
R
A
A
A
A
P OR Sr
SLAVE ADDRESS
RESULT 1
RESULT 2
RESULT N
t
t
t
ACQ1
ACQ2
ACQN
t
t
t
CONV1
CONV2
CONVN
Figure 11. External Clock Mode Read Cycles
16 ______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Table 3. Channel Selection in Single-Ended Mode (SGL / DIF = 1)
CS31 CS21
CS1
0
CS0
0
AIN0 AIN1 AIN2 AIN32 AIN4
AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112 GND
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
+
+
+
+
+
-
-
-
-
-
0
1
1
0
1
1
0
0
0
1
+
-
-
-
-
-
-
-
1
0
+
1
1
+
0
0
+
0
1
+
1
0
+
1
1
+
0
0
RESERVED
RESERVED
RESERVED
RESERVED
0
1
1
0
1
1
Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero.
Note 2: When SEL1 = 1, a single-ended read of AIN3/REF (MAX1036/MAX1037) or AIN11/REF (MAX1038/MAX1039) returns GND.
______________________________________________________________________________________ 17
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Table 4. Channel Selection in Pseudo-Differential Mode (SGL / DIF = 0)
CS31
0
CS21
0
CS1
0
CS0
0
AIN0
AIN1
AIN2 AIN32
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9 AIN10 AIN112
+
-
-
0
0
0
1
+
0
0
1
0
+
-
-
0
0
1
1
+
0
1
0
0
+
-
-
0
1
0
1
+
0
1
1
0
+
-
-
0
1
1
1
+
1
0
0
0
+
-
-
1
0
0
1
+
1
0
1
0
+
-
-
1
0
1
1
+
1
1
0
0
RESERVED
RESERVED
RESERVED
RESERVED
1
1
0
1
1
1
1
0
1
1
1
1
Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero.
Note 2: When SEL1 =1, a pseudo-differential read between AIN2 and AIN3/REF (MAX1036/MAX1037) or AIN10 and AIN11/REF
(MAX1038/MAX1039) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of
1011 returns the negative difference between AIN10 and GND.
Note 3: When scanning multiple channels (SCAN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned,
while CS0 = 1 causes the odd-numbered channel-select bits to be scanned. For example, if the MAX1038/MAX1039
SCAN[1:0] = 00 and CS[3:0] = 1010, a differential read returns AIN0–AIN1, AIN2–AIN3, AIN4–AIN5, AIN6–AIN7,
AIN8–AIN9, and AIN10–AIN11. If the MAX1038/MAX1039 SCAN[1:0] = 00 and CS[3:0] = 1011, a differential read returns
AIN1–AIN0, AIN3–AIN2, AIN5–AIN4, AIN7–AIN6, AIN9–8, and AIN11–AIN10.
18 ______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Table 5. Scanning Configuration
SCAN1
SCAN0
SCANNING CONFIGURATION
Scans up from AIN0 to the input selected by CS3–CS0 (default setting).
Converts the input selected by CS3–CS0 eight times.*
0
0
0
1
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for
AIN0–AIN2, the scanning stops at AIN2 (MAX1036/MAX1037).
1
0
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6
scanning stops at AIN6 (MAX1038/MAX1039).
1
1
Converts the channel selected by CS3–CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting continues
until a not acknowledge occurs.
Table 6. Reference Voltage and AIN_/REF Format
INTERNAL REFERENCE
SEL2
SEL1
SEL0
REFERENCE VOLTAGE
AIN_/REF
STATE
0
0
1
1
1
0
1
0
0
1
X
X
0
1
X
V
Analog input
Always Off
Always Off
DD
External reference
Internal reference
Internal reference
Internal reference
Reference input
Analog input
Auto Shutdown
Always On
Analog input
Reference output
Always On
X = Don’t care.
External Reference
necting the two ground systems (analog and digital). For
lowest noise operation, ensure the ground return to the
star ground’s power supply is low impedance and as
short as possible. Route digital signals far away from sen-
sitive analog and reference inputs.
The external reference can range from 1.0V to V . For
DD
maximum conversion accuracy, the reference must be
able to deliver up to 30µA and have an output imped-
ance of 1kΩ or less. If the reference has a higher output
impedance or is noisy, bypass it to GND as close to
AIN_/REF as possible with a 0.1µF capacitor.
High-frequency noise in the power supply (V ) could
DD
influence the proper operation of the ADC’s fast
comparator. Bypass V
to the star ground with a
DD
Transfer Functions
Output data coding for the MAX1036–MAX1039 is binary
in unipolar mode and two’s complement binary in bipolar
0.1µF capacitor located as close as possible to the
MAX1036–MAX1039 power-supply pin. Minimize
capacitor lead length for best supply-noise rejection,
and add an attenuation resistor (5Ω) if the power sup-
ply is extremely noisy.
mode with 1LSB = (V
/2N) where N is the number of
REF
bits (8). Code transitions occur halfway between succes-
sive-integer LSB values. Figures 12 and 13 show the
input/output (I/O) transfer functions for unipolar and bi-
polar operations, respectively.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The INL
is measured using the endpoint method.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap config-
urations are not recommended since the layout should
ensure proper separation of analog and digital traces. Do
not run analog and digital lines parallel to each other, and
do not lay out digital signal paths underneath the ADC
package. Use separate analog and digital PC board
ground sections with only one star point (Figure 14) con-
______________________________________________________________________________________ 19
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
OUTPUT CODE
(TWO'S COMPLEMENT)
V
REF
V
REF
1LSB =
OUTPUT CODE
REF
1LSB =
256
256
REF
0...111
0...110
0...101
0...100
1...111
1...110
1...101
1...100
0...001
0...000
1...111
1...011
1...010
1...001
0...011
0...010
0...001
0...000
1...000
-128 -127 -126 -125
-1
0
+1
+124 +125 +126 +127 +128
0
1
2
3
252 253 254 255 256
'-' INPUT
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 12. Unipolar Transfer Function
Figure 13. Bipolar Transfer Function
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
SUPPLIES
3V/5V
V
LOGIC
= 3V/5V
GND
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
R* = 5Ω
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
0.1µF
edge of the sampling clock and the instant when an
actual sample is taken.
GND
V
3V/5V DGND
DD
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
DIGITAL
CIRCUITRY
MAX1036
MAX1037
MAX1038
MAX1039
*OPTIONAL
✕
SNR = (6.02 N + 1.76)dB
Figure 14. Power-Supply and Grounding Connections
20 ______________________________________________________________________________________
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
In reality, there are other noise sources besides quanti-
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
2
2
2
2
×
THD = 20 log
V
+ V + V + V
/ V
1
2
3
4
5
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
harmonics.
5
✕
SINAD (dB) = 20 log (Signal
/ Noise
)
RMS
RMS
Spurious-Free Dynamic Range
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Chip Information
MAX1036/MAX1037 TRANSISTOR COUNT: 6283
MAX1038/MAX1039 TRANSISTOR COUNT: 7257
PROCESS: BiCMOS
ENOB = (SINAD - 1.76) / 6.02
Pin Configurations
Typical Operating Circuit
5V
TOP VIEW
V
DD
AIN0
AIN1
1
2
3
4
8
7
6
5
V
DD
AIN0
*R
*R
S
S
MAX1036
MAX1037
MAX1038
MAX1039
GND
SDA
SCL
AIN1
AIN2
SDA
SCL
ANALOG
INPUTS
MAX1036
MAX1037
AIN2
AIN3/REF
AIN3/REF
GND
5V
R
P
P
SOT23
5V
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
1
16 AIN8
R
2
3
4
5
6
7
8
15 AIN9
SDA
SCL
µC
14 AIN10
13 AIN11/REF
MAX1038
MAX1039
12
V
DD
*OPTIONAL
11 GND
10 SDA
9
SCL
QSOP
______________________________________________________________________________________ 21
2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
ENG LIS H • ? ? ? ? • ? ? ? • ? ? ?
WH AT' S N EW
PRO DU CT S
S OL UT IO NS
D ESIGN
A PPNOTES
SU PPORT
B U Y
CO MPA N Y
M EMB ERS
M a x i m > P r o d u c t s > A n a l o g - t o - D i g i t a l C o n v e r t e r s
M A X 1 0 3 6 , M A X 1 0 3 6 K , M A X 1 0 3 6 L , M A X 1 0 3 6 M ,
M A X 1 0 3 7 , M A X 1 0 3 7 K , M A X 1 0 3 7 L , M A X 1 0 3 7 M ,
M A X 1 0 3 8 , M A X 1 0 3 8 K , M A X 1 0 3 8 L , M A X 1 0 3 8 M ,
M A X 1 0 3 9 , M A X 1 0 3 9 K , M A X 1 0 3 9 L , M A X 1 0 3 9 M
2 . 7 V t o 5 . 5 V , L o w - P o w e r , 4 - / 1 2 - C h a n n e l 2 - W i r e S e r i a l 8 - B i t A D C s
Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
A l l
O r d e r i n g I n f o r m a t i o n
N o t e s :
1 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
2 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n o n e
b u s i n e s s d a y .
3 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e F u l l D a t a
S h e e t o r P a r t N a m i n g C o n v e n t i o n s .
4 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e p r o d u c t
u s e s .
D
e
v
i
c
e
s
:
1
-
4
6
o
f
4
6
M
A
X
1
0
3
6
F
r
e
e
B uy
B uy
B uy
T
e
m
p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P
a
c
k
a
g
e
:
T
Y
P
E
P
I
N
S
F
O
O
T
P
R
I
N
T
Sa m p l e
D RA WI NG C OD E/ VA R *
M A X 1 0 3 6 E K A +
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 E K A
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 E K A + T
M A X 1 0 3 6 E K A - T
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X1 036K
F r e e
T e m p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : TY PE PI NS F O OTPRI NT
Sa m p l e
D RA WI NG C OD E/ VA R *
M A X 1 0 3 6 K E K A +
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 K E K A
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 K E K A + T
M A X 1 0 3 6 K E K A - T
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 L
F r e e
T e m p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : TY PE PI NS F O OTPRI NT
Sa m p l e
D RA WI NG C OD E/ VA R *
M A X 1 0 3 6 L E K A +
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
M A X 1 0 3 6 L E K A
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
M A X 1 0 3 6 L E K A - T
M A X 1 0 3 6 L E K A + T
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
M A X 1 0 3 6 M
F r e e
B uy
B uy
B uy
B uy
T e m p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : TY PE PI NS F O OTPRI NT
Sa m p l e
D RA WI NG C OD E/ VA R *
M A X 1 0 3 6 M E K A +
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 M E K A
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
M A X 1 0 3 6 M E K A - T
M A X 1 0 3 6 M E K A + T
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : S e e d a t a s h e e t
M a t e r i a l s A n a l y s i s
M A X 1 0 3 7
F r e e
T e m p
R o H S/ L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : TY PE PI NS F O OTPRI NT
Sa m p l e
D RA WI NG C OD E/ VA R *
M A X 1 0 3 7 E K A +
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C + 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
M A X 1 0 3 7 E K A
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 1 0 3 7 E K A - T
M A X 1 0 3 7 E K A + T
S O T - 2 3 ; 8 p i n ; 9 m m
D w g : 2 1 - 0 0 7 8 G ( P D F )
U s e p k g c o d e / v a r i a t i o n : K 8 C - 6 *
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MAX1036MEKA 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
MAX1036MEKA+ | MAXIM | ADC, Successive Approximation, 8-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, PDSO8, LEAD FREE, MO-178, SOT-23, 8 PIN | 获取价格 | |
MAX1036MEKA+T | MAXIM | 暂无描述 | 获取价格 | |
MAX1036MEKA-T | MAXIM | 暂无描述 | 获取价格 | |
MAX1036MEKA-T | ROCHESTER | 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MO-178BA, SOT-23, 8 PIN | 获取价格 | |
MAX1036_09 | MAXIM | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs | 获取价格 | |
MAX1037 | MAXIM | 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs | 获取价格 | |
MAX1037 | ADI | 2.7V至5.5V、低功耗、4/12通道、2线串口、8位ADC | 获取价格 | |
MAX1037EKA | MAXIM | ADC, Successive Approximation, 8-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, PDSO8, MO-178, SOT-23, 8 PIN | 获取价格 | |
MAX1037EKA+T | MAXIM | 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs | 获取价格 | |
MAX1037EKA- | MAXIM | 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs | 获取价格 |
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